ImprovementsforNewPeak/ValleyHoldUnits
1. Changed to updated 16 bit processor with considerably more computing power. 2. Analogue to Digital speed increased to 100 ksps and resolution increased to 12 bits. 3. Input and output signal range selection and configuration done using DIP switches and firmware – much easier configuration of input and outputs and more flexible. 4. Standard inputs (DIP switch selectable): 4‐20 mA, 0‐20 mA, 0‐100 mV, 0‐1 V, 0‐10 V, 0‐100 V, ±1 V, ±10 V. 5. We have added a “Loop Powered” mA input option for 22 mA at 15 V. 6. Standard outputs (DIP switch selectable): 4‐20 mA, 0‐20 mA, 0‐5 V, 0‐10 V, ±10 V. Each output can be different if required. 7. Resistance inputs can now be catered for using a controlled current source to provide a constant current for the resistance input. 8. Many more LEDs to indicate various states of inputs and outputs. 9. Push button for user configuration and “soft trimpots”. Filename: Peak_Valley Hold Unit Design Notes.docx danntech – PROCESS INSTRUMENTATION 2014 ©
Date: 20 October 2014 Version: 2.00 Page 2 of 7 10. Isolated RS232/TTL interface for software configurations in the future. 11. Various operating options now selected also using DIP switches (not solder links). 12. DIP switches accessible beneath decal covers on left side of unit. 13. Updated user manual will show how to do all the configuration and set‐up. 14. The operation of the new unit, besides adding more flexibility and features, will perform at least as well as the previous (old) version. 15. We provide reset function of the captured peak and valley outputs using the digital inputs. Din #1 for the Peak output, Din #2 for the Valley output. There will be a DIP switch option to use this. 16. The two digital outputs will be used to indicate that a peak or valley has been captured and it will remain active while the peak or valley is being held. 17. We will add a “window setting” where when the input is within this window no digital output of peak or valley will be indicated. 18. The digital outputs can either be signal relays (about 20 mS response time) or opto‐coupler outputs (< 1 mS). Please indicate your preference. 19. We expect the minimum detectable input pulse width to be 1 mS or less (I will expect about 500 µS from my initial tests). The new processor has some internal analog threshold detection which may allow us to detect much shorter pulses in the future. 20. We expect the Input/Output delay time to be 1 mS or less (my initial tests show about 400 µS). Figure 1 The new PVHU will look similar to this. Filename: Peak_Valley Hold Unit Design Notes.docx danntech – PROCESS INSTRUMENTATION 2014 ©
Date: 20 October 2014 Version: 2.00 Page 3 of 7