Introduction to
CMOS VLSI
Design
Slides adapted from:
N. Weste, D. Harris, CMOS VLSI Design,
© Addison-Wesley, 3/e, 2004
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Outline
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A Brief History
MOS transistors
CMOS Logic
CMOS Fabrication and Layout
Design Flow
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System Design
Logic Design
Physical Design
Design Verification
Fabrication, Packaging and Testing
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1
CMOS Fabrication
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CMOS transistors are fabricated on a thin silicon
wafer that serve as both a mechanical support
and electrical common point called substrate
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
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Inverter Cross-section
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Typically use p-type substrate for nMOS
transistors
Requires n-well for body of pMOS transistors
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Well and Substrate Taps
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Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts /
taps
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Inverter Mask Set
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Transistors and wires are defined by masks
Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
substrate tap
pMOS transistor
well tap
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Detailed Mask Views
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n well
Six masks
z n-well
z Polysilicon
z n+ diffusion
z p+ diffusion
z Contact
z Metal
Polysilicon
n+ Diffusion
p+ Diffusion
Contact
Metal
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Fabrication Steps
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Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
z Cover wafer with protective layer of SiO2 (oxide)
z Remove layer where n-well should be built
z Implant or diffuse n dopants into exposed wafer
z Strip off SiO2
p substrate
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4
Photoresist
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Spin on photoresist
Photoresist is a light-sensitive organic polymer
z Softens where exposed to light
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Photoresist
SiO2
p substrate
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Lithography
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Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
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5
Etch
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Etch oxide with hydrofluoric acid (HF)
z Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
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n-well
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n-well is formed with diffusion or ion implantation
Diffusion
z Place wafer in furnace with arsenic gas
z Heat until As atoms diffuse into exposed Si
Ion Implanatation
z Blast wafer with beam of As ions
z Ions blocked by SiO2, only enter exposed Si
SiO2
n well
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Strip Oxide
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Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of
steps
n well
p substrate
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Polysilicon
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Deposit very thin layer of gate oxide
z < 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
z Place wafer in furnace with Silane gas (SiH4)
z Forms many small crystals called polysilicon
z Heavily doped to be good conductor
Polysilicon
Thin gate oxide
p substrate
n well
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Polysilicon Patterning
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Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
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Self-Aligned Process
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Use oxide and masking to expose where n+
dopants should be diffused or implanted
N-diffusion forms nMOS source, drain, and nwell contact
n well
p substrate
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8
N-diffusion
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Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
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N-diffusion cont.
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Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n+
n+
n+
n well
p substrate
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N-diffusion cont.
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Strip off oxide to complete patterning step
n+
n+
n+
n well
p substrate
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P-Diffusion
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Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact
p+ Diffusion
p+
n+
n+
p substrate
p+
p+
n+
n well
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Contacts
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Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
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Metalization
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Sputter on aluminum over whole wafer, filling the contacts
as well
Pattern to remove excess metal, leaving wires
M etal
Metal
Thick field oxide
p+
n+
n+
p+
p+
n well
p substrate
n+
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Layout
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Chips are specified with set of masks
Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)
Feature size f = distance between source and
drain
z Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing
design rules
Express rules in terms of λ = f/2
z E.g. λ = 0.3 µm in 0.6 µm process
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Layout Design Rules
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Design Rules Summary
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Metal and diffusion have minimum width and spacing of 4λ
Contacts are 2λ x 2λ and must be surrounded by 1λ on the layers
above and below
Polysilicon uses a width of 2λ
Polysilicon overlaps diffusions by 2λ where a transistor is desired
and has spacing or 1λ away where no transistor is desired
Polysilicon and contacts have a spacing of 3λ from other
polysilicon or contacts
N-well surrounds pMOS transistors by 6λ and avoid nMOS
transistors by 6λ
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Gate Layout
ƒ Layout can be very time consuming
ƒ Design gates to fit together nicely
ƒ Build a library of standard cells
ƒ Standard cell design methodology
ƒ VDD and GND should abut (standard height)
ƒ Adjacent gates should satisfy design rules
ƒ nMOS at bottom and pMOS at top
ƒ All gates include well and substrate contacts
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Inverter Layout
ƒ Transistor dimensions specified as W / L ratio
- Minimum size is 4λ / 2λ, sometimes called 1 unit
- In f = 0.6 µm process, this is 1.2 µm wide,
0.6 µm long
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Example: Inverter Standard Cell Layout
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Example: 3-input NAND Standard Cell Layout
ƒ Horizontal n-diffusion and
p-diffusion strips
ƒ Vertical polysilicon gates
ƒ Metal1 VDD rail at top
ƒ Metal1 GND rail at bottom
ƒ 32 λ by 40 λ
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Stick Diagrams
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Stick diagrams help plan layout quickly
z Need not be to scale
z Draw with color pencils or dry-erase markers
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Wiring Tracks
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A wiring track is the space required for a wire
z 4 λ width, 4 λ spacing from neighbor = 8 λ pitch
Transistors also consume one wiring track
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Well spacing
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Wells must surround transistors by 6 λ
z Implies 12 λ between opposite transistor flavors
z Leaves room for one wire track
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Area Estimation
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Estimate area by counting wiring tracks
z Multiply by 8 to express in λ
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Design Challenges
ƒ The greatest challenge in modern VLSI is not in
designing the individual transistors but in managing
system complexity
ƒ Modern System-on-Chip designs use:
ƒ Many millions (soon billions!) of transistors
ƒ Tens to hundreds of engineers
ƒ How to cope with Complexity ?
ƒ Abstraction Level
ƒ Structured Design
ƒ Design Flow
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Design Abstraction Levels
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Structured Design Tenets
ƒ Hierarchy
ƒ Divide and Conquer
ƒ Regularity
ƒ Reuse modules wherever possible
ƒ Ex: standard cell library
ƒ Modularity
ƒ Well-formed interface allows modules to be treated as
black boxes
ƒ Locality
ƒ Physical and Temporal
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Design Flow
ƒ Architecture: User’s perspective, what does it do?
ƒ Instruction set, MIPS, x86, Alpha, PIC, ARM, …
ƒ Microarchitecture
ƒ Single cycle, multi cycle, pipelined, superscalar?
ƒ Logic: how are functional blocks constructed ?
ƒ Ripple carry, carry look ahead, carry select adders
ƒ Circuit: how are transistors used ?
ƒ Static CMOS, pass transistors, domino logic, …
ƒ Physical: chip layout
ƒ Datapaths, memories, random logic
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Design Flow: Gajski’s Y-Diagram
The design process can be viewed
as making transformations from
one domain to another while
maintaining the equivalency of the
domains
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Architecture: MIPS example
ƒ Instruction Set
ƒ Instruction encoding formats
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Architecture: MIPS example cont.
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Microarchitecture: MIPS example
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Logic Design: MIPS example
ƒ Start at the top level
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Define the top-level interface
Top level block diagram
Hierarchically decompose top level into units
Design the units (e.g. HDL)
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Logic Design: MIPS top level block diagram
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Logic Design: MIPS Hierarchy
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Logic Design using HDLs
ƒ Hardware Description Languages
ƒ Widely used in logic design
ƒ Verilog and VHDL
ƒ Describe hardware using code
ƒ Document logic functions
ƒ Simulate logic before building
ƒ Synthesize code into gates and layout
ƒ Requires a library of standard cells
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Circuit Design
ƒ How should logic be implemented?
ƒ NANDs and NORs vs. ANDs and ORs?
ƒ Fan-in and fan-out?
ƒ How wide should transistors be?
ƒ These choices affect speed, area, power
ƒ Logic synthesis makes these choices for you
ƒ Good enough for many applications
ƒ But when a system has critical requirement
Hand-crafted circuits are still better
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Example: Full Adder
Transistors? Gate Delays?
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Example: Carry circuit
ƒ VERILOG:
assign cout = (a&b) | (a&c) | (b&c);
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Gate-level Netlist
module carry(input a, b, c,
output cout)
wire
and
and
and
or
g1
x, y, z;
g1(x, a,
g2(y, a,
g3(z, b,
g4(cout,
x
a
b
g2
b);
c);
c);
x, y, z);
g4
y
a
c
cout
g3
z
b
c
endmodule
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Transistor-Level Netlist
module carry(input
a, b, c, output cout)
wire
i1, i2, i3, i4, cn;
tranif1
tranif1
tranif1
tranif1
tranif1
tranif0
tranif0
tranif0
tranif0
tranif0
tranif1
tranif0
n1(i1, 0, a);
n2(i1, 0, b);
n3(cn, i1, c);
n4(i2, 0, b);
n5(cn, i2, a);
p1(i3, 1, a);
p2(i3, 1, b);
p3(cn, i3, c);
p4(i4, 1, b);
p5(cn, i4, a);
n6(cout, 0, cn);
p6(cout, 1, cn);
endmodule
a
p1
c
c
a
n1
b p2
p3 i3
b
n3 i1
b n2
a
a
b
p4
i4
p5
n5
i2
n4
cn
p6
cout
n6
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SPICE Netlist
.SUBCKT CARRY A B C COUT VDD GND
MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P
MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P
MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P
MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P
MP1 I3 A VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1 P
MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P
MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P
MP4 I4 B VDD VDD PMOS W=2U L=0.18U AD=0.3P AS=1P
MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P
MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P
MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P
CI1 I1 GND 2FF
CI3 I3 GND 3FF
CA A GND 4FF
CB B GND 4FF
CC C GND 2FF
CCN CN GND 4FF
CCOUT COUT GND 2FF
.ENDS
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Physical Design
ƒ Floorplan
ƒ Standard cells
ƒ Place & route
ƒ Datapaths
ƒ Slice planning
ƒ Area estimation
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MIPS floorplan
Does the design fit the chip
area budgeted ?
Estimates area of major units
and defines their relative
placement
Estimate wire lengths
Estimates wiring congestion
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MIPS layout
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Taxonomy of On-Chip structures
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Random logic
Data paths
Arrays
Analog
Input/output (I/O)
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Synthesized MIPS Controller
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Hand-Crafted MIPS Datapath
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Standard Cells
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Synthesized MIPS
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Area Estimation
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Need area estimates to make floorplan
z Compare to another block you already designed
z Or estimate from transistor counts
z Budget room for large wiring tracks
Some cell library vendor specify cell layout densities in Kgates/mm2
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Design Verification
ƒ Fabrication is slow & expensive
ƒ MOSIS 0.6µm masks: $1000, 3 months
ƒ State of art masks (130nm): $1M, 1 month
ƒ Debugging chips is very hard
ƒ Limited visibility into operation
ƒ Prove design is right before building!
ƒ System simulation (C/C++)
ƒ Logic simulation (HDL testbench)
ƒ Circuit simulation / formal verification
ƒ Layout vs. schematic comparison
ƒ Design & electrical rule checks
ƒ Verification is > 50% of effort on most chips !
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Fabrication
ƒ Tapeout final layout
ƒ Formats for mask descriptions:
CIF (academia) and GDS II (industry)
ƒ Fabrication
ƒ 6, 8, 12” wafers (bare wafer costs $1000-$5000)
ƒ Optimized for throughput, not latency (turnaround times up to 10
weeks !)
ƒ Cut into individual dice
ƒ Fabs cost billions of dollars and become obsolete in a few years
ƒ Fabless semiconductor companies
ƒ Manufacturing Companies: TSMS, UMC, IBM
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Packaging
ƒ
Bond gold wires from die I/O pads to package
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Testing
ƒ Test that chip operates
ƒ Design errors
ƒ Manufacturing errors
ƒ A single dust particle or wafer defect kills a die
ƒ Yields from 90% to < 10%
ƒ Depends on die size, maturity of process
ƒ Test each part before shipping to customer
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Summary
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Many chip designers spend much of their time
specifying circuits with HDL and seldom look at
the actual transistor
However:
Chip Design is not software engineering
z It requires a fundamental understanding of
circuit and physical design
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The best way to learn VLSI design is by doing it
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Summary cont.
Now you know everything to start designing a
simple chip !
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