EV10AS180x-EB Evaluation Board
..............................................................................................
User Guide
Table of Contents
Section 1
Introduction ........................................................................................... 1-1
1.1
1.2
Scope ........................................................................................................1-1
Description ................................................................................................1-1
Section 2
Hardware Description ........................................................................... 2-1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Board Structure .........................................................................................2-1
Analogue Inputs/Clock Input .....................................................................2-2
Digital Output Data....................................................................................2-3
RSTN ........................................................................................................2-3
SA, RSx, TMx, SDA, SDAEN, GA, OA, DECN, Diode..............................2-4
Ground Layers ..........................................................................................2-4
Power Supplies .........................................................................................2-4
Section 3
Operating Characteristics ..................................................................... 3-1
3.1
3.2
3.3
Introduction ...............................................................................................3-1
Operating Procedure.................................................................................3-1
Electrical Characteristics...........................................................................3-2
Section 4
Application Information ......................................................................... 4-1
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Analogue Input ..........................................................................................4-1
Clock Input ................................................................................................4-1
RESETN input...........................................................................................4-2
SA, GA, OA, SDA and SDAEN Commands..............................................4-2
RSx, TMx and DECN Commands.............................................................4-6
Output Data...............................................................................................4-8
Diode for Junction Temperature Monitoring............................................4-10
Test Bench Description ...........................................................................4-10
Section 5
Ordering Information ............................................................................. 5-1
Section 6
Appendix............................................................................................... 6-1
6.1
6.2
EV10AS180x-EB Evaluation Kit User Guide
EV10AS180x-EB Electrical Schematics....................................................6-1
EV10AS180x-EB Board Layers ................................................................6-6
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Table of Contents
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EV10AS180x-EB Evaluation Kit User Guide
Section 1
Introduction
1.1
Scope
The EV10AS180x-EB Evaluation Kit is designed to facilitate the evaluation and characterization of the EV10AS180x 10-bit 1.5 GSps ADC in AC coupled mode.
The EV10AS180x-EB Evaluation Kit includes:
„ The 10-bit 1.5 GSps ADC Evaluation board with EV10AS180x ADC soldered on the
PCB.
„ A CD ROM with the datasheet and device User Guide.
The User Guide describes the use the EV10AS180x-EB Evaluation Kit as an evaluation
and demonstration platform and provides guidelines for its proper use.
1.2
Description
The EV10AS180x-EB Evaluation board is very straightforward as it implements e2v
EV10AS180x 10-bit 1.5 GSps ADC device, SMA connectors for the sampling clock,
analogue inputs and reset input accesses and 2.54 mm pitch connectors compatible
with high speed acquisition system probes.
Thanks to its user-friendly interface, the EV10AS180x-EB Kit enables to test all the functions of the EV10AS180x 10-bit 1.5 GSps ADC.
To achieve optimal performance, the EV10AS180x-EB Evaluation board was designed
in a 6-metal-layer board using FR4 HTG epoxy dielectric material (200 µm, ISOLA
IS410 featuring a resin content of 45%). The board implements the following devices:
„ The 10-bit 1.5 Gsps ADC Evaluation board with the EV10AS180x ADC soldered.
„ SMA connectors for CLK, CLKN, VIN, VINN, RESETN signals.
„ 2.54 mm pitch connectors for the digital outputs, compatible with high speed
acquisition system probes.
„ Banana jacks (2 mm) for the power supply accesses, the Die junction Temperature
monitoring functions.
„ Jumpers for SDAEN, RS0, RS1, TM0, TM1, DECN, SDA, SA, OA, GA.
„ Potentiometers for SA, OA, GA, SDA.
The board dimensions are 260 mm × 220 mm.
The board comes fully assembled and tested, with the EV10AS180x installed.
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Introduction
Figure 1-1. EV10AS180x-EB Evaluation Board Simplified Schematic
SA
GA
OA
Diode
Connector
port A
RSTN
CLK
Connector
port B
PIN 1
CLKN
Connector DR DRN
VIN
VINN
Connector
port C
AGND
SDAEN
AGND
RS0
RS1
TM0
TM1
DECN
Connector
port D
SDA
VCC5
VCC3
3
V
3
D
G
N
D
V
C
C
O
D
G
N
D
As shown in Figure 1-1 on page 2, different power supplies are required:
„ VCC5 = 5.2V analogue positive power supply (referenced to AGND).
„ VCC3 = 3.3V analogue positive power supply (referenced to AGND).
„ VCCO = 2.5V digital output power supply (referenced to DGND).
„ 3.3V board supply for control functions (referenced to DGND).
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EV10AS180x-EB Evaluation Kit User Guide
Section 2
Hardware Description
2.1
Board Structure
In order to achieve optimum full speed operation of the EV10AS180x 10-bit 1.5 Gsps
ADC, a multi-layer board structure was retained for the evaluation board. Six copper layers are used, dedicated to the signal traces, ground planes and power supply planes.
The board is made in FR4 HTG epoxy dielectric material (ISOLA IS410).
Board characteristics:
„ RO4003 for the top and bottom layers, FR4 HTG for the internal layers
„ Dielectric thickness: 200 µm
„ Dielectric constant: 3.38
„ Lands diameter: 750 µm
„ GND Via/Land Diameter: 200 µm
The following table gives a detailed description of the board's structure.
Table 2-1. Board Layer Thickness Profile
Layer
Characteristics
Layer 1
Copper layer
Copper thickness = 40 mm (with NiAu finish)
AC signals traces = 50Ω microstrip lines
DC signals traces
FR4 HTG / dielectric layer
Layer thickness = 200 µm
Layer 2
Copper layer
Copper thickness = 18 µm
AGND, DGND (separate planes)
FR4 HTG / dielectric layer
Layer thickness = 349 µm
Layer 3
Copper layer
Copper thickness = 18 µm
Power planes = VCC5, VCC3, VCCO
FR4 HTG / dielectric layer
Layer thickness = 350 µm
Layer 4
Copper layer
Copper thickness = 18 µm
Power planes = 3V3
FR4 HTG / dielectric layer
Layer thickness = 350 µm
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Hardware Description
Table 2-1. Board Layer Thickness Profile (Continued)
Layer
Characteristics
Layer 5
Copper layer
Copper thickness = 18 µm
AGND, DGND (separate planes)
FR4 HTG / dielectric layer
Layer thickness = 200 µm
Layer 6
Copper layer
Copper thickness = 40 µm (with NiAu finish)
AC signals traces = 50Ω microstrip lines
DC signals traces
The board is 1.6 mm thick.
The Clock, analogue inputs, reset and ADC functions occupy the top metal layer. The
digital data output signals occupy the top and bottom layers.
The Ground planes occupy layer 2 and 5.
Layer 3 and 4 are dedicated to the power supplies.
2.2
Analogue
Inputs/Clock
Input
The differential clock and analogue inputs are provided by SMA connectors (Reference:
JOHNSON 142-0701-851-6).
Both pairs are AC coupled using 10 nF capacitors.
Special care was taken for the routing of the analog and clock input signals for optimum
performance in the high frequency domain:
„ 50Ω lines matched to ±0.1 mm (in length) between VIN and VINN or CLK and CLKN.
„ 1270 µm between two differential pairs.
„ 400 µm line width.
„ 40 µm thickness.
„ 870 µm diameter hole in the ground layer below the VIN and VINN or CLK and CLKN
ball footprints.
„ In addition, the lines for VIN, VINN and CLK, CLKN are matched to one another within
±1mm.
„ A clearance in the ground plane below the CLK, CLKN and VIN, VINN package lands
is necessary.
Note:
These values have been calculated with RO4003 dielectric material.
Figure 2-1. Board Layout for the Differential Analog and Clock Inputs with RO4003
e = 40 µm
400 µm
870 µm
RO4003
400 µm
200 µm
AGND
1270 µm
Note:
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The analogue inputs and clock inputs are AC coupled with 10 nF very close to the SMA
connectors.
EV10AS180x-EB Evaluation Kit User Guide
Hardware Description
Figure 2-2. Recommended Clearance Under CLK, CLKN, and VIN, VINN on the
Ground Plane
1270 µm
1400 µm
2.3
Digital Output
Data
The high speed differential output signals (digital output, clock output), are routed in parallel with 50Ω impedance, 370 µm width and a pitch of 0.77 mm.
Max difference between any two signals = ±1.5mm.
Max difference between longest and shortest data per port = ±1mm
Max difference between two signals of the same differential pair (Xi, XiN) = ±0.5mm
(where X = A, B, C or D, i = 0…9).
Note:
These values have been calculated with RO4003 dielectric material.
Figure 2-3. Recommended Routing on RO4003 for Digital Output Data Signals
e = 40 µm
370 µm
400 µm
370 µm
RO4003
200 µm
DGND
770 µm
2.4
RSTN
The RSTN signal is a single-ended signal with 50Ω impedance.
Figure 2-4. Recommended Routing on RO4003 for RSTN Signal
e = 40 µm
430 µm
RO4003
200 µm
DGND
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Hardware Description
2.5
SA, RSx, TMx,
SDA, SDAEN,
GA, OA, DECN,
Diode
These are "static" signals. They are routed in single-ended 50Ω impedance.
Figure 2-5. Recommended Routing on RO4003 for Static Signal
e = 40 µm
430 µm
RO4003
200 µm
DGND
2.6
Ground Layers
There are 2 separated planes for the AGND and the DGND on the PCB. These planes
must be reunited via 0Ω resistors. Only the input clock and analogue input are referenced to AGND, the other parts of the ADC are referenced to DGND.
Important note: AGND and V CCO are not superimposed in order to avoid coupling
effects. VCC3 and VCC5 are referenced to AGND while VCCO is referenced to DGND.
2.7
Power Supplies
Layers 3 and 4 are dedicated to power supply planes:
„ VCC5: ADC Analog part supply (VCC5 = 5.2V)
„ VCC3: ADC Analogue Core and Digital parts supply (VCC3 = 3.3V)
„ VCCO: ADC Output buffers supply (VCCO = 2.5V)
„ 3.3V: external reference for GA, OA, SA and SDA commands.
The supply traces are low impedance and are surrounded by two ground planes (layer 2
and 5).
Each incoming power supply is bypassed at the banana jack by a 1 µF Tantalum capacitor in parallel with a 100 nF chip capacitor.
Each power supply is decoupled as close as possible to the EV10AS180x device by
10 nF in parallel with 100 pF surface mount chip capacitors.
Note:
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The decoupling capacitors are superimposed with the 100 pF capacitor mounted first.
EV10AS180x-EB Evaluation Kit User Guide
Section 3
Operating Characteristics
3.1
Introduction
This section describes a typical configuration for operating the EV10AS180x 10-bit 1.5
Gsps ADC, evaluation board.
The analogue input signals and the sampling clock signal should be accessed in a differential fashion. Band pass filters should also be used to optimize the performance of
the ADC both on the analog input and on the clock.
It is necessary to use a very low jitter source for the clock signal (recommended maximum jitter = 225 fs rms).
Note:
3.2
Operating
Procedure
The analogue inputs and clock are AC coupled on the board.
1. Connect the power supplies and ground accesses through the dedicated banana
jacks.
VCC5 = 5.2V, VCC3 = 3.3V, VCCO = 2.5V and board supply = 3.3V
2. Connect the clock input signals.
The clock input level is typically 4 dBm and should not exceed 10 dBm (into 100
differential).
The clock frequency should be set to 1.5 GHz (for operation in 1:2 or 1:4 DEMUX
Ratio).
3. Connect the analogue input signals (the board has been designed to allow only
AC coupled analogue inputs).
Use a low-phase noise High Frequency generator as well as a band pass filter to
optimize the analogue input performance.
The analogue input Full Scale is 500mV peak-to-peak around zero (analogue
input providing the Input common mode). It is recommended to use the ADC with
an input signal of –12 dBFS max (to avoid saturation of the ADC).
4. Connect the high speed acquisition system probes to the output connectors.
The digital data are differentially terminated on-board (100Ω) however, they can
be probed either in differential.
5. Switch on the ADC power supplies (recommended power up sequence: simultaneous or in the following order: VCC3 = 3.3V, VCC5 = 5.2V, VCCO = 2.5V and board
supply 3.3V).
6. Turn on the RF clock generator.
7. Turn on the RF signal generator.
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Operating Characteristics
The EV10AS180x-EB evaluation board is now ready for operation.
Note:
3.3
Electrical
Characteristics
An external reset (RSTN) SMA connector or switch is available in case it is necessary to
reset the ADC during operation (it is not mandatory to perform an external reset on the
ADC for proper operation of the ADC as a power up reset already implemented). This
reset is 2.5V CMOS compatible. It is active low (inactive by default on the board).
Values in the table below are given for information only, for more accurate values refer
to datasheet.
Table 3-1. Recommended Conditions of Use
Parameter
Symbol
Power supplies
Comments
Typ
Unit
VCC5
5.2
V
VCC3
3.3
V
VCC0
2.5
V
Differential analog input
voltage (Full Scale)
VIN – VINN
100Ω differential
500
mVpp
Clock input power level
(Ground common mode)
PCLK PCLKN
100Ω differential input
4
dBm
Unless otherwise stated, requirements apply over the full operating temperature range
(for performance) and at all power supply conditions.
Table 3-2. Electrical Characteristics
Parameter
Symbol
RESOLUTION
Min
Typ
Max
10
ESD CLASSIFICATION
> 1000V (HBM model)
Unit
Test level
bit
1,6
V
NA
POWER REQUIREMENTS
Power Supply voltage
- Analog
VCC5
5.0
5.2
5.5
V
- Analog Core and Digital
VCC3
3.15
3.3
3.45
V
- Output buffers
VCCO
2.4
2.5
2.6
V
1,6
Power Supply current in 1:1 DEMUX Ratio
- Analog
- Analog Core and Digital
- Output buffers
I_VCC5
I_VCC3
I_VCCO
71
85
mA
300
330
mA
100
110
mA
I_VCC5
I_VCC3
I_VCCO
71
85
mA
312
335
mA
137
160
mA
I_VCC5
I_VCC3
I_VCCO
71
85
mA
325
355
mA
216
240
mA
1,6
Power Supply current in 1:2 DEMUX Ratio
- Analog
- Analog Core and Digital
- Output buffers
1,6
Power Supply current in 1:4 DEMUX Ratio
- Analog
- Analog Core and Digital
- Output buffers
1,6
Power dissipation
- 1:1 Ratio with standard LVDS output swing
PD
1.6
1.9
W
- 1:2 Ratio with standard LVDS output swing
PD
1.75
2.0
W
- 1:4 Ratio with standard LVDS output swing
PD
1.9
2.3
W
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1,6
EV10AS180x-EB Evaluation Kit User Guide
Operating Characteristics
Table 3-2. Electrical Characteristics (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
Test level
LVDS Data and Data Ready Outputs
Logic compatibility
LVDS differential
Output Common Mode
Differential output
(1)
VOCM
1.125
1.25
1.375
V
1,6
(1)(2)
VODIFF
250
350
450
mVp
1,6
(3)
VOH
1.25
–
–
V
1,6
VOL
–
–
1.25
V
1,6
Output level “High”
Output level “Low”
(3)
Output data format
Binary
1,6
ANALOG INPUT
Input type
AC coupled
Analog Input Common Mode (for DC coupled input)
Full scale input voltage range (differential mode)
3.1
V
VIN
–125
+125
mVp
VINN
–125
+125
mVp
1,6
Full scale analog input power level
PIN
–5
dBm
1,6
Analog input capacitance (die only)
CIN
0.3
pF
5
Input leakage current (VIN = VINN = 0V)
IIN
50
µA
5
Analog Input resistance (Differential)
RIN
Ω
1,6
V
1,6
96
100
104
CLOCK INPUT (CLK, CLKN)
Input type
Clock Input Common Mode (for DC coupled clock)
DC or AC coupled
VICM
2
Clock Input power level (low phase noise
sinewave input) at 1.5 GHz
PCLK
0
4
+7
dBm
4
±447
±708
±1000
mVp
4
pF
4
Ω
4
V
1,6
V
1,6
100Ω differential
Clock input swing (differential voltage) at 1.5 GHz
VCLK
VCLKN
Clock input capacitance (die only)
CCLK
Clock Input resistance (Differential)
RCLK
0.3
94
98
102
RSTN (active low)
Logic compatibility
2.5V CMOS compatible
Input level “High”
VIH
Input level “Low”
VIL
2.0
0.4
DIGITAL INPUTS (RS0, RS1, DECN, SDAEN, TM1, TM0)
Logic low
- Resistor to ground
RIL
0
10
Ω
- Voltage level
VIL
–
0.5
V
- Input current
IIL
–
450
µA
- Resistor to ground
RIH
10k
infinite
Ω
- Voltage level
VIH
2.0
–
V
- Input current
IIH
–
150
µA
1,6
Logic high
1,6
OFFSET, GAIN & SAMPLING DELAY ADJUST SETTINGS (OA, GA, SDA)
Min voltage for minimum Gain, Offset or SDA
EV10AS180x-EB Evaluation Kit User Guide
Analog_min
2*Vcc3/3 – 0.5
V
1,6
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Operating Characteristics
Table 3-2. Electrical Characteristics (Continued)
Parameter
Max
Unit
Test level
Analog_max
2*Vcc3/3
+ 0.5
V
1,6
Input current for min setting
Imin
200
µA
1,6
Input current for nominal setting
Inom
50
µA
1,6
Input current for max setting
Imax
200
µA
1,6
Smax
2*Vcc3/3
Max voltage for maximum Gain, Offset or SDA
Symbol
Min
Typ
ANALOG SETTINGS (SA)
SA voltage for default swing value
1,6
SA voltage for minimum swing value
Smin
Input current (low, for default swing value
Imin
50
µA
1,6
Input current (high) for min swing value
Imax
150
µA
1,6
Notes:
2*Vcc3/3 – 0.5
1,6
1. Assuming 100Ω termination ASIC load.
2. VODIFF can be lowered down to 100 mV with SA pin to reduce power consumption.
3. VOH min and VOL max can never be 1.25V at the same time when VODIFFmin.
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EV10AS180x-EB Evaluation Kit User Guide
Section 4
Application Information
4.1
Analogue Input
The analogue input (VIN, VINN) are entered in differential AC coupled mode as
described in Figure 4-1.
It is recommended to use a differential source to drive the analogue inputs of this ADC
(external balun or differential amplifier). Please refer to Section Test Bench Description
for more information.
In order to optimize the performance of the ADC, it is also recommended to use a band
pass filter on the analogue input path.
Figure 4-1. Differential Analogue Inputs Implementation
10 nF
VIN
VIN
EV10AS180x
VNN
VINN
10 nF
4.2
Clock Input
It is recommended to use a differential source to drive the clock input. The clock is AC
coupled via 10 nF capacitors as described in Figure 4-2. Please refer to Section Test
Bench Description for more information.
Figure 4-2. Clock Input Implementation
10 nF
CLK
CLK
EV10AS180x
CLKN
CLKN
10 nF
The jitter performance on the clock is crucial to obtain optimum performance from the
ADC. We thus recommend to use a very low phase noise clock and to filter the clock
signal if a fixed frequency is used.
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Application Information
4.3
RESETN input
The RESETN signal can be applied by using a switch (SW5):
„ By default, RESETN is floating, it is not active, the ADC is in normal mode;
„ When the switch is activated, it connects RESETN to ground, which performs a reset
on the ADC (reset of the clock circuitry, after reset, the first data will be seen on port
A).
It is also possible to apply a signal via the SMA connector, providing R4 is connected (0
ohm) and R3 is removed.
The reset signal is implemented as illustrated in Figure 4-3.
Figure 4-3. RESETN Input Implementation
EV10AS180x
RESETN
R4
0Ω
NC
RESETN
R3
0Ω
R1
0Ω
DGND
4.4
SA, GA, OA, SDA
and SDAEN
Commands
4.4.1
GA and OA
Commands
These signals are connected by default via their respective jumper to the command middle value (ie. 2 × VCC3/3 = 2.2V).
When the jumper is removed, it is possible to tune the OA and GA commands between
(2 × VCC3/3 – 0.5V) to (2 × VCC3/3 + 0.5V).
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EV10AS180x-EB Evaluation Kit User Guide
Application Information
Figure 4-4. GA and OA Commands Implementation
3.3V
3.3V
3.3V
R12
R14
P1
3.3V
R74
R76
R75
R77
P3
R15
R13
DGND
DGND
DGND
DGND
GA
OA
EV10AS180x
EV10AS180x
With:
R12 = R74 = 240Ω
R14 = R76 = 649Ω
P1 = P3 = 1K
R13 = R75 = 1.05 kΩ
R15 = R77 = 1.33 kΩ
Figure 4-5. GA and OA Commands Jumper Settings
GA and OA set to default middle value 2 x VCC3/3
EV10AS180x-EB Evaluation Kit User Guide
GA and OA tunable between (2 x VCC3/3 - 0.5V)
and (2 x VCC3/3 + 0.5)
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Application Information
4.4.2
SA Command
This signal is connected by default via its jumper to the command middle value (ie. 2 ×
VCC3/3 = 2.2V).
When the jumper is removed, it is possible to tune the OA and GA commands between
(2 × VCC3/3 – 0.5V) to (2 × VCC3/3 + 0.5V).
Figure 4-6. SA Command Implementation
3.3V
3.3V
R16
R18
R17
R19
P2
DGND
DGND
SA
EV10AS180x
With:
R16 = 1 kΩ
R18 = 649Ω
P2 = 1K
R17 = 1.62 kΩ
R19 = 1.33 kΩ
Figure 4-7. SA Command Jumper Settings
SA set to default middle value
2 x VCC3/3
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SA tunable between (2 x VCC3/3) and
2 x VCC3/3 - 0.5V)
EV10AS180x-EB Evaluation Kit User Guide
Application Information
4.4.3
SDAEN and SDA
Commands
SDAEN signal allows to activate the SDA command when its jumper is OUT or connected as described in Figure 4-9 on page 5. When the SDA function is activated via
SDAEN, then it is possible to tune the sampling delay of the ADC by tuning the SDA
command between (2 × VCC3/3 – 0.5V) and (2 × VCC3/3 + 0.5V) by ±40 ps around the
nominal Aperture delay of the ADC.
Figure 4-8. SDAEN and SDA Commands Implementation
3.3V
3.3V
R82
NC
3.3V
R78
R80
P4
R81
DGND
DGND
DGND
SDAEN
SDA
EV10AS180x
EV10AS180x
With:
R82 = 10 kΩ (NC: can be connected to provide a true High level to SDAEN)
R78 = 240Ω
R80 = 649Ω
P4 = 1K
R79 = 1.05 kΩ
R81 = 1.33 kΩ
Figure 4-9. SDAEN Command Jumper Settings
SDAEN activated: JUMPER
ON
EV10AS180x-EB Evaluation Kit User Guide
SDAEN inactivated: JUMPER
OUT
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Application Information
Figure 4-10. SDA Command Jumper Settings
SDA set to default middle value
2 x VCC3/3
4.5
RSx, TMx and
DECN
Commands
SDA tunable between (2 x VCC3/3 - 0.5) and
(2 x VCC3/3 + 0.5)
The RSx, TMx and DECN functions are implemented on board with a jumper which can
be ON or OUT (default setting is when the Jumpers are OUT, refer to Figure 4-12 on
page 7). A 10 kΩ resistor can be connected in case a pull up is necessary to force a high
level on these signals. This resistor is not connected.
Figure 4-11. RSx, TMx and DECN Commands Implementation
3.3V
RSx
10 kΩ
NC
TMx
DECN
DGND
The default setting for RSx, TMx and DECN is when their respective jumper is OUT
(refer to Figure 4-12). This gives a default setting of the ADC as described below (refer
also to Table 4-1):
„ RS1 = RS0 = Logic High = Jumper OUT -> 1:2 DMUX mode
„ TM1 = TM0 = Logic High = Jumper OUT -> Test mode inactive
„ DECN = Logic High = Jumper OUT -> Decimation Mode inactive
4-6
1072A–BDC–11/12
e2v semiconductors SAS 2012
EV10AS180x-EB Evaluation Kit User Guide
Application Information
When the jumper are on (refer to Figure 4-12), the different settings are described in
Table 4-1.
Table 4-1. RSx, TMx and DECN Commands Jumper Position
Function
Logic Level
Jumper
position
Description
0
ON
Decimation by 8
1
OUT
Normal conversion (no decimation)
01
RS1 : ON
RS0 : OUT
1:1 DEMUX Ratio (Port A)
11
RS1 : OUT
RS0 : OUT
1:2 DEMUX Ratio (Ports A and B)
10
RS1 : OUT
RS0 : ON
1:4 DEMUX Ratio (Ports A, B C and D)
00
RS1 : ON
RS0 : ON
Not used
01
TM1 : ON
TM 0 : OUT
Static Test (all “0”s at the output for VOL test)
11
TM 1 : OUT
TM 0 : OUT
Normal conversion mode (default mode)
10
TM 1 : OUT
TM 0 : ON
Static Test (all “1”s at the output for VOH test)
00
TM1 : ON
TM0 : ON
Dynamic test (checker board pattern = all bits toggling from “0” to “1” or “1” to “0”
every cycle with 1010101010 or 0101010101 patterns)
DECN
RS<1:0>
TM<1:0>
Figure 4-12. RSx, TMx, DECN Command Jumper Settings
Jumpers OUT
EV10AS180x-EB Evaluation Kit User Guide
Jumpers ON
4-7
1072A–BDC–11/12
e2v semiconductors SAS 2012
Application Information
4.6
Output Data
The digital outputs are compatible with LVDS standard. They are on-board 100Ω differentially terminated as described in Figure 4-13.
Figure 4-13. Differential Digital Outputs Implementation
Connector
ADC
100Ω
Double row 2.54 mm pitch connectors are used for the digital output data. The upper
row is connected to the signal while the lower row is connected to Ground, as illustrated
in Figure 4-5 on page 3 and Figure 4-6 on page 4. The connectors are vertical
connectors.
Figure 4-14. Differential Digital Outputs 2.54 mm Pitch Connector (X = A, B)
X0
X0N
X1
X1N
X8
X8N
X9N
X9N
GND
GND
GND
GND
GND
GND
GND
GND
A6N
A7
A7N
A8
A8N
A9
A9N
B6N
B7
B7N
B8
B8N
B9
B9N
A6
A5N
A5
A4N
A4
A3N
A3
A2N
A2
A1N
A1
A0N
A0
Figure 4-15. Differential Digital Outputs 2.54 mm Pitch Connector (Port A)
4-8
1072A–BDC–11/12
e2v semiconductors SAS 2012
B6
B5N
B5
B4N
B4
B3N
B3
B2N
B2
B1N
B1
B0N
B0
Figure 4-16. Differential Digital Outputs 2.54 mm Pitch Connector (Port B)
EV10AS180x-EB Evaluation Kit User Guide
Application Information
Figure 4-17. Differential Digital Outputs 2.54 mm Pitch Connector (X = C, D)
X9N
X9
GND
GND
X8N
GND
X8
X1N
X1
X0N
X0
GND
GND
GND
GND
GND
C0
C0N
C1
C1N
C2
C2N
3C
C3N
C4
C4N
C5
C5N
C6
C6N
C7
C7N
C8
C8N
C9
C9N
Figure 4-18. Differential Digital Outputs 2.54 mm Pitch Connector (Port C)
D0
D0N
D1
D1N
D2
D2N
D3
D3N
D4
D4N
D5
D5N
D6
D6N
D7
D7N
D8
D8N
D9
D9N
Figure 4-19. Differential Digital Outputs 2.54 mm Pitch Connector (Port D)
Figure 4-20. Differential Digital Outputs 2.54 mm Pitch Connector (DR, DRN Signal)
DR
DRN
The data are output in Binary format and in double data rate (the output clock frequency
is half the data rate and thus half the input clock frequency in 1:1 DMUX mode, or ¼ the
input clock frequency in 1:2 DMUX mode and 1/8 the input clock frequency in DMUX 1:4
mode).
EV10AS180x-EB Evaluation Kit User Guide
4-9
1072A–BDC–11/12
e2v semiconductors SAS 2012
Application Information
4.7
Diode for
Junction
Temperature
Monitoring
Two 2 mm banana jacks are provided for the die junction temperature monitoring of the
ADC.
One banana jack is labeled DIODEA and should be applied a current of up to 1 mA (via
a multimeter used in current source mode) and the second one is connected to
DIODEC.
Figure 4-21. Die Temperature Monitoring Test Setup
Protection
Diodes
DIODEA
Banana
jacks
1 mA
V
To DIODEA
To DIODEC
DIODEC
Note:
4.8
The protection diodes are NC.
Test Bench
Description
Figure 4-22. Test Bench Description
Band pass filter
Thermal system
Temperature range
-80 to +163˚
Input Signal
Generator
VINN
balun
Evaluation Board
VIN
ADC
10 -bit
Digital Acquisition
System
Band pass filter
Clock Signal
Generator
balun
Supply
Computer
„ Equipment (for example)
– Input Signal Generator: Agilent E4426B
– Clock Signal Generator: Agilent E4426B
– Power Supply: Agilent 6629A
– Logic Analyser: HP16500C
– Balun: MACOM-H9 (2MHz => 2GHz)
– Band pass filter: LORCH (500MHz => 1GHz) & LORCH (1GHz => 2GHz)
4-10
1072A–BDC–11/12
e2v semiconductors SAS 2012
EV10AS180x-EB Evaluation Kit User Guide
Section 5
Ordering Information
5.1
Ordering
Information
Table 5-1. Ordering Information
Part Number
Package
Temperature Range
Screening Level
Comments
EV10AS180AGS-EB
CI-CGA255
Ambient
Prototype
Evaluation board
EV10AS180x-EB Evaluation Kit User Guide
5-1
1072A–HIREL–11/12
e2v semiconductors SAS 2012
Ordering Information
5-2
1072A–HIREL–11/12
e2v semiconductors SAS 2012
EV10AS180x-EB Evaluation Kit User Guide
Section 6
Appendix
6.1
EV10AS180x-EB
Electrical
Schematics
Figure 6-1. Power Supplies Bypassing
VCCA 5
.
2
.
J3
1
2
C3
1uF
16V K
.
VCC5
.
2
2
VCC3
1
.
C2
100nF
50V K
1
.
.
J8
2
1
2
C1
1uF
16V K
.
1
1
2
.
J1
1
VCC0
PT2
1
J6
C4
100nF
50V K
C5
1uF
16V K
.
1
2
AGND
1
.
2
.
J5
PT1
1
Vcarte
.
.
C6
100nF
50V K
J7
1
2
C7
1uF
16V K
.
.
2
1
2
2
1
2
J4
.
2
1
2
1
PT4
1
3V3
.
1
.
J2
PT3
1
.
C8
100nF
50V K
1
VCCA 3
VCCO
AGND
Figure 6-2. Power Supplies Decoupling
. C27
100pF
J 50V
2
1
2
C26 .
10nF
25V K
1
2
2
. C25
100pF
J 50V
1
C24 .
10nF
25V K
1
2
2
. C23
100pF
J 50V
1
2
C22 .
10nF
25V K
1
. C21
100pF
J 50V
1
C20 .
10nF
25V K
1
2
2
2
. C19
100pF
J 50V
1
C18 .
10nF
25V K
1
2
2
. C17
100pF
J 50V
1
2
C16 .
10nF
25V K
1
. C15
100pF
J 50V
1
2
C14 .
10nF
25V K
1
2
1
. C13
100pF
J 50V
1
2
VCCO
C28 .
10nF
25V K
. C83
100pF
J 50V
2
1
C82 .
10nF
25V K
2
2
. C67
100pF
J 50V
1
C66 .
10nF
25V K
2
2
2
. C81
100pF
J 50V
1
C80 .
10nF
25V K
1
. C65
100pF
J 50V
2
C64 .
10nF
25V K
2
2
2
. C79
100pF
J 50V
1
C78 .
10nF
25V K
1
. C63
100pF
J 50V
2
C62 .
10nF
25V K
2
2
1
. C61
100pF
J 50V
1
2
VCCA 3
C68 .
10nF
25V K
AGND
1
1
1
1
1
1
2
1
. C77
100pF
J 50V
1
2
VCCA 5
C84 .
10nF
25V K
AGND
EV10AS180x-EB Evaluation Kit User Guide
6-1
1072A–BDC–11/12
e2v semiconductors SAS 2012
1
.
PT15
2
1
R5
J 10K
0.10W
NE
2
3
1
.
J13-B
SM A-bord-de-cart
e
RSTN
J13-A
SM A-bord-de-cart
e
SW 11 .
2
1
.
J14
2
1
DIODE C
DIODE A
J15
R72
J 10K
0.10W
NE
NC
NC
1
.
PT16
1
70V
NE
CR2
BAV99
70V
NE
3V3
R2
J 10K
0.10W
NE
1 2
NE
70V
CR4
BAV99
NE
70V
NC
NC
1
1
.
PT14
.
.
PT17
SW 19
.
1
1
1
B
.
.
.
PT7
PT6
PT5
R3
J 0
0.10W
R4
J 0
0.10W
NE
SW 12
SW 13 .
3 4
SW 5
R6
J 10K
0.10W
NE
3V3
SW 18
R73
J 10K
0.10W
NE
3V3
SW ITCH-STTS
KHUB
.
CR3
BAV99
R1
. J 0
0.10W
.
PT11
.
SW 16
SW 17
.
CR1
BAV99
SW 10
3V3
SW 14
.
2
1
1 2
2
TM 1
TM 0
DE CN
DiodeC
DiodeA
RS TN
RS 1
RS 0
.
P2
1K
R16
F 1K
0.10W
R17
F 1.62K
0.10W
.
.
3
.
C10
100nF
K 50V
SW 7
1
.
.
.
PT13
R19
F 1.33K
0.10W
1 2 3
J17
.
.
R18
F 649
0.10W
2
1
2
1
2
2 1
1
2
1
.
R13
F 1.05K
0.10W
.
2
3
.
C9
100nF
K 50V
3V3
P1
1K
R12
F 240
0.10W
.
.
1
R15
F 1.33K
0.10W
.
R14
F 649
0.10W
.
PT12
1 2 3
J16
.
SW 6
.
3V3
2
1
2
1
2 1
1
2
1
3V3
.
R7
J 10K
0.10W
NE
SW15 .
.
2
1
1 2
1 2
4
5 6
V1 V2 V3
V4 V5 V6
7
8 9
2
1
2
1
2
1
1 2
2
1
1
1 2
.
2
1
.
R75
F 1.05K
0.10W
.
3
.
C11
100nF
K 50V
3V3
P3
1K
R74
F 240
0.10W
.
2
2 1
1
2
1
3V3
.
2
3
21
3
1
1
3
12
3
2
2
1
2
1
.
1
.
R77
F 1.33K
0.10W
.
R76
F 649
0.10W
.
PT18
1 2 3
J23
.
SW 8
2
1
3V3
2
1
2
1
SW 20
R82
J 10K
0.10W
NE
3V3
2
1
1 2
3V3
1
.
.
PT20
SW 21
.
.
.
SD AEN
R79
F 1.05K
0.10W
SA
GA
OA
3V3
P4
1K
R78
F 240
0.10W
.
3
.
C12
100nF
K 50V
.
1
.
.
SD A
R81
F 1.33K
0.10W
PT19
1 2 3
J24
.
SW 9
.
R80
F 649
0.10W
N3
P3
T4
R13
T13
R14
T14
N14
P14
P4
N4
R12
T12
3V3
2
1
2
2
2 1
1
2
1
e2v semiconductors SAS 2012
2
1072A–BDC–11/12
1
6-2
1
3V3
1/3
CONTROL
DIOD EC
MN 1-A
EV10AS180x
DIOD EA
RS TN
RS 1
RS 0
TM 1
TM 0
DE CN
SA
GA
OA
SD AEN
SD A
Appendix
Figure 6-3. Electrical Schematics
EV10AS180x-EB Evaluation Kit User Guide
Appendix
Figure 6-4. Electrical Schematics (Analogue and Clock Input)
6
.
4
5
V1 V2 V3
V4 V5 V6
7
8
9
J11-B
SM A-bord-de-carte
AGND
AGND
J11-A
SM A-bord-de-carte
2/3
C93 .
10nF
25V K
DA TA A
A0
A0N
A1
A1N
A2
A2N
A3
A3N
A4
A4N
A5
A5N
A6
A6N
A7
A7N
A8
A8N
A9
A9N
P1
P2
N1
N2
M1
M2
L3
M3
L1
L2
K1
K2
K3
J3
J1
J2
H1
H2
H3
G3
A0
A0N
A1
A1N
A2
A2N
A3
A3N
A4
A4N
A5
A5N
A6
A6N
A7
A7N
A8
A8N
A9
A9N
DA TA B
B0
B0N
B1
B1N
B2
B2N
B3
B3N
B4
B4N
B5
B5N
B6
B6N
B7
B7N
B8
B8N
B9
B9N
F1
F2
E3
F3
E1
E2
D1
D2
A4
B4
A5
B5
C6
C5
A6
B6
A7
B7
C7
C8
B0
B0N
B1
B1N
B2
B2N
B3
B3N
B4
B4N
B5
B5N
B6
B6N
B7
B7N
B8
B8N
B9
B9N
EV10AS180x
MN 1-B
1
2
1
2 .
3
VIN
VIN
AGND
J12-A
SM A-bord-de-carte
VINN
C94 .
10nF
25V K
1
2
3
2
.
1
AGND
6
.
4
5
V1 V2 V3
V4 V5 V6
7
8 9
J12-B
SM A-bord-de-carte
AGND
VIN
AGND
T9
VINN
T10
DATA READY
DA TA C
C0
C0N
C1
C1N
C2
C2N
C3
C3N
C4
C4N
C5
C5N
C6
C6N
C7
C7N
C8
C8N
C9
C9N
DA TA D
D0
D0N
D1
D1N
D2
D2N
D3
D3N
D4
D4N
D5
D5N
D6
D6N
D7
D7N
D8
D8N
D9
D9N
P16
P15
N16
N15
M1 6
M1 5
L14
M1 4
L16
L15
K16
K15
K14
J14
J16
J15
H16
H15
H14
G1 4
D0
D0N
D1
D1N
D2
D2N
D3
D3N
D4
D4N
D5
D5N
D6
D6N
D7
D7N
D8
D8N
D9
D9N
CLKN
6
5
.
4
V1 V2 V3
V4 V5 V6
7
8
9
J9-B
SM A-bord-de-carte
C95 .
10nF
25V K
1
2
3
2
.
1
CLK
CLKN
CLK
AGND
J10-A
SM A-bord-de-carte
C96 .
10nF
25V K
1
2
3
2
.
1
.
DRN
F16
F15
E14
F14
E16
E15
D16
D15
A13
B13
A12
B12
C11
C12
A11
B11
A10
B10
C10
C9
R6
DR
R83 100
1
A9
B9
C0
C0N
C1
C1N
C2
C2N
C3
C3N
C4
C4N
C5
C5N
C6
C6N
C7
C7N
C8
C8N
C9
C9N
CLK
T6
AGND
AGND
J9-A
SM A-bord-de-carte
DR
DRN
.
TSM-104-01-L-DV-A
F
0.10W
.
1
J22 J22
2
3
J22 J22
4
5
J22 J22
6
7
J22 J22
8
2
AGND
6
5
.
4
AGND
V1 V2 V3
V4 V5 V6
7
8 9
J10-B
SM A-bord-de-carte
AGND
EV10AS180x-EB Evaluation Kit User Guide
6-3
1072A–BDC–11/12
e2v semiconductors SAS 2012
Appendix
Figure 6-5. Electrical Schematics (Output Connectors Ports A and B)
J18
2
3
J18 J18
4
5
J18 J18
6
7
J18 J18
8
9
J18 J18
10
11
J18 J18
12
13
J18 J18
14
.
.
B0N
15
J18 J18
16
R41
F 249
0.10W
R43
F 249
0.10W
B1
17
J18 J18
18
R29
F 249
0.10W
A1
1
1
1
R27
F 249
0.10W
F
A0N
.
A2
1
A3
1
A4
1
A5
1
A6
1
A7
1
A7N
A8
1
R24 100
F
A8N
A9
1
0.10W
.
B3
25
J18 J18
26
B3N
27
J18 J18
28
B4
29
J18 J18
30
B4N
31
J18 J18
32
B5
33
J18 J18
34
B5N
35
J18 J18
36
B6
37
J18 J18
38
B6N
39
J18 J18
40
B7
41
J18 J18
42
B7N
43
J18 J18
44
B8
e2v semiconductors SAS 2012
4
5
J19 J19
6
7
J19 J19
8
9
J19 J19
10
11
J19 J19
12
13
J19 J19
14
15
J19 J19
16
17
J19 J19
19
J19 J19
20
21
J19 J19
22
23
J19 J19
24
25
J19 J19
26
27
J19 J19
28
29
J19 J19
30
31
J19 J19
32
33
J19 J19
34
35
J19 J19
36
37
J19 J19
38
39
J19 J19
40
41
J19 J19
42
43
J19 J19
44
45
J19 J19
B8N
J18 J18
48
B9
46
47
J19 J19
49
J18 J18
50
B9N
J18 J18
52
F
48
49
J19 J19
50
51
J19 J19
2
0.10W
.
R39 100
1
2
2
0.10W
.
R38 100
F
2
0.10W
.
R37 100
F
2
0.10W
.
R36 100
F
0.10W
.
18
2
0.10W
.
R35 100
F
1
PORT A
1072A–BDC–11/12
F
1
J18
J19 J19
2
0.10W
.
R34 100
1
46
NC Alignem
entPin
F
1
J18 J18
54
2
3
2
0.10W
.
R33 100
1
47
45
J19
2
0.10W
.
R32 100
F
1
2
51
6-4
2
2
24
2
0.10W
.
R25 100
F
J18 J18
2
0.10W
.
F
1
2
0.10W
.
R23 100
F
B2N
2
0.10W
.
R22 100
F
A6N
22
2
0.10W
.
R21 100
F
A5N
J18 J18
2
0.10W
.
R20 100
F
A4N
J18 J18
23
J19
.
J19
2
0.10W
.
R31 100
1
B2
21
F
B1N
20
19
R30 100
1
2
0.10W
.
R11 100
F
A3N
100
B0
2
0.10W
.
R10 100
F
A2N
100
0.10W
.
R9
F
A1N
A9N
R8
53
1
100 Oh ms shall be put
outside toget 1V and 1V4
1
.
2
2
1
100 Oh ms shall be put
outside to get1V and 1V4
1
100 Oh ms shall be put
outside toget1V and 1V4
A0
TSM-126-01-L-DV
NC Alig
neme ntPin
.
J18
J18
1
100 Oh ms shall be put
outside toget1V and 1V4
.
R42
F 464
0.10W
1
53
1
NC Aligne
me ntPin
.
R40
F 464
0.10W
1
TSM-126-01-L-DV
.
R28
F 464
0.10W
1
2
2
.
R26
F 464
0.10W
3V3
2
3V3
3V3
2
3V3
2
NC Alig
neme ntPin
54
52
J19
PORT B
EV10AS180x-EB Evaluation Kit User Guide
Appendix
Figure 6-6. Electrical Schematics (Output Connectors Ports C and D)
TSM-126-01-L-DV
NC Aligne
me ntPin
R58 100
1
F
C9
C8N
F
C7N
F
C6N
F
C6
C5N
1
F
C5
C4N
1
F
C4
C3N
F
C2N
F
6
7
J20 J20
8
9
J20 J20
10
11
J20 J20
12
13
J20 J20
14
15
J20 J20
16
D7N
D6N
17
J20 J20
18
19
J20 J20
20
21
J20 J20
22
23
J20 J20
24
25
J20 J20
26
27
J20 J20
28
29
J20 J20
30
31
J20 J20
32
33
J20 J20
34
35
J20 J20
36
F
37
J20 J20
38
39
J20 J20
40
41
J20 J20
42
43
J20 J20
44
45
J20 J20
46
47
J20 J20
48
49
J20 J20
50
51
J20 J20
52
D5N
D4N
D3N
D2N
100 Oh ms shall be put
outside toget1V and 1V4
0.10W
.
D1N
100 Oh ms shall be put
outside toget1V and 1V4
.
R57
F 249
0.10W
.
D0N
R68
F 464
0.10W
R65 100
1
D0
F
100 O hm s shall be put
outside to get1V and 1V4
100 O hm s shall be put
outside to get1V and 1V4
J21 J21
12
13
J21 J21
14
15
J21 J21
16
17
J21 J21
19
J21 J21
20
21
J21 J21
22
23
J21 J21
24
25
J21 J21
26
27
J21 J21
28
29
J21 J21
30
31
J21 J21
32
33
J21 J21
34
35
J21 J21
36
37
J21 J21
38
39
J21 J21
0.10W
.
40
41
J21 J21
42
43
J21 J21
44
45
J21 J21
46
47
J21 J21
48
49
J21 J21
50
51
J21 J21
52
18
2
NC Alig
neme ntPin
2
EV10AS180x-EB Evaluation Kit User Guide
11
2
0.10W
.
.
R66
F 464
0.10W
J20
PORT C
1
1
.
R55
F 249
0.10W
F
D1
2
2
NC Aligne
me ntPin
54
10
2
0.10W
.
R64 100
1
2
J21 J21
3V3
1
F
8
9
54
J21
2
1
C0
1
1
R51 100
F
J21 J21
2
0.10W
.
R63 100
1
D2
1
C0N
F
6
7
2
0.10W
.
R62 100
1
D3
2
.
R56
F 464
0.10W
F
J21 J21
2
0.10W
.
R61 100
1
D4
2
2
.
R54
F 464
0.10W
F
4
5
2
0.10W
.
R60 100
1
D5
2
0.10W
.
F
D6
J21 J21
2
0.10W
.
R53 100
1
2
3
2
1
C1
F
J21
.
J21
J21
2
0.10W
.
R52 100
1
D7
3V3
R50 100
F
53
1
2
0.10W
.
R71 100
1
D8
3V3
C1N
F
D8N
2
0.10W
.
R70 100
1
D9
.
.
R67
F 249
0.10W
R69
F 249
0.10W
1
3V3
J20 J20
2
0.10W
.
R49 100
1
C2
5
D9N
2
0.10W
.
R48 100
1
C3
4
2
0.10W
.
R47 100
J20 J20
2
0.10W
.
R46 100
3
2
0.10W
.
R45 100
1
2
2
0.10W
.
R44 100
1
C7
.
J20
J20
2
0.10W
.
R59 100
1
C8
NC Aligne
me ntPin
J20
1
PORT D
1
C9N
53
TSM-126-01-L-DV
6-5
1072A–BDC–11/12
e2v semiconductors SAS 2012
Appendix
6.2
EV10AS180x-EB
Board Layers
Figure 6-7. Top Layer
EV10AS18X-EVALUATION-BOARD
9001661B
GA
SA
1
B
OA
DIOD EA
DIOD EC
A0
A1
A2
GN D
A3
B0
RS TN
A4
B1
A5
B2
A6
A7
B3
B4
A8
B5
A9
B6
CLK
B7
B8
B9
CLKN
DR
VIN
C9
C8
VINN
C7
D9
C6
C5
D8
D7
C4
D6
C3
AG ND
C2
D5
VCC5
D4
C1
C0
SD A
D3
AG ND
D2
D1
DECN
TM 1
TM 0
RS 1
RS 0
D0
SDAE N
DG ND
VCCO
DG ND
3V3
VCC3
EV10AS18X-EVALUATION BOARD
6-6
1072A–BDC–11/12
e2v semiconductors SAS 2012
LAYER 1 COMPONENT SIDE
EV10AS180x-EB Evaluation Kit User Guide
Appendix
Figure 6-8. Bottom Layer
6
B
LAYER 6 SOLDER SIDE
EV10AS180x-EB Evaluation Kit User Guide
6-7
1072A–BDC–11/12
e2v semiconductors SAS 2012
Appendix
Figure 6-9. Equipped Board (Top)
Dotted components are not wired
FX2
FX7
R15
R14
C9
PT12
R77
R76
PT18
C11
PT6
P1
P2
R26
R27
J23
J17
PT13
C10
J16
R19
R18
FX4
R28
R29
PT7
P3
R8
R16 R17
R12 R13
R74 R75
R9
R41
R40
SW 5
R1
R10
R2
R43
SW 3
R42
R4
R11
J13
J18
R3
PT5
R30
R20
R31
R21
R32
SW 1
R22
R33
J19
R23
R34
R24
FX1
R35
R25
J9
R36
C95
R37
R38
J10
R39
C96
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
MN 1
8
R83
9
J22
10
11
12
13
14
15
J11
16
C93
R58
R59
R44
C94
J12
R45
R70
R46
FX8
R71
R47
R52
J20
R48
C5 C6
R53
R49
PT2
R60
R50
R61
SW 4
J21
R62
R63
C3 C4
P4
PT3
PT1
R65
6-8
1072A–BDC–11/12
e2v semiconductors SAS 2012
R7
R72
R66
R67
PT17
R73
SW 18
R5
SW 14
R6
PT16 PT15
SW 16
R82
PT11
SW 10
FX3
PT14
SW 12
C1
SW 20
PT20
C2
C7
R54
R55
R68
R69
PT4
C8
R51
R56
R57
R64
C12
R81
R80
J24
R78 R79
PT19
SW 2
FX5
FX6
EV10AS180x-EB Evaluation Kit User Guide
Appendix
Figure 6-10. Equipped Board (Bottom)
BLACK
RED
Dotted components are not wired
J14
J15
CR4
CR3
R88
CR1
R98
CR2
R1
01
R9
1
R9
R99
R93
R92
R89
R 103
R94
C79
C80
C81 C82
C65 C66
C64 C63
C
C2 21
2
C
C2 23
4
C83 C84
C61 C62
C77
C78
C67 C68
0
02
C20 C19
C14 C13
R1
5
C2 2 6
7 C
C2 28
C
C16
C15
C17 C18
R104
R97
Put all 100 pF capacitor below 10 nF capacitor
J5
J6
RED
J3
BLACK
RED
J7
RED
BLACK
R 117
R 116
J2
J8
RED
15
J1
BLACK
R1
EV10AS180x-EB Evaluation Kit User Guide
R 111
R8
4
R9
6
R8
6
R1
06
BLACK
J4
R1
05
R 107
R87
R 100
R9
5
R85
6-9
1072A–BDC–11/12
e2v semiconductors SAS 2012
Appendix
6-10
1072A–BDC–11/12
e2v semiconductors SAS 2012
EV10AS180x-EB Evaluation Kit User Guide
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e2v semiconductors SAS 2012
1072A–BDC–11/12