Technical Report #USC 03-0511
Electronic Noise Characterization −
Part II: Circuit Noise Characteristics
Dr. John Choma
Professor of Electrical Engineering
Scholar in Residence, Raytheon Space and Airborne Systems Electronics Center
University of Southern California
Ming Hsieh Department of Electrical Engineering
University Park: Mail Code: 0271
Los Angeles, California 90089–0271
213–740–4692 [USC Office]
818–384–1552 [Cell]
johnc@usc.edu
ABSTRACT:
This report applies the theories and concepts developed in Technical Report #USC 02511 to analyze and assess the noise responses of electronic circuits designed to
process broadband input signals linearly. In addition to examining the noise
characteristics of these active networks, we shall discuss the design strategies that lead
to optimal noise performance in the senses of a minimal input noise floor, a minimal
noise factor, or minimal output noise power. In general, emphasis is placed herewith
on analog MOS and CMOS technology circuits. But in advance of a consideration of
canonic analog MOSFET cells, we shall begin our work by examining the noise
properties of simple resistive, resistive-capacitive (RC), and resistive-inductive (RL)
networks.
August 2011
Technical Report #03-0511
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University of Southern California Viterbi School of Engineering
Choma
INTRODUCTION
The companion document to this disclosure is Technical Report #USC 02-511, which
examines the fundamental system concepts and models that underpin a noise analysis and assessment of active and passive circuits[1]. In addition to identifying the noise models of a resistor,
the PN junction diode, and the MOSFET, that report addresses the various metrics that are commonly used to evaluate the noise characteristics of linear networks. Included among these metrics are the signal -to- noise ratio, the noise factor (or noise figure), the noise equivalent bandwidth, the equivalent input noise voltage and current, along with its associated noise floor, the
correlation coefficient, the noise power spectral density, and Friis’ formula for network cascades.
A cursory review of these issues appropriately frames the work on which this report relies.
(1). The signal -to- noise ratio, SNR, is evaluated at stipulated network ports. Generally, the network ports at which signal -to- noise ratios are of particular interest are the input and output
ports. The signal -to- noise ratio is the ratio of the signal power established at the subject
port -to- the noise power delivered to that port. It is customary to measure both signal and
noise powers in terms of mean square voltages or currents, which are equivalent to the
square of the root mean square (RMS) values of these voltages and currents, respectively.
Naturally, prudent design objectives advance large SNR’s at each port of interest.
(2). The noise factor, F, of a linear two port network is the ratio of the signal -to- noise ratio at
the input port -to- the signal -to- noise ratio established at the network output port. The
noise figure is simply the decibel value of this noise factor. Ideally, F = 1 (or 0 dB), which
implies that the output noise level incurred by noise generators implicit to the network are
negligible in comparison to the output noise manifested exclusively by the noise associated
with the applied input signal source.
(3). The noise equivalent bandwidth, Δf, is proportional to, and larger than, the signal bandwidth, B, of the network subjected to a noise characterization. The noise equivalent bandwidth is the passband of a brick wall filter whose passband gain is the true zero frequency
gain of the network earmarked for noise characterization. The noise bandwidth is chosen so
that the output noise level of the simple brick wall model matches that of the actual circuit
subjected to investigation.
(4). Noisy linear networks can be modeled by their noiseless counterparts, provided that proper
equivalent noise voltage and/or noise current generators are appropriately deployed at network input port to produce an output port noise level from the internally noiseless system
that is identical to the output noise level observed with the original, noisy network. Once
equivalent input noise generators are quantified, the noise floor, which is the minimum
amplitude of an input signal that the network is capable of detecting reliably and processing
faithfully, can be defined in terms of these noise generator equivalencies.
(5). When uncorrelated noise sources in a given circuit superimpose with one another, the net
mean square value of the resultantly generated noise is simply the sum of the mean square
noise voltage or current values of the individual noise sources.
(6). The noise power spectral density defines the manner in which available noise power is
distributed as a function of frequency. For white noise, the noise spectral density is a constant, independent of frequency, which is to say that white noise power is uniformly distributed over frequency. Flicker noise, which is pervasive of MOS devices and other devices
featuring carrier transport at surface interfaces, has nominally an inverse frequency dependence.
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(7). Friis’ formula allows a convenient estimate of the noise factor for a cascade of linear networks. It confirms that if the magnitude of first stage gain is large, the noise factor of the
entire cascade is essentially the noise factor of the first stage.
2.0.
NOISE IN PASSIVE NETWORKS
Our circuit level noise analyses begin by considering the noise properties of a simple
resistive network, a single pole lowpass RC filter, a two pole lowpass RLC filter, and a PN
junction diode network. In each of these examples, we use established noise models and
documented noise analysis procedures and strategies to compute the mean square value of the net
output noise[1].
2.1.
RESISTANCE NETWORK
In the two-resistor network of Figure (1a), each resistance generates thermal white
noise in the mean square voltage amounts of
e 2 (t)  E 2  4kTR Δf
1
1
1
e 2 (t)  E 2  4kTR Δf
2
2
2
,
(1)
R1
R1
R2
eo(t)
R2
e1(t)
(a).
*
e2(t)
*
(b).
R1 ||R2
R1||R2 eo(t)
jo(t)
eo(t)
*
(c).
(d).
Figure (1). (a). The parallel interconnection of two noisy resistances. (b). The
noise equivalent circuit of the shunt configuration in (a). (c). The
Thévenin noise equivalent circuit of the shunt configuration in (a). (d).
The Norton noise equivalent circuit of the shunt network in (a).
where E1 and E2 respectively denote the RMS values of the two resistive noise voltages, and it is
tacitly presumed that the resistive network is ultimately embedded into a network whose noise
equivalent bandwidth is Δf. Figure (1b) displays the noise equivalent circuit in which e1(t) and
e2(t) symbolically designate the time domain noise voltages associated with resistances R1 and
R2, respectively. Assuming that the two resistor noise voltages are uncorrelated, the mean square
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open circuit noise voltage, E 2  e 2 (t) , established across the parallel combination of resistances
o
o
is simply the sum of the scaled mean square contribution of each resistor noise voltage. In
particular,
2
 R
 2  R
2
2
2
1
 E 
e (t)  E  
o
o
1
R R 
R R
 1
 1
2 
2
2
 2
 E ,
 2

(2)
and by (1),
2
 R
 2  R
2
2
1
 E 
E  
o
R R  1 R R
 1
 1
2 
2
2
 2
 R R 
 E  4kT  1 2  Δf  4kT R R Δf . (3)
1 2
 2
R R 

 1
2 
In other words, the resultant mean square output noise voltage can be attributed to a resistance
whose value is (R1||R2), as Figure (1c) underscores. This result is visceral since we could have
argued at the outset that the parallel interconnection of resistances R1 and R2 in Figure (1a) could
have been supplanted by a single resistance of value (R1||R2), whose mean square noise voltage
follows directly as

e 2 (t)  E 2  4kT R R
o
o
1
2


 Δf .
(4)
We note in passing that the Norton noise current equivalent of (4) is, with Jo representing a mean
square noise current,
2
2
j (t)  J 
o
o
2
o
E

 Δf
4kT R R
1
2
2
2.2.



4kTΔf


(5)
 4kT G  G Δf ,
1
2
R
R
R R 
R R
1 2
 1 2
1 2


where G1 and G2 are the conductances of resistances R1 and R2, respectively. In a word, the
mean square value of the short circuit noise current, jo(t), attributed to a parallel connection of
noisy resistances R1 and R2 is indeed the noise current attributed to a single resistance of conductance (G1 + G2). Once again, (5) is seen as reflecting expectations in that the net conductance of
two shunt resistances, R1 and R2, is merely the sum of the individual conductances. Figure (1d)
reflects the foregoing Norton equivalent noise circuit of two resistances connected in parallel.
2

RC NETWORK
In the RC network of Figure (2a), the I/O voltage transfer function, Av(j2πf), is
V
1
A (j2πf)  o 
.
v
V
1  j2πf RC
(6)
s
This single pole relationship portends a zero frequency value of Av(0) = 1, and a 3-dB bandwidth, B, (in Hz) of B = 1/2πRC. It follows that the noise equivalent bandwidth, Δf, (also in
hertz) of the subject circuit is
1

Δf    B 
.
(7)
4RC
 2
If the signal noise, say eR(t), is attributed solely to thermal noise in resistance R, the
noise equivalent circuit is the structure in Figure (2b), where the mean square value of the resistor noise voltage, whose RMS value is ER is
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Vo
eo(t)
R
Brick Wall
Filter Model
Eo /ER
R

C
Vs
eR(t)

C
*
(a).
Choma
ER
1
0
(b).
Eo
1/4RC
f
(c).
Figure (2). (a). A single pole, lowpass RC filter. (b). The noise equivalent circuit of the filter in
(a). Noise is presumed to derive exclusively from thermal effects in resistance R. (c).
The resistance noise applied to the brick wall model of the filter in (b). The frequency, 1/4RC, is the noise equivalent bandwidth, Δf, of the RC filter in (a).
2
R
e (t)  E
2
 4kTRΔf .
R
(8)
Since noise voltage eR(t) in Figure (2b) appears in series with resistance R, as does signal voltage
Vs in Figure (2a), the I/O transfer function with respect to the RMS resistor noise voltage is the
same as the transfer relationship in (6). The formal, but somewhat cumbersome, procedure for
determining the mean square noise voltage developed across the network output port where
capacitance C is incident is as follows. First, we multiply the spectral density, e 2 (t) Δf  4kTR ,
R
of the input resistance noise by the squared magnitude of the transfer function in (6). While this
multiplication is hardly provocative, the next step embodies the awkward task of integrating this
multiplied product over all positive frequency space. This integrated disclosure is the desired
mean square output noise voltage of the RC filter at hand. But the desired result can be obtained
more directly by imagining that the RMS resistance noise voltage, ER, is applied to the input of
the brick wall filter depicted symbolically in Figure (2c). The resultant voltage response of the
idealized filter has an RMS value of Eo. Observe that the passband gain of this brick wall
abstraction is one, which is the low frequency gain of the original network. Moreover, the passband width of the filter is the noise equivalent bandwidth delineated by (7) as 1/4RC. Then,
since nonzero output noise can be generated only over the brick wall passband of frequency
width Δf, the mean square output noise voltage, e 2 (t)  E 2 , derives directly as
o
2
o
e (t)  E
2

o
12 4kTRΔf

4kTR
kT

.
4RC
C
o
(9)
The foregoing compact result is interesting from several perspectives. The first, and
arguably most provocative, observation is that the net mean square output noise voltage is
independent of resistance R. This functional independence accrues despite the fact that resistance R breeds the input noise that activates the input port of the RC network. Of course, the reason that the output mean square noise voltage is independent of R is that the input mean square
noise voltage is taken as exclusively due to the circuit resistance, R, and thus, the input noise voltage (or power spectral density) is directly proportional to R. But the noise equivalent bandwidth, Δf, is inversely proportional to the same resistance, whence 4kTRΔf, on which the mean
square output noise is directly dependent, is independent of R. If the input signal noise were to
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be generated by means other than thermal noise in resistance R, R would have appeared in the final noise response.
A second important point is that the direct computational method, which entails
cumbersome integration, delivers precisely the same response as does the simple brick wall
analytical strategy. In other words, the brick wall v is not an approximation. The reason for
matched results between the direct and brick wall computational strategies is that the brick wall
passband, Δf, is chosen expressly to ensure that the hypothetical brick wall system delivers a
mean square voltage (or current) output noise response that is identical to the output noise observed for all signal frequencies in the original circuit. Moreover, Δf derives from integration
over all positive frequency space of the product of the squared magnitude of the network transfer
function and the input noise power spectral density. Such integration is precisely the computational tack entailed by the formal analytical approach.
Finally, it is somewhat curious that while capacitance C generates no electrical noise in
and of itself, the mean square output noise voltage is functionally inversely dependent on C. Although capacitance C generates no electrical noise, it does serve to limit the 3-dB bandwidth of
the original filter and thus, the noise equivalent bandwidth of the system. To this end, note that
progressively larger values of C, which unfortunately result in correspondingly narrower signal
passbands, produce proportionately reduced output noise response. The lesson to be learned here
is that broadband systems are, in fact, vulnerable to degraded noise characteristics.
2.3.
RLC NETWORK
The RLC network depicted in Figure (3a) has a voltage transfer function, Av(s), of
L
L
Vo
R
eo(t)
Brick Wall
Filter Model
Eo /ER
R

C
Vs

eR(t)
C
*
(a).
ER
1
0
(b).
Eo
f
f
(c).
Figure (3). (a). A two pole, lowpass RLC filter. The filter is designed to deliver a maximally flat
magnitude frequency response. (b). The noise equivalent circuit of the filter in (a).
Noise is presumed to derive exclusively from resistance R. (c). The resistance noise applied to the brick wall model of the filter in (b). The noise equivalent bandwidth, Δf, of
the RLC filter in (a) is given by (16).
A (s) 
v
V
1
o 
,
2
V
1  sRC  s LC
s
(10)
which can be cast into the traditional second order format,
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1
A (s) 
v
1
 s 


 
Q
n  n
s
2
.
Choma
(11)
In (11),
n 
1
(12)
LC
is the radial undamped natural frequency of oscillation, which is also commonly referred to as
the radial self-resonant frequency of the second order filter. Moreover,
1 L
(13)
Q 
R C
is the quality factor of the subject filter. It can be demonstrated that in the steady state, the
second order filter in Figure (3a) delivers a Butterworth, maximally flat magnitude (MFM) response, when Q is chosen to be the inverse of the square root of two[2]. In other words, the subject filter delivers the maximal possible bandwidth, subject to the constraint of no response peaking within the filter passband. With Q  1 2 , resistance R necessarily satisfies the design
constraint,
2L
R 
,
(14)
C
and frequency ωn becomes precisely the radial 3-dB bandwidth of the second order network.
Thus, bandwidth B in units of Hz, subject to the MFM design constraint of (14), is
ω
1
B  n 
.
(15)
2
2 LC
It follows that the noise equivalent bandwidth, Δf, of this second order filter is

  4 
1
1
1
2

Δf  
.
 
 
8 LC
8 sin  4  LC
 sin  4    2 LC 
(16)
Figure (3b) displays the equivalent noise model, for which we assume that signal noise,
as in the case of the previously considered single pole RC filter, is incurred solely because of
thermal noise in resistance R. Accordingly, the mean square value of the noise voltage produced
by resistance R over a noise equivalent bandwidth of Δf is
e 2 (t)  E 2  4kTRΔf ,
R
(17)
R
where it is understood that R and Δf are given by (14) and (16), respectively. As in the case of
the RC filter, we see that the RMS value, ER, of this noise voltage is delivered to the output port
of the RLC filter with a network transfer factor that is identical to the transfer function that operates on the applied signal voltage, Vs. Thus, we can determine the mean square value of the output noise voltage by viewing the resistance noise as applied to the input port of a suitable brick
wall filter that emulates the noise performance of the filter. As delineated in Figure (3c), this
brick wall filter has a passband of Δf, as per (16), and a passband transfer function value of one,
which indeed is the zero frequency transfer function, Av(0), in accord with (10). We therefore
find that that the mean square value of the RLC output noise voltage is
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2
e 2 (t)  E 2   1 4kTRΔf  4kT
o
o
2L
C
1

8
2
LC

kT
.
 
C

Choma
(18)
Perhaps somewhat surprisingly, the mean square value of the output noise voltage for
the RLC filter of Figure (3a), which has been designed to deliver a maximally flat magnitude frequency response, is identical to that of the simple RC filter shown in Figure (2a). While the result is arguably unexpected, there is a common denominator to the two circuits considered thus
far. In particular, both filters exude a maximally flat magnitude frequency response. The
second filter is specifically designed to yield this flat response, while an inherently MFM response nature pervades all first order filters possessed of no finite frequency transmission zeros.
We observe in (18) that to the extent that resistance R is chosen to satisfy (14), the mean square
output noise voltage is independent of circuit inductance L. This observation encourages the
selection of capacitance C to ensure the satisfaction of targeted output noise requirements and
then finding inductance L in concert with the desired 3-dB filter bandwidth, B.
2.4.
DIODE NETWORK
Semiconductor diodes are commonly used as voltage divider branch elements in biasing circuits. This situation commonly surfaces in bipolar technology circuits for which thermal
matching of junction voltages in transistors with junction voltages of counterpart diodes is often
important. To this end, consider the simple two-diode network in Figure (4a) which depicts a series interconnection of diodes D1 and D2 connected to a voltage bus whose Thévenin voltage
and resistance are Vcc and Rcc, respectively. The desired response of the network is a static, or
quiescent output voltage, VoQ, which is essentially the voltage developed across diode D2.
Resistance Rcc arises from the inherently nonzero resistivity of the power bus metallization in
integrated circuits and therefore, it generates thermal noise in the mean square voltage amount of
2
R
e (t)  E
2
 4kTR Δf ,
R
cc
(19)
where, of course, Δf represents the noise equivalent bandwidth of the electronic system in which
the indicated diode bias string is connected, and ER is the RMS voltage value of the resistance
noise. Figure (4b) offers the pertinent noise equivalent circuit, where the time deterministic biasing voltage, Vcc, is reduced to zero to allow an exclusive analytical focus on noise phenomena.
Moreover, resistance Rcc is supplanted by a noiseless resistance of value Rcc in series with an
RMS noise voltage of ER. Each diode is replaced by its equivalent noise circuit, which consists
of small signal diode resistance rD inserted in series with a noise voltage whose mean square
value is
e 2 (t)  E 2  2n kT r Δf ,
D
D
j
(20)
D
where ED is the RMS value of this diode noise voltage. The two diodes in the network of Figure
(4a) obviously conduct the same static current. In view of this fact and the presumption that the
two diodes are matched semiconductor elements, resistances rD in both of the diode noise models
are identical. Moreover, the diode RMS noise voltages, eD1(t) and eD2(t), have identical RMS
values of ED1 and ED2, respectively. We have nonetheless chosen to differentiate between the
indicated two noise voltages solely for the purpose of tracking the mathematical fruits of
superposition theory, which we invoke to formulate an expression for the total mean square
output noise voltage, e 2 (t)  E 2 .
o
o
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Rcc
Rcc
rD
D1
eR(t)
*
*
eD1(t)
VoQ

RDout
Vcc

rD
eo(t)
RDout
D2
(a).
eo(t)
eo(t)
*
*

eD2(t)
VoQ

(b).
(c).
Figure (4). (a). A biasing network that utilizes two PN junction diodes connected in series with the
supply line voltage, Vcc. The internal resistance of this voltage line is Rcc. (b). The noise
equivalent circuit of the network in (a). The diodes, which necessarily conduct the same
static current, are presumed identical, whence the RMS values, ED1 and ED2, of these diode voltages are identical. (c). The Thévenin noise equivalent circuit for the divider output port.
In terms of RMS noise voltages, Figure (4b) affirms




 r R 
r
r
cc  E
D
D
E  
E   D
(21)
E  
.
o
 2r  R  R  2r  R  D1  2r  R  D2
cc 
cc 
cc 
 D
 D
 D
Assuming that the three noise sources are uncorrelated, the mean square value of the output noise
voltage follows as
2

 2 
r
r
2
2
D
D
 E 
e (t)  E  
o
o
 2r  R  R  2r  R
cc 
cc
 D
 D
2
2
 2
 r R  2
cc  E
 E  D
.
 D1  2r  R  D2
cc 

 D
Using (19) and (20), as well as the fact that in the present case,
E2
D1
 E2
D2
 E2 ,
(22)
(23)
D
(22) becomes, with the help of (20),


2
 2
2
r

r

R


r

D
cc 
D
 R Δf  2n kT  D
e 2 (t)  E 2  4kT 
r Δf .
o
o
cc
j
2  D
 2r  R 


cc 
 D
2r  R
D
cc


We note in Figure (4b), that the output resistance, RDout, of the diode divider is

R
Dout
 r
D
 rD  Rcc  .

(24)
(25)
This disclosure allows us to write (24) in the form,
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2
n 
 R
 

j
2
2
Dout
 R 
1 

e (t)  E  4kT 
1
o
o

 r  R   cc
2 

cc 
 D


R
2

  
 r Δf .
 D
 
cc 
r 
D 
Choma
(26)
Equation (26) suggests two important design considerations that are supportive of low
output noise in the diode divider topology. The first is a low output resistance. By (25) low
RDout requires small rD and hence, recalling that the diode small signal terminal resistance is inversely related to quiescent diode current, a robust static current conducted by the diodes.
Unfortunately, relatively large biasing currents are not synergistic with the low power design
realizations to which the extant electronics portability culture sensitizes us. The second
consideration is a need to ensure a low resistivity power line metallization in that (26) projects a
mean square output noise voltage that rises monotonically with resistance Rcc. One hopes that
resistance Rcc is significantly smaller than diode resistance rD, which is possible if the diodes do
not conduct large static current. If Rcc << rD, (26) collapses to the simpler relationship,
2
o


2
 kT R  n r Δf  kT n r Δf .
o
cc
j D
j D
e (t)  E
(27)
The foregoing results are summarized by Figure (4c), which offers the Thévenin noise
equivalent model evidenced at the output port of the diode divider. In this model, a dashed
branch is appended across the battery representing the static output voltage, VoQ, to remind that
constant sources of voltage are supplanted by short circuits in small signal analytical domains.
The short-circuited voltage branch is nonetheless included to dramatize the fact that the generated output noise serves to perturb the quiescent output voltage. To the extent that this bias output voltage is used to energize one or more transistors in the considered system, bias current
fluctuations incurred by noise are certainly possible.
The analytical procedure leading to (26) demonstrates the general analytical tack exploited to arrive at a noise voltage response for virtually any electronic circuit. In particular, we
first draw the noise equivalent circuit, we then apply superposition theory to relate the output response to each of the RMS noise generators, and finally, we square each individual term in the
superposition expression to arrive at the desired mean square result. Of course, the viability of
the last step presumes uncorrelated noise sources. The final step to the procedure is an insightful, design-oriented interpretation of the disclosed result. Unfortunately, however, the
particular diode divider result at hand is not rife with design insights, save for those addressed
above.
3.0.
NOISE ANALYSIS STRATEGY
Before turning our attention to the noise characteristics of MOSFET technology
amplifiers, which are rife with both passive and active noise sources, it may prove profitable to
expand on the cursory noise analysis generalization propounded at the conclusion of the preceding section of material. Our intent here is to establish systematic noise analysis procedures for
practical linear active networks that foster a tractable formulation and application of design insights serving to assuage the deleterious effects of noise. To this end, consider the linear active
network in Figure (5a), which is plagued by (p+q+1) uncorrelated sources of noise. Specifically, the noise model of the network contains p sources of voltage noise and q sources of current
noise that are generated within the considered linear active network. The mean square value of
Electronic Circuit Noise, Part II
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University of Southern California Viterbi School of Engineering
e1(t)
0
e2(t)
0
..
.
e (t)
0
p
Vi
Zs j1(t)
Vs
es(t)


*
..
.
0
Linear Active Network
e3(t)
j2(t)
..
.
j (t)
j3(t)
Zin
Vo
Vi
eo(t)
0
Zs
Vs
0

..
.
0
0

0
q
*
(a).
Choma
Linear Active Noiseless Network
Aos = Vo /Vs
Technical Report #03-0511
Vo
(b).
V1



V2


V3


..
.V
Vs


.
.
.
.
o1
A
o2
A
o3
p
Vi
Zs
A
Aop
Aos
I1
Vo
Z o1
I2
I3
..
.I
q
Lin Zoq Zo3 Zo
2
Te ear
s t N Ac
e tw tiv e
o rk

.
.
.
(c).
Figure (5). (a). A linear active network whose noise performance is modeled by signal source
noise, p internal noise voltage sources, and q internal noise current sources. All noise
sources are presumed uncorrelated. (b). Model for the determination of the I/O transfer
function, Aos, and the driving point input impedance, Zin. (c). Model used to evaluate
the gain sensitivities, Aoi and Zoj, with respect to the individual noise voltages and currents observed in the original network.
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the jth of these internal noise voltages is e 2 (t) , while the mean square value of the ith internal noise
j
current is designated as j 2 (t) . We shall also let Ej denote the RMS value of the jth noise voltage
i
and Ji be the RMS value of the ith noise current source.
Accordingly, e 2 (t)  E 2 , and
j
j
2
2
2
j (t)  J . A signal voltage, Vs, whose internal noise voltage has a mean square value of e (t)
i
i
s
and RMS value of E , is applied through a source impedance of Zs to the network input port,
s
which presents a driving point input impedance of Zin to the applied signal source. The response
of the network to the applied, and presumably time deterministic, signal is the indicated output
voltage, Vo, which, because of the (p+q) internal noise sources and the noise voltage implicit to
the applied signal source, is immersed in a sea of noise whose mean square voltage observed at
the network output port is e 2 (t) .
o
The first step underpinning a tractable noise analysis of the network in Figure (5a) is
the delineation of the I/O transfer function, Aos, which mathematically links the applied input
voltage signal, Vs, to the time deterministic output response, Vo, of the network. As suggested in
Figure (5b), we determine this transfer relationship by setting all noise sources to zero, which
leaves voltage Vs as the lone source of energy applied to the network. In a linear network, the
output voltage response, Vo, is directly proportional to Vs, whence a conventional small signal
analysis produces Aos as the I/O voltage -to- voltage gain ratio, Aos = Vo /Vs. Obviously, the signal source can be a current and/or the output response can be a current conducted by a branch
element in the overall amplifier model. But despite these alternative input and output signal
waveforms, computing the foregoing I/O gain as a foundational condition for a definitive noise
analysis remains a requirement, subject to the understanding that the resultant I/O signal gain can
be a current gain, a transadmittance, or a transimpedance, as opposed to the voltage gain projected by Figure (5b). A closely related second analysis step is the routine determination of the
driving point input impedance, Zin, via conventional mathematical ohmmeter strategies.
Three important points surface immediately from the foregoing straightforward circuit
analysis. First, if analytical attention focuses on high frequency dynamics, gain Aos and input
impedance Zin are complex functions of frequency since the active devices embedded within the
linear network contain energy storage elements. These memory elements generally are either
diffusion (current dependent) or transition (voltage dependent) capacitances. In certain types of
broadbanded amplifiers or for cases when the signal frequencies of interest span well into the
tens of gigahertz, inductances may accompany the capacitances in the relevant high frequency
model. The second point of importance entails understanding that the mere action of setting all
noise sources to zero while computing the I/O gain of the network exploits classic superposition
theory. Implicit to the utilization of this theory is the presumption that with the signal source and
all noise sources activated, network linearity continues to prevail. Stated in yet another way,
with the signal and all noise sources set to their nonzero values, the small signal (and inherently
linear) model of the entire linear active network remains a valid, viable, and meaningful circuit
analysis tool. Finally, we note through a comparison of Figures (5a) and (5b) that the gain quantity, Aos, linking the applied signal source to the output voltage response is precisely the gain
quantity that couples the signal source noise to its contribution to the net mean square output
noise. This contention simply reflects the fact that the signal source and the signal noise genera-
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tors are interconnected in series with one another at the network input port. Accordingly, the
2
contribution of signal noise to the mean square output noise is little more than A
E 2 , where
os
s
Aos is recalled to be the I/O gain of the subject network.
3.1.
NET OUTPUT MEAN SQUARE NOISE RESPONSE
The next interlude to our noise analysis party entails determining the transfer factors
associated with each of the (p+q) internal noise sources. Network linearity and superposition
once again combine to expedite this task. In particular, we reduce to zero the signal noise
source, es(t), and we replace each of the p internal noise voltage sources by independent, time
deterministic signal voltages, V1, V2, V3, · · · Vp. We also replace each of the q noise current
sources by independent, time deterministic signal currents, I1, I2, I3, · · · Iq. In effect, the Vj and
the Ii become surrogate sources to the respective noise generators that they replace for the purpose of identifying the transfer factors associated with these noise sources. The resultant linear
network becomes the architecture displayed in Figure (5c). We then ascertain the linear effects
of each of the surrogate signal sources −one at a time− by setting to zero all other signal sources
(including Vs) to find the transfer ratio, Aoj, for the jth voltage source and transimpedance Zoi for
the ith current source. Specifically,
Aoj 
V
o
V Vs 0
,
(28)
.
(29)
j V 0,i  j
i
All I 0
i
and
Z oi 
V
o
I Vs 0
i I 0, j  i
j
All V =0
j
Of course, for the fundamental I/O transfer function, Aos,
V
.
Aos  o
V All I i 0
s
(30)
All V 0
j
Because of the strict presumption of network linearity, we can elect to set voltage Vj in (28) to a
convenient 1-volt value, which makes the resultantly computed output voltage response, Vo, in
(28) numerically equivalent to the voltage transfer function from the jth noise voltage source -tothe network output port. Similar commentary can be advanced for current Ii in (29) and voltage
Vs in (30).
Superposition theory now enables us to write for the output signal voltage, Vo, in Figure
(5c),
V
o
 AosVs 
p
q
 Aoj V j   Zoi Ii .
j 1
(31)
i 1
Since all (p+q+1) sources of electrical noise are presumed uncorrelated, (31) gives precipitates a
net mean square (square of RMS value) output noise voltage of
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2
o
University of Southern California Viterbi School of Engineering
2

o
e (t)  E
2
A
p

2
s
E 
os
A
2
oj
j 1
2
j
E 
q
 Zoi
i 1
2
Choma
2
i
(32)
J .
It is worthwhile interjecting that in addition to facilitating a straightforward computation of the
net mean square output noise response, the Aoj and Zoi, per (28) and (29), respectively, convey
the effective sensitivity of net output noise to the jth noise voltage and the ith noise current,
respectively. For example, if we lived in electronic fantasyland where Aoj = 0 and Zoi = 0, (32)
shows that the only noise evidenced at the output port, despite prevailing internal noise sources,
is the noise arising from the signal source alone. In other words, the network undergoing
investigation boasts unity noise factor or 0 dB noise figure. While the foregoing special case indeed reflects pure fantasy, we can state in general that very small Aoj implies a relative output
noise insignificance to the jth internal noise voltage source, while very small Zoi advances a relative immateriality of the ith internal noise current source.
3.2.
NOISE FACTOR
Recall that the noise factor, F, is merely the ratio of the input -to- output signal -tonoise ratios; in generic form, this noise factor is
F 
S N
i
S
o
N
i
V 2 E2
s
2

A
o
os
s
V 2 E2
s
o
,
(33)
In (33), we understand that the input signal variable, Si, symbolizes the mean squared value of
the signal source voltage, which is equivalent to the square of its RMS value, Vs. It follows that
2
the mean square value, So, of the output signal response is simply A
V 2 . Moreover, the outos
s
put noise variable, No, with reference to the system abstracted in Figure (5), is little more than the
square of the RMS output noise voltage, Eo, while the input noise variable, Ni, is the square of
the RMS value, Es, of input signal noise. Thus, (33) transforms to
F 
S N
i
S
o
N
i
E2
o
2

A
o
,
E2
s
os
(34)
and using (32), we conclude that
A
2
os
p
2
s
E 

A
2
A
os
p

 1
j 1
A
oj
2
E
A
E
oj
j 1
F 
2
2

j
os
2
E
q

i 1
E2
s
2

j
q
 Zoi
i 1
2
s
2 2
J
i
(35)
2 2
Z
J
oi
i
.
As we projected earlier, F = 1 if no internal noise sources prevail. Moreover, the noise factor
converges toward its minimum unity value if the squared magnitudes of all Aoj and all Zoi are
small. The final functional form on the right hand side of (35) renders clear that noise factor F
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effectively compares the mean square output noise generated by all of the noise sources internal
to the considered network to the mean square output noise incurred exclusively by noise generated in the signal source. In attempt to dispel notational confusion, it may be prudent to underscore herewith that Es, Ej, and Ji in (35) represent RMS values of the signal source noise, es(t), the
jth internal noise voltage, ej(t), and the ith internal noise current, ji(t), respectively.
3.3.
EQUIVALENT INPUT NOISE
Figure (6) refreshes our understanding of the engineering significance of the equivalent
input noise voltage, en(t), whose RMS value is En, and the equivalent input noise current, jn(t),
whose RMS current value is denoted by Jn. In particular, with all internal noise sources of the
linear active network undergoing investigation reduced to zero so that the subject network is
noiseless and in addition, with the signal source noise constrained to zero, en(t) and jn(t) are the
only sources of noise to which the network is exposed. These two equivalent noise sources are
*
Linear Active
Noiseless Network
es(t)
jn (t)
Zin
Zs
*
meaningful if and only if their respective mean square values, e2 (t) and j 2 (t) , combine to pron
n
duce a computed mean square output noise voltage for the noiseless form of the considered linear active network that is identical to the mean square noise observed at the network output port
in Figure (5a) when the signal source noise is reduced to zero. In a word, En and Jn account only
for the effects of noise generated within, but not applied to, the subject network. This accounting
duly embraces any noise generated by the load that terminates the output port if, in fact, such
loading is considered an implicit part of the linear active network.
en (t)
eni (t)
eo (t)
Figure (6). System level illustration of the concepts of the equivalent input
noise voltage, en(t), and the equivalent input noise current, jn(t).
The determination of the equivalent input noise voltage and current obviously requires
an awareness of the mean square value, e 2 (t) , of the net output noise voltage, eo(t). It is also
o
expedient to evaluate the voltage gain, Aoi, from the input port -to- the output port in the network
of Figure (5b). Clearly, this port gain is the previously determined voltage gain, Aos, under the
condition of a null source impedance, Zs; that is,
V
V
 A
(36)
A  o  o
.
oi
os Z 0
V
V
s
i
Electronic Circuit Noise, Part II
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s
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We observe in Figure (6) that the input port noise voltage, eni(t) is identically equal to
noise voltage en(t) under the conditions of zero source impedance and zero source noise; that is,
Zs = 0 and es(t) = 0. Hence, we arrive at the mean square value of the equivalent input noise voltage by computing the mean square value, e 2 (t) , of the input port noise voltage, eni(t), in accorni
dance with
e 2 (t)  E 2  E 2 Z 0
n
n
ni s
E2
o

A
e (t)0
o

2
A
Z 0
s
e (t)0
oi
ns
E2
os
ns
2
.
(37)
Z 0
s
e (t)0
ns
Using (32), we can expand this result to
e 2 (t)  E 2 Z 0
n
ni s
 p A 2

q Z 2
oj

2
2
oi
E 
J 
.
 
j
i
A
A
 j 1 os

i 1 os

 Z 0
s
E2
o

A
e (t)0
oi
ns
2

Z 0
s
e (t)0
ns

(38)
We also observe in Figure (6) that if the source impedance, Zs, is infinitely large, the input port noise voltage is necessarily produced exclusively by the flow of noise current jn(t) into
the input port of the network. Thus, with Jn representing the RMS value of the equivalent input
noise current, jn(t),
e 2 (t)  E 2
ni
 Z
ni Z 
s
2 2
J ,
in
n
(39)
whence,
E2
j 2 (t)  J 2 
n
n
ni Z 
s
Z
2
in
E2
o

Z
2
in
A
.
2
oi
(40)
Z 
s
Equations (38) and (40) establish the mathematics for identifying the mean square values (or the
square of the RMS values) of the equivalent input noise voltage and the equivalent input noise
current that act to mirror the original output port noise response of the considered two-port network when such network is divorced of signal noise. We note that when the input impedance,
Zin tends toward infinity, as it does, for example, in common source and source follower
configurations that operate at low -to- moderate signal frequencies, the equivalent input noise
current is forced to zero.
4.0.
NOISE IN ANALOG MOSFET CIRCUITS
Our ability to extract design insights from a sedulous investigation of the noise
characteristics projected by the canonic cells of analog MOSFET technology is implicitly dependent on our understanding of how noise and small signal device parameters intertwine. To this
end, we depict in Figure (7) the approximate, small signal, noise equivalent circuit of a
MOSFET. No attempt is made herewith to model definitively such high order effects as mobility
degradation, carrier velocity saturation, and other phenomena that are largely indigenous to short
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channel devices. Nevertheless, the model topology set forth by Figure (7) remains the same for
deep submicron transistors, but the analytical expressions given below for certain model parameters necessarily differ[3]. While such expressions are available in the literature, it may be more
productive merely to extract the numerical values of key model parameters directly from SPICE
computer-aided simulations of the active devices undergoing scrutiny.
(D)
Id
(G)
(B)
NMOS
NMOS
Vgs
Vbs
Vds
(S)
(D)
eng(t)
gmV1
bgmV 2
ro
 V1 
*
(G)
Cgd
rg
jnds(t)
(S)
Cgs
 V2 
Cbd
(B)
Cbs
(D)
Id
Vsd
PMOS (G)
(B)
Vsg
PMOS
Vsb
(S)
Figure (7). The small signal noise equivalent model for both N-channel (NMOS) and P-channel
(PMOS) MOSFETs operated in their saturation regimes.
It should be understood that NMOS and PMOS transistors share identical equivalent
circuits even though the net drain current, Id, flows into the drain of NMOS, but out of the drain
in PMOS. Moreover, the NMOS polarities of drain-source voltage, Vds, total gate-source voltage, Vgs, and net bulk-source voltage, Vbs, are respectively reversed in PMOS to establish
correspondingly a source-drain voltage, Vsd, a source-gate voltage, Vsg, and a source-bulk voltage, Vsb. In the saturation regime, where MOSFETs are generally biased for most analog
applications, we require for given threshold potential Vh that
V  V
gs
h
(41)
,
V  V V  V
ds
gs
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dsat
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for NMOS transistors. Voltage Vdsat in this equation pair is the drain saturation voltage 1 .
Additionally, we require Vbs ≤ 0 to preclude current conduction in the p-type substrate bulk of the
device. Ordinarily, non-positive bulk-source voltage is achieved by returning the bulk terminals
(B) of all NMOS devices to the lowest of available fixed circuit potentials, which is to say that
for small signals, the bulk terminal is grounded, as is depicted in Figure (7). For PMOS devices,
(41) changes to
V  V
sg
h
(42)
,
V
 V V  V
sd
sg
h
ssat
where threshold potential Vh remains a positive number and Vssat is the source saturation voltage. Additionally, Vsb ≤ 0 to preclude current conduction in the n-type substrate bulk of a
PMOS device. Ordinarily, non-positive source-bulk voltage is achieved by returning the bulk
terminals (B) of all PMOS devices to the largest of available fixed circuit potentials. As in the
case of NMOS, this means that the bulk terminals of PMOS rest at signal ground.
An abridged itemization of all small signal parameters in the model of Figure (7) fol.
lows
(1). Capacitance Cgs is the gate-source capacitance of the transistor. In saturation,
2
2 WL ox
C
,
 WLC  C

C
(43)
gs
ox
gov
gov
3
3 T
[4]-[5]
ox
where W is the gate width, L is the geometric source-drain channel length, Tox is the gate
oxide thickness, Cox is the density of the gate oxide capacitance, and εox is the dielectric constant of silicon dioxide [345 fF/cm]. Finally, Cgov is the component of gate-source capacitance associated with gate oxide overlap with the source implant. In self-aligning gate
technology, Cgov is minimal.
(2). Capacitance Cgd is the gate-drain capacitance of the transistor. In saturation, this capacitance is almost exclusively the overlap capacitance, Cdov, associated with the gate oxide overlap with the drain region implant. Like Cgov, Cdov is typically small.
(3). Capacitance Cbd is the bulk-drain depletion capacitance. This capacitance varies inversely
with nominally a square or cube root function of the bulk-source voltage. Similarly, Cbs
represents the bulk-source depletion capacitance. It is inversely related to a square or cube
root function of the bulk-source potential.
We note that each of the four capacitances highlighted above can be supplanted by open circuits
when circuit analyses focus on relatively low signal frequencies that lie well within the frequency capabilities of the considered transistor.
(4). In the saturation region, gm, which is the forward transconductance of the transistor, is
roughly proportional to the square root of the quiescent drain current, Id. It can be approximated as
g
m

c ox 
2 C
W L I
d

c ox 
  C
W L V
gs
V
h
,
(44)
where carrier mobility μc assumes either its electron mobility value, μn, or its hole mobility
value, μp, depending on whether the considered transistor is NMOS or PMOS, respectively.
1
In deep submicron devices, the effect of carrier mobility degradation manifested by applied drain-source voltage is
to reduce the drain saturation voltage from its long channel value of (Vgs − Vh). This reduction can be of the order of
as much as a factor of two.
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Additionally, the well-known Schichman-Hodges square law model is invoked to express
the relationship of the static drain current, Id, to the excess gate-source voltage, (Vgs − Vh)[6].
(5). The transconductance, λbgm, represents the bulk transconductance of the transistor. It arises
from the mild dependence of threshold voltage on bulk-source bias. Parameter λb is generally smaller than 0.15 and is directly proportional to the thickness of the gate oxide. Thus, a
thinner oxide produces the desirable result of a smaller bulk transconductance.
(6). Resistance ro is the drain-source channel resistance. In the saturation regime, it is given by
V V V

ds
dsat ,
(45)
r 
o
I
d
where Vλ, the channel length modulation voltage, is directly proportional to the geometric
channel length, L. Long channels therefore give rise to large ro, although small drain currents flowing through deep submicron devices also produce large channel resistances. For
PMOS devices, Vds and Vdsat in (45) are supplanted by Vsd and Vssat = (Vsg − Vh), respectively. Since resistance ro is a small signal mathematical artifact, as opposed to a physical
resistance, it causes no thermal, or Johnson, noise.
(7). Gate noise is modeled by two parameters: a noise generator, eng(t), whose RMS voltage is
Eng, inserted in series with a second parameter that is the gate resistance, rg. The mean
square value of this gate noise voltage is
e 2 (t)  E 2
ng
ng
 4kT  r Δf ,
(46)
g
where in the saturation domain,
1
r 
g
5  C W L  V  V

c ox
gs
h


1
5g
.
(47)
m
Parameter δ, the gate noise coefficient, is typically assigned a value approaching δ = 4/3.
We observe that resistance rg, and hence the mean square gate voltage in (46), increases
with longer channel lengths, narrower gate widths, thicker gate oxides, and smaller drain
currents, which correspond to a smaller excess gate voltage, (Vgs − Vh).
(8). The drain circuit noise is an amalgam of the effects of thermal noise in the inverted portion
of the drain-source channel, shot noise in the depleted part of the channel, and flicker phenomena. The mean square value of this noise current, jnds(t), which postures an RMS current
value of Jnds, is
f 

j 2 (t)  J 2  4kT  g  1  c  Δf ,
(48)
nds
nds
m

f


where the empirical noise modeling parameter, γ, abides by

2
.
 

(49)
2
3
Moreover, fc in (48) is the flicker noise corner frequency. This frequency domain flicker
noise metric is given by
 f
4WLK  T
f  3k
 m
f 
c
kT  g
2



 .
(50)
m
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where Kf is the flicker noise coefficient, fT is the unity gain frequency of the transistor, and
C
gs
k 
.
(51)
m
C C
gs
gd
Since gate-drain capacitance Cgd is merely a small overlap component in saturated transistors, parameter km tends toward unity. From (48), we see that for frequencies satisfying f
>> fc, flicker noise effects are minimal. We note further from (49) and (50) that the constraint, f >> fc, is progressively easier to satisfy for transistors boasting small channel length
(small L) or for transistors characterized by small fT. While short channel transistors generally boast large fT, the fT of a particular transistor can be artificially degraded by appending
capacitance across the gate-source terminals. This design tack takes advantage of the fact
that fT derives as
k g
f  m m .
(52)
T
2 C
gs
The approach is effective in offsetting flicker noise phenomena as long as the potential
degradation incurred in effective gain-bandwidth product does not inflict a substantial penalty on the response passband requirements of the circuit undergoing development.
4.1.
CURRENT SOURCE NOISE
N-channel current sinks and P-channel current sources are commonly used in such analog applications as biasing subcircuits, balanced differential pairs, and Gilbert multipliers. The
ubiquity of these subcircuits logically dictates that we examine their noise properties. To this
end, consider Figure (8a), which shows the basic circuit schematic diagram of a current sink
utilizing a source degeneration resistance of Rss. The circuit sinks a constant drain current bias,
Ibias, when voltage Vbias is suitably larger than the threshold voltage of the transistor and the drain
is incident with a circuit node (K) that supports a sufficiently positive voltage, Vk. In order for
the transistor at hand to operate in its saturation domain, Vk must be capable of supplying the
sum of the MOSFET drain saturation voltage and the static voltage drop established across resistance Rss.
Two metrics quantify the overall quality of a current sink. The first of these is the output resistance, Rout, whose target design value is very large if the network is to approximate the
electrical operation of an ideal current sink. The second is the RMS value of the noise component, Jout, of the net drain current in the Norton equivalent circuit established between circuit
ground and the output circuit node (K). We display this low frequency Norton architecture in
Figure (8b), where Vks symbolizes the signal component of the voltage, Vk. In this model, current
source Ibias appears in a dashed network branch because strictly speaking, constant currents are
modeled as open circuits in small signal models. Ideally, we should like to have Jout null (meaning no noise is generated by the current sink). However, practicality allows us only to enforce
the compromise of a root mean square value of output noise current that is much smaller than the
biasing current, Ibias; that is, Jout << Ibias. The latter stipulation is conducive to a high signal -tonoise ratio at the current sink output port defined by node (K) and ground.
Because the current source is a de facto biasing network, we shall direct our attention to
only low frequency issues. Accordingly, Figure (9a) depicts the low frequency (sans device and
circuit capacitances and other energy storage elements), small signal model appropriate to the
calculation of the output resistance, Rout, of the subject current sink. The gate terminal of the
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transistor is grounded in this model because of our presumption that the gate biasing voltage,
Vbias, is established by a well-regulated static voltage source. The subject output resistance derives as the voltage -to- current ratio of the mathematical ohmmeter variables, Vx and Ix; that is,
Rout = Vx /Ix. An inspection of the model at hand produces
Vk
(K)
Rout
Ibias
(K)
Vks
Vbias
Rout
Ibias
Jout
Rss
(a).
(b).
Figure (8). (a). A simple N-channel current sink employing a source degeneration
resistance, Rss. (b). Norton equivalent circuit at the output port of the
sink in (a). Resistance Rout designates the driving point output resistance of the current sink, Ibias is the desired drain biasing current, and
Jout is the RMS value of the net output noise current generated by the
sink. The branch conducting current Ibias is shown dashed to imply an
open circuited branch because sources of constant currents behave as
open circuits under small signal conditions.
V
x
 r
o
V  V
1
2
 I s  gmV1  b g mV2   Rss I x
 R I
(53)
.
ss x
From these results, we conclude
V
 x  1   g  1   g  R r  r  1  1   g r  R ,
R
out
b m  ss o
o 
b m o  ss
 o
I
x






(54)
where go = 1/ro is the conductive equivalent of channel resistance ro. We record herewith that
the immediate purpose served by the source degeneration resistance, Rss, is the establishment of
an output resistance that is potentially much larger than the channel resistance, ro. To this end,
note that ro is the output resistance if Rss = 0; that is, Rout = ro if no source degeneration resistance is deployed.
While a source degeneration resistance produces the laudable current sink attribute of a
large output resistance, the unfortunate price paid for such degeneration is increased output port
noise levels. This operating detriment is inferred by the low frequency noise model we display
in Figure (9b), which incorporates a source degeneration resistance noise current of RMS value
JR. The mean square value of this Johnson noise generator is, with Δf representing the usual
noise equivalent bandwidth of the network into which the current sink is embedded and JR
symbolizing the RMS value of this current,
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2
R
j (t)  J
University of Southern California Viterbi School of Engineering
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4kTΔf
2

.
R
R
ss
(55)
Rout
(D)

gmV1
bgmV 2
(G)
 V1 
ro
Vx
(B)
 V2 
(S)
Ix

Rss
Ix
(a).
(D)
gmV 1
rg
bgmV2
ro
 V1 
*
eng(t)
Rss
jout(t)
jnds(t)
(B)
 V2 
(S)
jR(t)
(G)
(b).
Figure (9). (a). Low frequency, small signal equivalent circuit appropriate to computing the driving
point output resistance, Rout, of the current sink in Figure (8a). (b). Low frequency,
small signal, noise model used in the computation of the short circuit, or Norton, noise
current, jout(t), conducted by the drain of the current sink in Figure (8a).
Naturally, we include gate noise, whose RMS voltage value is Eng, and drain circuit noise, whose
RMS current value is Jnds, into the noise model. The mean square values of these two noise
sources derive from (46) -through- (51). The Norton equivalent output noise current, jout(t),
whose RMS value is Jout, is a superposition of the individual mean square noise contributions of
voltage eng(t) and currents jnds(t) and jR(t) to the output response.
We shall deduce these individual contributions to the net output noise by first replacing
the random energy sources, eng(t), jnds(t), and jR(t), by the time deterministic energy sources, Vng,
Inds, and IR, as depicted in Figure (10). This diagram delineates a short circuit, or Norton, output
current, Iout, which superposition theory dictates to be of the form,
I
 G V A I
A I ,
(56)
out
m ng
id nds
iR R
where Gm is the transconductance linking voltage Vng to current Iout, Aid is the current transfer ratio from Inds to Iout, and AiR is the current transfer ratio coupling current IR to current Iout. Once
we have evaluated Gm, Aid, and AiR, the uncorrelated nature of the individual noise sources,
whose RMS values are Eng, Jnds, and JR, produces
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University of Southern California Viterbi School of Engineering
j 2 (t)  J 2
out
 G
out
2
m
Choma
2 2
2 2
J
 A
J .
id
nds
iR
R
E2  A
ng
(57)
A straightforward analysis of the network in Figure (10), coupled with a direct application of the linear superposition expression in (56), delivers
(D) Iout
gmV 1
rg

ro
bgmV2
 V1 

V2

(B)
Vng

(G)
Inds
(S)
IR
Rss
Figure (10). Circuit model used to evaluate the transfer function scale factors associated
with the noise sources, eng(t), jnds(t), and jR(t), in Figure (9b). These noise
sources are in one to one correspondence with variables Vng, Inds, and IR in the
model.
I
 out
m
V
ng
G

I
nds
 I 0
R
g

m

1  g  1   g  R
b m  ss
 o

g r
mo ,
out
R
(58)
which literally identifies the effective forward transconductance from gate -to- drain of the current sink undergoing investigation. We note in (58) that the effective transconductance is identically the transistor transconductance if Rss = 0, which by (54) produces Rout = ro. Continuing,
I
r
G
1
o 
m .
(59)


A  out
id
I
R
g
g  1   g  R

1
nds V
out
m
0, I 0
b m  ss
 o
nd  g
R


Note that Aid = 1 if Rss = 0, which reflects expectations since Rss = 0 grounds the transistor
source terminal, thereby placing the current source, Inds, in shunt with the current sink output port
where we are measuring current, Iout. Finally,
g  1   g  R

I
r 
o
b m  ss
out
(60)
 
 1  o  .
A 
iR


I
R


1  g  1  g R
R V 0, I 0
out 

b m  ss
 o

ng
ds



Observe that if Rout >> ro, which is engendered by large Rss, AiR ≈ 1. It is interesting that while
(58) and (59) portend minimal sensitivity of short circuit output current to both gate and drainsource noise for large Rss, (60) suggests that large Rss (which makes Rout correspondingly large)
encourages the noise current generated by Rss to be transmitted directly to the output port of the
current source.
If the preceding three transfer relationships, along with the expressions for the noise
generators, Eng, Jnds, and JR are inserted into (57), we obtain a mean square output noise current
of
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2

R
 

out

 1 
2

 
 r 
f   ro

2
2
2

o
c

 Δf .
  g r   g 1   
(61)
 4kT 
j (t )  J
out
out
m


R   m g
f
R


ss
 out  





Generally, the first term within the bracketed quantity on the right hand side of (61), which is
precipitated by gate resistance noise, is insignificant. This contention is particularly true of deep
submicron transistors, which generally exhibit anemic forward transconductances for reasonable
static drain currents. On the other hand, the middle, or flicker noise, term and the last (source
degeneration) term are comparable for frequencies at least as large as the flicker corner frequency, fc. An illustration of these allegations follows from a consideration of Table (1), which
itemizes typical values for all parameters on which the right hand side of (61) is functionally
dependent. In consideration of this itemization, it turns out that at f = fc, the RMS value of output noise current is Jout = 180 nA, which gives an impressive signal -to- noise ratio for the given
2.0 mA of drain bias current of almost 81 dB. Moreover, the first (gate resistance) term on the
right hand side of (61) contributes just under 3% to the net mean square value of output noise
current. In contrast, the middle (flicker) and last (source degeneration) terms contribute about
45% and 52%, respectively, to the net mean square noise output response.
PARAMETER
DESCRIPTION
VALUE
UNITS
μc
Carrier Mobility
500
cm2/volt-sec
εox
Dielectric Constant of Silicon Dioxide
345
fF/cm
Tox
Gate Oxide Thickness
40
Angstroms
W/L
Gate Aspect Ratio
50
−−
Vgs − Vh
Excess Gate-Source Voltage
150
mV
Id
Drain Bias Current
2.0
mA
Rss
Source Degeneration Resistance
250
ohms
ro
Channel Resistance
10
K-ohm
λb
Bulk Modulation Factor
0.06
−−
−23
k
Boltzmann’s Constant
T
Channel Temperature
300.16
°K
Δf
Noise Equivalent Bandwidth
500
MHz
δ
Delta Factor
4/3
−−
γ
Gamma Factor
2/3
−−
1.38(10
)
joules/°K
Table (1). Representative numerical values for parameters pertinent to the noise analysis of the Nchannel current sink.
For the case of no source degeneration, we can easily verify that the flicker noise term
in (61) dominates the noise response. Since Rout = ro for Rss = 0, we conclude that
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f 

(62)
 4kT  g  1  c  Δf .
out
out R =0
m
f 
R =0

ss
ss
In contrast, for very large Rss, which is tantamount to the realization of Rout >> ro, the last term
on the right hand side of (61) dominates so that
4kT Δf
j 2 (t)
 J2

.
(63)
out
out g R >>1
R
g R >>1
j 2 (t)
 J2
ss
m ss
m ss
In other words, for very large Rss, the mean square value of the Norton noise current at the output
port of the simple current source in Figure (8a) is essentially the mean square current noise associated with the source degeneration resistance itself.
4.2.
NOISE IN ACTIVE VOLTAGE DIVIDER
The active voltage divider shown in Figure (11a) is commonly used as a biasing subcircuit in analog MOS applications. In particular, its fundamental purpose is to establish a predictable quiescent output voltage, VQ, which can be applied to bias the gates of current sinks or
sources that are utilized in these applications. The subject divider consists of the series
interconnection of two diode-connected monolithic transistors, M1 and M2, which are identical,
save for the likelihood of differing gate aspect ratios. The ratio of these gate aspect ratios, which
we write herewith as
Rout1
Vdd
Id2

Va
M2

gm1Va
b1gm1Vb
ro1 Vx1

Ix1

Rout2
Id1
 Vb 
VQ
Rout1
M1
(b).
Rout

Vc
gm2Vc
b2gm2Vd


(a).
Vx2
ro2
 Vd 
Rout2
Ix2

(c).
Figure (11). (a). Circuit schematic diagram of a static voltage divider formed as the series
interconnection of two diode-connected MOSFETs. (b). Low frequency, small signal
equivalent circuit used to evaluate the resistance, Rout1, presented to the output port by the
M1 subcircuit. (c). Low frequency, small signal model used to compute the resistance,
Rout2, presented to the output port of the divider in (a) by the M2 subcircuit.
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W
University of Southern California Viterbi School of Engineering
L
2  2 ,
W L
1 1
2
Choma
(64)
determines the factor by which the power supply voltage, Vdd, is divided down to the desired
quiescent output voltage, VQ. This fact is easily confirmed if we use the simple square law
model for the static volt-ampere characteristics of each transistor. In particular and with reference to Figure (11a), the static Schichman-Hodges model gives for the drain currents, Id1 and Id2,
conducted by transistors M1 and M2, respectively[6],
2
 C W 
(65)
 n ox  1  V  V
I
d1
h1
2 L  Q
 1
and
2
 C W 
(66)
 n ox  2  V  V  V
I
.
d2
Q
h2
2  L  dd
 2
In these two relationships, we have allowed for different device threshold voltages, Vh1 and Vh2,
despite the matched nature of the two transistors. These differences arise because while the
grounding of both the bulk and source terminals of transistor M1 forces the bulk-source voltage
of M1 to zero, the source of M2 is not grounded, but its bulk is, thereby forcing a bulk-source
voltage applied to M2 of −VQ. Thus, bulk-induced threshold voltage modulation occurs in
transistor M2, but not in M1. Additionally, we have taken the oxide capacitance density, Cox, and
carrier (electron) mobility μn to be respectively the same in both devices. However, the assumption of identical mobilities is an approximation in that this physical metric is influenced by drainsource voltage, which is the same for both transistors in Figure (11a) if and only if the circuit is
designed to deliver VQ = Vdd /2. But regardless of the value of the output voltage, VQ, Figure
(11a) confirms that the drain current of transistor M2 necessarily flows into the drain of transistor
M1. This is to say that Id1 ≡ Id2 Δ IdQ, where IdQ denotes the quiescent current drawn from the
supply voltage, Vdd, by the divider network. With Id1 = Id2, (65) and (66) combine to yield
V
  
 h1 .
(67)
V  
V V

Q
h2
 1
   1  dd
Equation (67) substantiates our allegation that parameter η, as defined implicitly by (64),
instrumentally influences the observable quiescent output voltage, VQ. Moreover, we note that if
Vh1 ≈ Vh2, VQ = Vdd/2 for η = 1, which, by (64), implies identical gate aspect ratios between the
two transistors in Figure (11a).






If the network in Figure (11a) is to serve as a viable source of constant voltage for current sink/source biasing or related other analog purposes, the indicated output resistance, Rout,
should be relatively small. We shall shortly see that small Rout also reduces the net output noise
generated by the divider network. The subject output resistance is the parallel combination of
the resistance, Rout1, seen looking into the drain/gate node of M1 and the resistance, Rout2, witnessed at the source terminal of transistor M2. Figure (11b) depicts the small signal model pertinent to the computation of Rout1 as the voltage -to- current ratio, Vx1/Ix1, while Figure (11c) gives
the companion model for computing Rout2 as the ratio, Vx2/Ix2. In Figure (11b), we note that control voltage Va appears directly across, and in associated reference polarity with, the controlled
current source, gm1Va, which means that this controlled source behaves as a simple branch
conductance of value gm1. Moreover, Vb = 0, thereby clamping the bulk transconductance term,
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λb1gm1Vb, to zero. These issues reduce the model at hand to a shunt combination of conductance
gm1 and resistance ro1, whence resistance Rout1 follows as
r
1
1
o1
R



.
(68)
out1
g g
1 g r
g
m1
o1
m1 o1
m1
The approximation in (68) exploits the reasonable presumption that gm1ro1 >> 1. In Figure
(11c), voltage Vc appears across, and in associated polarity with, the controlled current source,
gm2Vc, and similarly, voltage Vd is established across the terminals of the controlled source,
λb2gm2Vd. Consequently,
r
1
1
o2
R



,
(69)
out2
g
 g
g
g
1 1 
g r
m2
b2 m2

o2
b2

m2 o2
m2
where the approximation reflects the assumptions, λb2 << 1 and gm2ro2 >> 1. To the extent that
bulk transconductance factor λb2 is significantly smaller than one, a comparison of (68) with (69)
conveys the small influence that bulk-induced threshold voltage modulation exerts on the two
output resistance quantities. We conclude that the net output resistance presented at the divider
output port is, recalling (44) and (64),
1
R
 R
R

,
(70)
out
out1 out2
  1 g
m1
which is indeed reasonably small for any quiescent output voltage if the gate aspect ratio of
transistor M1 is large and/or the divider draws a moderate level of quiescent current from the
power bus. In arriving at the final form expression on the right hand side of (70), we have used
(44), (64), and the fact that since the static drain currents, Id1 and Id2, conducted by transistors M1
and M2 are identical,
g
m2 
g
m1
W2 L2  I d 2
2  C W L  I
c ox 1 1 d1
2 C
c ox

W
L
W
L
2
1
2
 ,
(71)
1
An assessment of the noise characteristics of the divider network before us takes the
form of determining the open circuit RMS noise voltage, say EQ, generated at the divider output
port. This procedure is compatible with a proscribed bias response, VQ, in that since no load is
shown terminating the divider output port in Figure (11a), VQ is an open circuit output voltage.
Thus, finding EQ enables a quantitative assessment of the divider design by merely comparing
the RMS open circuit output noise voltage to the open circuit quiescent voltage developed at the
output port. In turn, our strategy for calculating EQ embraces an exploitation of superposition
theory in that we shall first determine the open circuit RMS noise voltage, EQ1, generated by the
M1 subcircuit alone, followed by a computation of the open circuit RMS noise voltage, EQ2, arising solely from the M2 subcircuit. Assuming that these two noise voltages are uncorrelated, we
shall then arrive at the mean square value of the output noise voltage by merely summing the
mean square voltage values of EQ1 and EQ2.
To the foregoing end, Figure (12a) depicts the noise equivalent circuit pertinent to
determining the RMS noise voltage, EQ1, manifested exclusively by the M1 subcircuit in Figure
(11a). Figure (12b), which incorporates the output resistance, Rout2, as the terminating load imposed on the M1 subcircuit, depicts the equivalent circuit germane to determining the noise
transfer sensitivities, Ag1 and Rd1, with respect to the noise sources delineated in Figure (12a) as
eg1(t) and jds1(t) respectively. Since the bulk-source voltage, V2, in the model of Figure (12a) is
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zero, the dependent current generator, λb1gm1V2, is omitted in the diagram of Figure (12b). A
straightforward circuit analysis of the model in Figure (12b) reveals a transfer function, say Ag1,
with respect to test signal Vg1, and thus a transfer sensitivity with respect to noise eg1(t), of
eQ1 (t)
eg1(t)
gm1V1
*
ro1
b1gm1V2
jds1(t)
 V2 
 V1 
rg1
Rout2
(a).
VQ1

Vg1
gm1V1

rg1
ro1
Rout2
Ids1
 V1 
(b).
Figure (12). (a). Noise equivalent model of the M1 subcircuit in the divider of Figure (11a).
Note that V2 in this model is null, which necessarily clamps the controlled source,
λb1gm1V2, to zero. (b). Model used to compute the transfer sensitivities with respect to the noise sources, eg1(t) and jds1(t), in (a).
V
Q1


g1
V
g1 I 0
ds1
A
 Rout2 ro1  
1  g R
r
m1 out2 o1 
g
m1
g
m1
1 g
g
m1
m2
g
,
(72)
m2
where we take ro1 >> Rout2 and have invoked (69). In turn, (71) allows us to rewrite (72) as
V
g
g
1
Q1
m1 m2


(73)
A 
.
g1
 1
V
1 g
g
g1 I
ds1
0
m1
m2
A similar analysis of the same model reveals a transresistance, Rd1, with respect to current Ids1 of
V
R
r
1

Q1
out2 o1
R




.
(74)
d1


I
 1 g
 1 g


1

g
R
r
ds1 V 0
m2
m1
g1
m1

out2 o1

It follows that

I
 1 
ds1  .

V
 

 g1
Q1
g 
   1  
m1 
(75)
V
We now turn our attention to a determination of the RMS noise voltage, eQ2(t), manifested exclusively by the M2 subcircuit in Figure (11a). To this end, Figure (13b) is the equivalent circuit pertinent to calculating the noise transfer sensitivities, Ag2 and Rd2, with respect to the
noise sources delineated in Figure (13a) as eQ2(t) and jds2(t), respectively. Conventional analyses
Electronic Circuit Noise, Part II
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University of Southern California Viterbi School of Engineering
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of the circuit model in Figure (13b) highlight a transfer function, say Ag2, with respect to signal
Vg2, and a transresistance, Rd2, with respect to current Ids2 that are given by
eg2(t)
gm2V3
*
ro2
b2gm2V4
 V4 
eQ2(t)
 V3 
rg2
jds2(t)
Rout1
(a).

Vg2
gm2V3

ro2
b2gm2V4
 V4 
VQ2
 V3 
rg2
Ids2
Rout1
(b).
Figure (13). (a). Noise equivalent model of the M2 subcircuit in the divider of Figure (11a).
(b). Model used to evaluate the transfer sensitivities with respect to the noise
sources, eg2(t) and jds2(t), in (a).
A
g2

V
Q2
V
g2 I

ds2
0
R
r

out1 o2 


1  1    g  R
r 
b2 m2 out1 o2
g
m2

(76)
 1
and
V
Q1
R
r
out1 o2

 
d2
I
1  1 
g
R
r
ds2 V 0
b2 m2 out1 o2
g2
R





where we have assumed λb2 << 1 and have used (68) and (71). Thus,

I
  
ds2  .

 

V
V
 g2
Q2
g 
   1  
m2 

  1 g m2
,
(77)
(78)
Superposition theory now allows us to assert that owing to the four independent generators, Vg1, Vg2, Ids1, and Ids2, the net, small signal, open circuit output voltage, say VQs, of the subject divider network is
I
 I ds2 
 1 
ds1 

,
 V V
 


V
V

V
(79)
 g1
Qs
Q1
Q2
g2 g

g
   1  
m1
m2 
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
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from which the open circuit, mean square, output noise voltage follows, assuming all noise
sources are uncorrelated, as
2 
2
J2
 2 J ds2
 1   2
2
2
2 2
ds1
.
(80)
e (t)  E  
  E g1   E g2  2 
Q
Q
2



1

 
g
g
m1
m2 

Appealing to (71) and (70), (80) becomes
2
2
e (t)  E 
Q
Q
E
2
g1
  1
2

 2 E g2 2
  1
2


2
2
2
J
J
,
out ds1
ds2
 R
(81)
which suggests that a small output resistance, Rout, exculpates drain-source noise current as a
dominant contributor to the net mean square output noise voltage. Using (46), (48), and (49),
this mean square output noise voltage observed at the divider output port is seen to be

f
f 

2  1  c1 1  c2  
 r   2r
R
f
f 
g1
g2
e 2 (t)  E 2  4kT  
Δf .
(82)
 out 

Q
Q
2

 r

10
r

1


g2  
 
 g1


 
A study of this expression indicates that if Rout is held at a minimum, low output noise is effected
(at least at moderately high frequencies) when gate resistances rg1 and rg2 are small. From (47),
these resistances are minimal when the device channel lengths are small, the device gate widths
are large, and/or the gate oxide thicknesses of the transistors are small. The fundamental lesson
learned here is that short channel, high gate aspect ratio transistors are an apparent key to low
noise performance in the divider network of Figure (11a).
Vdd
Id2
M2
Rout2
Id1
M1
Rout
VQ
Rout1
(noisy)
VQ + eQ(t)

Rout
VQ

Figure (14). Macromodel of the active voltage divider introduced in Figure (11a).
For noise analysis purposes at high frequencies where flicker phenomena
are neutralized, the indicated output resistance, Rout, can be viewed
(approximately) as a conventional, thermally noisy resistance.
A considerable simplification of (82) and an interesting final result are afforded if we
ignore flicker phenomena, which is tantamount to assuming that the frequencies of interest are
substantially larger than both of the flicker corner frequencies, fc1 and fc2; that is, f >> fc1 and f
>> fc2. Using (47), (70), and (71), (82) can be collapsed into the form,
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
e 2 (t)
Q
f  f
c1
,f
c2
7

 E 2  4kT   R  Δf
Q
out
 10

(83)
Since δ ≈ 4/3, 7δ/10 = 14/15, which is almost one. Accordingly,
7

e 2 (t)
 E 2  4kT   R  Δf  4kTR Δf ,
Q
Q
out
out
 10

f  f , f
c1
Choma
(84)
c2
which suggests that the open circuit, mean square output noise voltage of the divider network in
Figure (11a) is equivalent to the thermal noise voltage generated by a passive resistance that is
numerically equal to the divider output resistance, Rout. This suggestion is inferred schematically
in Figure (14).
4.3.
NOISE IN COMMON SOURCE AMPLIFIER
Figure (15a) depicts the schematic diagram of a common source amplifier. In this version of the common source configuration, a source degeneration resistance, Rss, is used to
desensitize the gain of the stage with respect to uncertainties in the forward transconductance and
other small signal parameters of transistor M. The load is taken to be a simple passive resistance,
Rl, although in other embodiments of the amplifier, one or more diode-connected transistors or a
P-channel current source can be used. The power supplies, Vdd and Vgg, are selected to ensure
that transistor M operates in its saturation domain for all time. In concert with this saturation
constraint, Figure (15b) is the low frequency, small signal model of the subject architecture.
This equivalent circuit includes voltage and current sources that represent noise generated in the
gate [eg(t)], the drain-source channel [jds(t)], the source degeneration resistance [jss(t)], and the
load resistance [jl(t)]. Also included in this model is the noise generator, esn(t), which represents
noise associated with the signal source. In this analysis, we shall assume that noise in the signal
source arises exclusively from thermal phenomena in the Thévenin source resistance, Rs, so that
e 2 (t)  E 2  4kTR Δf ,
sn
sn
(85)
s
where, of course, Esn represents the RMS value of the noise voltage associated with resistance Rs.
Figure (16a) offers the small signal model pertinent to discovering the low frequency
I/O voltage gain, Avs = Vos /Vs. This circuit mirrors the structure in Figure (15b) with the proviso
that all presumably independent and uncorrelated noise generators are set to zero. A conventional circuit analysis produces an I/O voltage gain of
 R

V
outs    g
(86)
A  os   g R 
R
R ,
os
me l  R
me outs l
V
R 
s
outs
l


where, gme, the effective Norton transconductance of the common source network, is given by
 r

o

g 
mr  R 
g
ss 
 o
m
(87)
g
.


me
1
g
R

1  1  g r R


b
 m o
ss


m ss
The approximation in (87) invokes the reasonable presumptions that the bulk transconductance
factor, λb, is much smaller than one and that the drain-source channel resistance, ro, is much
larger than the source degeneration resistance, Rss. Both of these presumptions reflect reasonable
Electronic Circuit Noise, Part II
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University of Southern California Viterbi School of Engineering
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and desirable engineering circumstances. In (86), Routs is the output resistance of the common
source amplifier:
+Vdd
Rl
Rs
Vo
M

Vs


Rss
Vgg

(a).
Routs
esn(t)
Rs
*
Vos + eon(t)

V1

rg
eg(t)
*
bgmV2
ro
jds(t)
Rl
jl(t)

Rins

gmV1
V2
Vs
Rss
jss(t)


(b).
Figure (15). (a). A common source amplifier realized in NMOS technology with a source degeneration
resistance. Transistor M is presumed to operate for all time in saturation. (b). Low frequency, small signal equivalent circuit, inclusive of applicable noise generators, of the amplifier in (a). The performance metric, Routs, symbolizes the common source driving point
output resistance facing load resistance Rl, while Rins designates the driving point input
resistance. Voltage Vos is the small signal component of the output signal response, while
eon(t) abstracts the total noise voltage developed at the amplifier output port.




 1  1   g R  r  1  g r R  g r R .
(88)
b m ss  o
m o ss
m o ss

Note that the output resistance in (88) is identical to the current sink output resistance in (54).
This identity is viscerally correct since the output resistance of any amplifier is evaluated with
zero signal source applied. In turn, a null input signal (Vs = 0) in Figure (16a) effectively reduces the common source stage to the current sink architecture shown In Figure (8a).
R
outs
 R
ss
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University of Southern California Viterbi School of Engineering
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Routs
Rs
Vos

V1

rg

gmV1
ro
bgmV2
Rl
Rins
Vs

(a).

Vsn

rg

Rs
Von

V1

gmV1
bgmV 2
ro
Ids
Rl
Il

Vg

V2
Rss
Iss

(b).
Figure (16). (a). Small signal equivalent circuit used to compute the low frequency voltage gain, Avs
= Vos/Vs, of the common source amplifier diagrammed in Figure (14a). (b). Small signal, low frequency model used to evaluate the transfer sensitivities with respect to each
of the five noise sources indigenous to the common source amplifier in Figure (14a).
The most expedient way of evaluating the net mean square output noise voltage, e 2 (t) ,
on
of the amplifier at hand is to begin by evaluating the transfer sensitivities with respect to each of
the five amplifier noise sources that compel attention. To this end, Figure (16b) is the applicable
circuit model. While five sources of noise prevail in the small signal model depicted in Figure
(15b), we need only evaluate three transfer sensitivities in Figure (16b) since we already know
two of the requisite five sensitivities. In particular, the indicated voltages, Vg (corresponding to
gate RMS noise voltage Eg) and Vsn (corresponding to RMS signal noise voltage Esn) appear as
series elements in the same branch as does the actual signal, Vs, applied to the amplifier input
port. Therefore, the transfer sensitivities, Ag, and Asn, with respect to the surrogate noise excitations, Vg and Vsn, respectively, are each identical to the voltage gain, Aos, discerned previously as
(86). Specifically,
Electronic Circuit Noise, Part II
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
g
A
University of Southern California Viterbi School of Engineering
V
on
V
g
V 0, I 0
sn
ss
I 0, I 0
ds
Choma
V
os  A ,
os
V
s

(89)
l
and
V
 on
sn
V 0, I 0
V
g
ss
sn
A
I
ds
V
os  A .
os
V
s

0, I 0
(90)
l
Continuing with the noise sensitivity analysis of the structure in Figure (16b), we find
that the output noise sensitivity, Zss, with respect to the noise current manifested by resistance Rss
is the transimpedance,

V
r 
Z  on
R .
(91)
 1  o  R
ss

 outs l
V 0, V 0
I
R
sn
g
ss
outs 



I
ds
0, I 0
l
If Rss = 0, (88) confirms Routs = ro, whence Zss in (91) is zero; in other words, there is no noise
sensitivity to resistance Rss if Rss is a short circuit, which is abundantly reasonable. Since Routs
for nonzero Rss is invariably much larger than the terminating load resistance, Rl, the approximate form of (88) combines with (91) to offer
1 

r

o


r 
g 
1 
o
m  R  1 

 R
R .
(92)
Z  1 
R  1
ss

 l

 outs l

R
R
g R  l
outs 
ss 
m ss 






The last result asserts, albeit subliminally, that for large transistor transconductance and/or large
source degeneration resistance Rss, the noise current generated by Rss is transported directly to the
amplifier output port where it is converted to an output noise voltage component by the terminating load resistance, Rl.


For the current source, Ids, the transfer sensitivity, Zds, is
 r 
 r
V
on
Z 
R   o
  o  R
ds
R
 outs l
R
V 0, V 0
I
sn
g
ds
 outs 
 outs

I 0, I 0
ss


R .
 l

(93)
l
where the usual approximation, Routs >> Rl, is invoked. Finally, the transfer sensitivity, Zll, with
respect to the load current, Il, is easily demonstrated to be
V
on
(94)
Z 
 R
R  R .
ll
outs l
l
V 0, V 0
I
sn
g
l
I 0, I
ss
ds
0
We note that if Rss = 0, which is tantamount to constraining output resistance Routs to ro, Zds ≡ Zll.
This result is reasonable in that Rss = 0 connects current sources Ids and Il in shunt with one
another from the amplifier output port to signal ground.
Electronic Circuit Noise, Part II
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University of Southern California Viterbi School of Engineering
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The disclosures set forth by (89) through (94) foretell a mean square output noise voltage of
2
on


2
2
2
2
2 2
2 2
2 2
 A E E Z J Z J Z J ,
on
os sn
g
ss ss
ds ds
ll l
e (t)  E
(95)
where we understand Eon, Es, Eg, Jss, Jds, and Jl represent RMS values of pertinent noise voltages
or currents. In view of our awareness of the mathematical nature of noise currents and voltages
generated by passive resistances and the noise currents and voltages inherent to MOSFET devices, (95) becomes
2




 
r
1
 R   r  1  o  


 s

g

  g 2 R 
R
outs




 me ss 
(96)
e 2 (t)  E 2  A2 4kT 
f .

on
on
os
2






r
f 

1 
o
  
  g 1  c   
m


2

g R

f   g R  


me
outs


 me l  

An assiduous examination of (96) forges several noteworthy observations.
(1). The fact that the I/O voltage gain, Aos, in (86) is independent of the signal source resistance,
Rs, implies that the mean square value of the equivalent input noise voltage for the common
source amplifier derives simply from dividing the mean square output noise voltage in (96)
by the square of the I/O gain. Clearly, this result is
2




 
r
1
 r   1  o  


 g 

  g 2 R 
2
R
E
outs   me ss 



2
2
on
e (t)  E 
 4kT 
  f , (97)
n
n
2


A2



r
f 

os R 0
1  
o
c




g
1




s

m 
f   g 2 R  
  g me Routs 



 me l  

where Rs is set to zero to null the signal source noise. To this end, recall that the equivalent
input noise, which should be held at a minimum to enable the detection and faithful
processing of low level input signals, reflects to the amplifier input port the total output
noise generated only by the amplifier (exclusive of the signal source noise, which inherently
contaminates the input port of the amplifier).
(2). Equation (97) highlights the potentially egregious effect a source degeneration resistance exerts on the noise properties of a common source amplifier. In particular, if Rss = 0, the
second term within the bracketed quantity on the right hand side of (97) vanishes because
from (88), Routs ≡ ro if Rss = 0. Moreover, (87) shows that the effective transconductance,
gme, rises to its maximum value of gm, if Rss = 0. Otherwise, gme is a factor of (1 + gmRss)smaller than gm. In turn, the third and fourth terms on the right hand side of the expression
for the equivalent input noise voltage are minimized when gme is maximized. We can therefore argue that

Electronic Circuit Noise, Part II
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Technical Report #03-0511
2
e (t)
n
University of Southern California Viterbi School of Engineering


2
 E
 4kT  r 
n R 0
 g
g
R 0
m
ss
ss

f   1

 1  c   
f   g 2 R

 m l
2f 

c f
4kT  1 


3f 

,

g
Choma

  f
 
 
(98)
m
where we have exploited (47) and (49) and have presumed that the gain-related product,
gmRl, is much larger than one. If flicker noise is tacitly ignored, perhaps because of a high
frequency analytical focus, (98) reduces to
4kT  f
e 2 (t)  E 2
.

(99)
n
n R 0
g
m
ss
In a word, the high frequency, mean square value of the equivalent input noise voltage of a
common source amplifier is approximately the Johnson noise manifested by an effective
resistance of 1/gm when the amplifier is designed with no source degeneration resistance
deployed. Clearly, large gm, which mandates a large gate aspect ratio, a thin gate oxide,
and/or a relatively large quiescent drain current, is conducive to a small equivalent input
noise voltage. Of course, these design guidelines entail engineering compromises since
large gate aspect ratios and thin gate oxides increase device capacitances that can limit frequency response, while a large drain current does not conflate with low power dissipation
constraints or requirements.
(3). To gain a perspective of how source degeneration exacerbates the equivalent input noise
voltage of a common source amplifier, it is instructive to compare (98) and (99) to the
counterpart noise expressions for the case of large Rss. We recall that for large Rss, gme in
(87) is approximately 1/Rss. This fact, combined with (88) reduces (97) to
2f


c
1



R
3f
2
2
(100)
e (t)
 E
 4kT 
  1  ss  R   f .
n
n g R 1
ss 



g
R
g R 1
m
l 

m ss
m ss




The term within the bracketed quantity on the far right hand side of (100) can be viewed as
an effective thermal noise resistance, say Rn, for the equivalent input noise voltage. This is
to say that (100) can be written as
e 2 (t)
n
 E2
n g R 1
g R 1
 4kTR  f ,
m ss
m ss
n
(101)
with
1
2f
c

R 
  1  ss  R .
n

g
R  ss
m
l 

By comparison with (98), we conclude
R

3f
Electronic Circuit Noise, Part II
(102)
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August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
Choma

R 
(103)
  1  ss  R ;
n g R 1
n R 0

 ss
R
m ss
ss
l 

that is, the effective noise resistance, and thus the equivalent input noise voltage, increases
monotonically with source degeneration resistance, Rss. Recalling that δ ≈ 4/3, we note that
the equivalent noise resistance in (102) for high signal frequencies becomes

R 
1
(104)
R

  1  ss  R ,
n f  f

 ss
g
R
c
m
l 

which increases quadratically with Rss.
(4). Since the input impedance of a common source amplifier is infinitely large at low signal
frequencies, the equivalent input noise current for low frequencies is necessarily zero.
Accordingly, the input port noise floor voltage, say Vnf, is established by the root mean
square value of the sum of the mean square signal source and equivalent input noise voltages. As we noted earlier, an assurance of signal processing integrity requires that the
amplitude, say Vsp, of the applied, time deterministic signal exceed Vnf, which by (85), (101),
and (104) for the case of f >> fc and gmRss >> 1 is
 R
R



R 
1
ss


(105)
V 
4kT  R 
R  f .
 1
nf
s g

R  ss 

m 
l 

Equation (105) suggests that the signal source amplitude must be sufficiently large to overcome the thermal noise of a signal source resistance that is embellished by the sum of the
indicated quadratic function of Rss and the gate noise term to which the resistance, 1/gm, is
attributed.
(5). Recalling (34), (85), (86), and (96), the noise factor, Fs, of the common source amplifier before us is
2
2
 
 rg 
 g 
r  
r
f
1
o
o
m 1 c 
 
 

 1 
F  1


s

  g 2 R R   g R
 R 
R
R
f 
s
outs   me s ss   me outs 
s

(106)

1
g2 R R
me s l
.
With no source degeneration resistance (Rss = 0),
2f 
1 
1
1 
(107)
F
 1
 c,
s R 0
g R 
g R
3f 
ss
m s
m l

With zero source degeneration, the magnitude of voltage gain in the common source amplifier is close to the product, gmRl. If this gain magnitude is large, which helps to reduce
the noise factor, and if the signal frequencies of interest are large in comparison to twothirds of the flicker noise corner frequency, fc, (107) reduces to the simple result,
1
(108)
F
 1
,
s
g R
R =0
ss
g R , f large
m l
Electronic Circuit Noise, Part II
m s
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University of Southern California Viterbi School of Engineering
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which infers the importance of large transconductance to low noise operation. On the other
hand, large Rss yields
2f  
R R
1 
(109)
F
1  c    1  ss  ss ,
 1

s g R 1
g R 
3f  
R  R
m ss
m s
l  s

which is potentially much larger than the zero source degeneration noise factor prevailing in
(107).
Noise With Current Source Load
4.3.1.
A quotidian alternative to the common source amplifier shown in Figure (15a) is the
CMOS realization depicted in Figure (17). Because no signal voltage activates the gate-source
terminals of PMOS transistor MP in the CMOS network, MP behaves, for small, low frequency,
signals as a linear two-terminal resistance that is incident between the drain of transistor MN and
the power supply line, which is signal ground for small signals. This equivalent resistance derives directly from (54). To be sure, (54) applies to the NMOS current sink in Figure (8a) but for
small signals, the equivalent circuit for the sink in Figure (8a) is identical to the small signal
model for the PMOS current source embedded in the amplifier at hand. Accordingly, the current
sink macromodel in Figure (8a) applies to the PMOS current source. In view of the fact that the
PMOS unit does not incorporate source degeneration, (54) yields the simple result,
+Vdd
Vbias
MP
Routp
Routs
Rs
Vo
MN

Vs


Rins
Rss
Vgg

Figure (17). Basic schematic diagram of a source-degenerated,
common source amplifier exploiting an active
(PMOS) current source load.
R
outp
 r
op
(110)
,
where, of course, rop is the drain-source channel resistance of transistor MP. Moreover, the RMS
noise current, Joutp, produced by the MP subcircuit derives from (61). In particular,

f 
2f 


cp 
cp
2
2
2




 Δf . (111)
j
(t)  J
 4kT  g r   g
1
Δf  4kTg
1
outp
outp
mp
gp
mp
mp


f 
3f 






Electronic Circuit Noise, Part II
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August 2011
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University of Southern California Viterbi School of Engineering
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where we have invoked the usual relationship between gate resistance and transconductance, as
well as the usual approximations surrounding empirical parameters δ and γ. It is interesting that
whereas large transconductance (gmn) in the common source driver benefits the noise characteristics of a common source amplifier in accordance with (100), (107), and (109), large transconductance (gmp) exacerbates the load noise current in the CMOS architecture. Fortunately, gmp < gmn
even for identical static drain currents and identical transistor geometries because hole mobility,
to which the square of forward transconductance is directly proportional, is inherently smaller
than electron mobility.
We are now in a position to adapt the relevant results documented in the preceding
subsection of material for the common source amplifier directly to the CMOS stage in Figure
(17). In particular, the low frequency gain, Aos, in (85) is, in light of (87), (88), and (110),


V
g
mn
 R
 
A  os   g
R
R
R
os
me outs outp
 1  g R  outs outp
V
s
mn ss 

(112)


g
mn
 g r R
 
r .
 1  g R   mn on ss op 
mn ss 

The transimpedance sensitivities, Zss, Zds, and Zll, in (92), (93), and (94) become




1
1
  1 
  R
 g r R
(113)
Z  1 
R
r ,

ss
outs
outp

mn
on
ss
op 







g R
g R
mn ss 
mn ss 


r r
 r

on op
 
Z
  on   R
R
,
(114)

ds
R
  outs outp 
g
r
R
r

 outs 
mn on ss
op








and
Z
ll
 R
outs
R
outp



 g mnron Rss  rop .
(115)
Additionally, since the load imposed on the common source amplifier in the CMOS configuration is the PMOS current source, MP, the RMS load noise current, Jl, in (95) must now be supplanted by Joutp, per (111). It is immediately evident that the current source load increases the total mean square output noise of the amplifier operated with a passive load resistance. In
particular, the passive load imposed on the common source stage projects a mean square noise
current that is simply the thermal noise attributed to resistance Rl. In contrast, the active load imposes gate, channel, and flicker noise on the common source architecture. Specifically, we see
that J 2
outp
 J
2
l
if
2f 

cp

  1,
(116)
g R 1
mp l 
3f 


which is inevitably true at low frequencies and indeed likely to be true at all frequencies for
realistic values of the PMOS forward transconductance. The preceding disclosures combine
with (95) and (97) to deliver an equivalent input noise voltage for the CMOS stage of
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
2f


cn
1 



2f

3f
cp  


2



e (t)  4kT 
R  f ,
 1 g R 1
nc
mp ss 
3f   ss 

 g mn





where we have presumed gmnRss >> 1.
4.3.2.
Choma
(117)
Noise With Diode-Connected Resistive Load
Yet another modification to the venerable common source structure is the architecture
depicted in Figure (18a). In this schematic diagram, the common source driver transistor, MD, is
assumed biased in its saturation regime. This transistor operates without source degeneration because, as we shall confirm, the load transistor, ML, interacts with the driver in such a way as to
establish a voltage gain that is independent of small signal model parameters. The active load
configuration is such that the gate and drain terminals of transistor ML are connected together,
thereby framing the typically invoked nomenclature of a diode-connected load. Because the
bulk and drain-gate interconnection lie at signal ground, ML is guaranteed to operate in saturation and functions as an effective two-terminal device, the two terminals being the source terminal and signal ground. This circumstance, coupled with the fact that in principle, ML is modeled by a small signal, and therefore linear, equivalent circuit implies that ML functions as a twoterminal resistance for small signal (inclusive of noise) excitation. The resistance postured by
ML derives from (69); namely,
r
1
1
ol
R



,
(118)
outl
g
1 1  g r
2 C W L I

bl

ml ol
ml
n ox

l
l
 dQ
where we have exploited (44) and have presumed large channel resistance and small bulk
transconductance factor in ML. Additionally, IdQ in (118) is the quiescent drain current conducted by both transistors ML and MD.
The most efficient way to execute a tractable noise analysis of the present circuit entails
an adaptation of noise results deduced for the basic common source amplifier in Figure (15).
The noise model in Figure (15b) remains architecturally correct for the present amplifier, provided, of course, that we properly account for the absence of source degeneration. Moreover, we
must reduce the load device in Figure (18a) to a shunt interconnection of resistance, which in this
case is Routl, and a Norton load current noise, jl(t), as Figure (15b) delineates. In order to obtain
the mean square value of this load noise current, we defer to the small signal model in Figure
(18b), which supports the tasks of evaluating the transfer sensitivities with respect to gate noise
and channel noise in load transistor ML. Note that control voltage V2 is clamped to zero in this
Norton equivalent model, thereby nullifying any impact the controlled current, λblgmlV2, might
otherwise exert on the short circuit, or Norton, output noise current.
The first of the requisite sensitivities is the transconductance, Gsg = Isc /Vg1, where Isc is
the indicated short circuit load current and Vgl represents gate noise voltage egl(t), which by (46)
and (47) has a mean square value of
4kT  Δf
16kT  Δf
2
2
(119)
e (t)  E 

.
gl
gl
5g
15g
ml
Electronic Circuit Noise, Part II
ml
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August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
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The second sensitivity function is the current transfer ratio, Asd = Isc /Idsl, where Idsl relates to the
channel noise current, jdsl(t). From (48) and (49), this channel noise current has a mean square
value that is given by
+Vdd
ML
Routl
Routd
Rs
Vo
MD

Vs

Rins

Vgg

(a).

Vgl
gmlV1

rgl
blgmlV2
rol
Idsl
 V2 
 V1 
Isc
(b).
Figure (18). (a). Basic schematic diagram of a common source amplifier exploiting an active
(NMOS) resistance load. (b). Small signal model for computing the short circuit transfer sensitivities with respect to gate noise (represented by Vgl) and
channel noise (represented by Idsl), which are generated in the active load device, transistor ML.
f 

1  cl  Δf ,
(120)

dsl
dsl
ml 
f 

where fcl, which can be extracted from (50), is the corner frequency of the flicker noise current
associated with the load transistor. Straightforward analyses of the model in Figure (18b) produce
j 2 (t)  J 2
G
sg

I
 2kT  g
sc
V
gl I
 g
dsl
ml
,
(121)
0
and
Electronic Circuit Noise, Part II
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A
sd
I

I
sc
dsl V
g1
University of Southern California Viterbi School of Engineering
Choma
 1 .
(122)
0
Assuming no correlation between the two noise sources within the load transistor, it therefore
follows that the mean square value of the Norton equivalent noise current is
J 2  G 2 E 2  A2 J 2
l
sg gl
sd dsl
 g2 E2  J 2
ml gl
dsl
(123)
f 
2f 


cl
cl

 2kT  g  1 
 Δf  4kTg ml  1 
 Δf ,
ml 
5
f
3
f




where we have utilized the fact that δ ≈ 4/3. By comparison of this result with (111), we note
with more than casual interest that the diode-connected load transistor produces a short circuit
mean square noise current whose form is identical to the noise produced by the PMOS current
source load. To this end, the reader is invited to compare (123) with (111). And since the mobility of channel electrons in NMOS exceeds that of channel holes in PMOS, the Norton current of
the diode load can be expected to be larger than that of the PMOS current source for similar device geometries and biasing conditions.
4kT  g
ml
Δf
Now, let us return to the problem of calculating the noise performance of the amplifier
in Figure (18a). The mean square value of the total output noise voltage derives directly from
(95), where J 2 is given by (123), and by (94)
l
Z
ll
 R
outd
R
outl
 r
od g
1

ml
1
g
(124)
.
ml
From (93),
 r 
1
1
  o  R
R
 r

,
(125)
ds
outd
outl
od
R

g
g
ml
ml
 outd 
while the mean square value, J 2 , of the channel noise in driver transistor MD is, appealing to


Z
ds
(48) and (49),
f 
f 


8
1  c  Δf  kTg  1  cd  Δf ,
(126)

ds
md 
md 


f
3
f




where, of course, fcd is the corner frequency of the flicker noise associated with the channel of
the driver transistor. With Rss = 0, Zss in (91) is zero.
J 2  4kT  g
Recalling (86), the small signal voltage gain of the amplifier in Figure (18a) is
V
g
W L
d d ,
A  os   g
R
R
  md  
os
md outd outl
V
g
W L
s


ml
l
(127)
l
where we have used (44) and (118). Note that this gain is related to a ratio of gate aspect ratios.
Since geometric ratios can be controlled precisely in monolithic processes, the gain at hand is
both predictable and reproducible. In effect, the diode-connected load obviates the use of resistive, and therefore noisy, source degeneration as a means of desensitizing the amplifier gain with
respect to processing uncertainties and vagarious transistor model parameters. Indeed, not only
do the amplifier noise characteristics suffer with the use of source degeneration in the amplifier
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
Choma
of Figure (18a), such degeneration in the present case renders the small signal voltage gain somewhat dependent on the forward transconductances of both the driver and the load transistors.
In (95), which stipulates the mean square output noise voltage of the generic common
source configuration shown in Figure (15a), the mean square value, E 2 , of the input signal
sn
noise remains as per (85). Moreover, the mean square value,
E2 ,
g
of the gate noise voltage de-
rives from (46). Accordingly, the mean square value, E 2 , of the output noise voltage generated
on
by the amplifier in Figure (18a) is


2
2
2
2
2 2
2 2
 A E E Z J Z J ,
on
os sn
g
ds ds
ll l
E
2
g
 

2f   
2f 
1 
4kT 
  md  4kT  R 
1  cd    Δf 
1  cl  Δf .


g  
3f   
g 
3f 
 s g md 
ml
 ml  

The mean square value of the equivalent input noise voltage follows as
2
on R 0
E
E
2

n
 gmd
s
g
ml

2

2f 
4kTg 
2f

ml 1  cl  Δf .
 1  cd  Δf 


2
3f
3f
g


md 
md 
4kT
g
(128)
(129)
An inspection of this expression underscores the importance of large driver transconductance to
low noise performance. As expected, a low load transistor transconductance, which serves to increase voltage gain, diminishes the significance of load noise to the equivalent input noise of the
entire amplifier. Moreover, a comparison of (129) with (98) indicates that a low load
transconductance renders the equivalent input noise voltage of the stage in Figure (18a)
comparable to the equivalent input noise for the zero source degeneration resistance form of the
common source amplifier displayed in Figure (15a).
If we apply (128) and (127 to (34), we arrive at the noise factor, Fsd, for the diode load
version of the common source amplifier. Specifically,
2f 
g
2f 
1 
ml  1 
cl .
F  1
1  cd  
(130)



sd



2
g R 
3f  g R 
3 f 
md s
md s
Once again, we see that a large driver transconductance facilitates good noise performance in at
least the sense of minimizing the noise factor.
4.4.
NOISE IN COMMON DRAIN AMPLIFIER
Figure (19a) displays the basic schematic diagram of a common drain amplifier, which
is otherwise known as a source follower. The source follower is traditionally used as a voltage
buffer in electronic systems. This utilization stems from an input resistance, Rind, that approaches infinity at low signal frequencies and an output resistance, Routd, which can be made
small for a large Q-point drain current and/or a large gate aspect ratio in transistor MN. Moreover, the low frequency voltage gain, Avd = Vos /Vs, is positive and smaller than one, but approaches one if the product, gmnron, of forward transconductance and channel resistance substantively exceeds one. This gain declaration facilitates understanding the “source follower”
Electronic Circuit Noise, Part II
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University of Southern California Viterbi School of Engineering
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descriptive, since with a positive voltage gain approaching one, the signal response established at
the source terminal effectively “follows” the signal applied across the gate port of the amplifier.
+Vdd
Rs
MN

Vs
Routd

Rind

Vo
Rl
Vgg

(a).
rgn
egn(t)
[Vgn]
*
esn(t)
[Vsn]
*
Rs

V1

gmnV1
ron
bngmnV2
jdsn(t)
[Idsn]
 V2 
Rind
Routd

Vs
Vos
jln(t)
[Iln]
Rl

(b).
Figure (19). (a). Basic schematic diagram of a common drain amplifier. (b). Small signal model,
inclusive of relevant noise generators, of the source follower in (a). Indicated in
bracketed concert with the noise generators are the surrogate voltage and current
sources used to ascertain the various transfer sensitivities with respect to the noise
generators.
With the help of the small signal model given in Figure (19b), it is easily demonstrated
that the common drain output resistance is
r
1
1
on
R



,
(131)
outd
g
1 1
g r
2 C W L I
mn
bn mn on


n ox

n
n
 dQ
where we have assumed the negligible bulk transconductance inferred by λbn << 1. Moreover,
the low frequency voltage gain, say Avd, can be shown to be
A
vd

g
V
R
r

mn l on
os 
V
1 1
g
R r
s
bn mn l on
Electronic Circuit Noise, Part II



- 44 -


g
R
mn l
1 g
R
,
(132)
mn l
August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
Choma
where we presume ron >> Rl. Clearly, a sufficiently large load resistance termination of the amplifier output port is complementary to a voltage gain of nearly unity.
The gate noise voltage, egn(t), has, in terms of its RMS value, Egn, the familiar mean
square expression,
16kT
2
2
f ,
(133)
e (t)  E
 4kT  r  f 
gn
gn
gn
15g
mn
while the signal source noise, which is herewith attributed to thermal noise in the source resistance, Rs, is
e 2 (t)  E 2  4kTR  f .
sn
sn
(134)
s
The transfer sensitivities, say Agn and Asn, with respect to the gate and signal source
noise voltages, respectively, are identical to the amplifier I/O voltage gain in that the subject two
noise sources are in series with the time deterministic input signal voltage, Vs2. Accordingly,
A
gn

V
os
V
gn
 A
sn

V
os
 A
vd
V
sn
V =V =0
sn s
I
=I =0
dsn ln

g
R
mn l
1 g
V
=V =0
gn s
I
=I =0
dsn ln
R
 1
(135)
mn l
On the other hand, the channel noise current, jdsn(t), whose RMS value is Jdsn, projects a mean
square noise current of
f 
8kTg 
f

mn 1  cn  Δf .
j 2 (t)  J 2  4kT  g  1  cn  Δf 
(136)


dsn
dsn
mn 


f
3
f




Of course, the thermal noise current associated with load resistance Rl abides by
4kT
2
2
(137)
j (t)  J 
Δf .
ln
ln
R
l
Since these two noise current sources are in parallel with one another, their transfer sensitivities,
Zdsn and Zln, respectively, (albeit the magnitudes thereof) are identical and given by
V
V
Z
 os
 Z  os
dsn
ln
I
I
dsn
ln
V =V =V 0
sn s gn
I =0
ln
 R R
l
outd

V =V =V =0
gn s gn
I
=0
dsn
R
1 g
l
R
mn l

(138)
A
vd .
g
mn
Assuming all sources of noise in the small signal amplifier model of Figure (19b) are
uncorrelated, we find that the mean square value of the total output noise voltage is
2
It should be understood that the polarities of the test voltage sources, Vgn and Vsn, as well as the directions of the
test current sources, Idsn and Iln, are inconsequential since these transfer sensitivities are ultimately squared to forge
the expression for the net mean square output noise voltage of the amplifier under consideration.
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering

2

Choma


A 
e 2 (t)  E 2  A2 E 2  E 2   vd  J 2  J 2 ,
(139)
on
on
vd sn
gn
dsn
ln
g 
 mn 
where Eon symbolizes the RMS output noise voltage. Using (133), (134), (136), and (137), we
conclude that


2f 
1 
1 
2
2
2
cl

 A 4kT R 
(140)
e (t)  E
Δf ,
1 
 
on
on
vd
2
 s g 

3f
g
R

mn 

mn l 
where Avd is the I/O voltage gain defined by (132). This expression readily leads to an equivalent input noise voltage possessing the mean square value,
2
on R 0
E
2f 
4kT 
1
1 
(141)
 cl  .
2


g
g
R
3f
A
mn 
mn l

vd
Despite the fact that the equivalent mean square input noise voltage is independent of amplifier
gain, both (140) and (141) convey the importance of large gmn to low noise performance.
Additionally, (141) suggests the prudence of gmnRl >> 1, which unfortunately, is often difficult
to achieve in view of the fact that source followers are commonly dispatched when amplifiers are
called upon to drive small load resistances. Moreover, the forward transconductance, gmn, of
deep submicron MOSFETs is anemic unless inappropriately high quiescent drain currents are allowed and/or excessively large gate aspect ratios are used. Of course, high quiescent current is
hardly apropos for low power applications, while large gate aspect ratios increase device capacitances, which can compromise observable 3-dB bandwidth. For sake of completeness, the noise
factor, say Fsd, of the common drain unit is, by (140),
2
n
e (t)  E
2

n
2
on
s


2f 
1
1 
(142)
 cl  .
sd
2


g
R
g
R
3f
A 4kTR
mn s 
mn l

vd
s
Since the signal source resistance, Rs, of a source follower is generally large, the noise factor in
(142) often tends toward unity at high signal frequencies, especially if gmnRl >> 1. But the large
source resistance that expedites a noise factor tending toward unity is precisely the same reason
that the output noise voltage of a follower can be distressingly large.
F
E

 1
1
In order to promote an I/O voltage gain that closely approaches unity, the passive load
resistance, Rl in the follower of Figure (19a) is often supplanted by an active current sink, which
takes the form of transistor MS in the alternative follower configuration of Figure (20). Because
no source degeneration is employed with MS and both the bulk and source terminals of MS are
grounded, the effective load presented to transistor MN by the current sink is the reasonably large
channel resistance, say ros, of transistor MS. Consequently, the common drain voltage gain in
(132) modifies to the value, Avds, which is
A
vds

g
V
r
r

mn os on
os 
V
1 1
g
r r
s
bn mn os on





g
r
r
mn os on
1 g

r
r

mn os on

,
(143)
which tends toward one since gmn(ros||ron) is likely to be significantly larger than one and assuredly, larger than the original (gmnRl) product.
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
Rs
+Vdd
MN

Vs

Routd
Rind

Choma
ros
Vo
MS
Vgg

Vbias
Figure (20). Alternative schematic diagram of a common drain amplifier that utilizes an active
current sink load, as opposed to the passive resistive load adopted by the follower of
Figure (19a).
The small signal model in Figure (19b) remains applicable to the alternative follower
architecture, subject to the provisos that Rl is supplanted by channel resistance ros and jln(t) is replaced by the Norton equivalent noise current, say jlns(t), of a current sink. Recalling (61), which
pertains to the degenerated current sink in Figure (8a),
 2
f 
2f 


2
2
j (t )  J
 4kT  g r   g  1  cs   Δf  4kTg  1  cs  Δf . (144)
dsn
dsn
ms 
ms 
f  
3f 
 ms g


where we have used (47) and (49). A comparison of this load noise current expression with its
resistive counterpart in (137) suggests that in the foregoing output noise voltage, equivalent input
noise voltage, and noise factor expressions, we need only replace (1/Rl) by gms(1 + 2fcs/3f).
Accordingly, the mean square value of the equivalent input noise voltage for the current sink
load case is, by (141),
2
ons R 0
E
g 
2f  2f 
4kT 
1  ms  1  cs   cl  .
2
g
g 
3f 
3f 
A
mn 
mn

vds
Similarly, (142) for the noise factor revises to
2
ns
e (t)  E
F
sds

2

ns
2
ons
E
2
4kTR
vds
s
A
s
 1


g 
2f  2f 
1  ms  1  cs   cl  .
g R 
g 
3f 
3f 
mn s 
mn

1
(145)
(146)
To the extent that
2f 

g R  1  cs   1 ,
(147)
ms l 

3
f


which is likely, particularly at low signal frequencies, (145) and (146) confirm that the active
current source load version of the source follower is noisier than the resistive load version of the
follower. Moreover, it would appear that the gate aspect ratio of the current sink transistor, MS,
must be kept small to ensure that gms < gmn, thereby minimizing both the equivalent input noise
and noise factor of the actively loaded follower architecture.
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
4.5.
University of Southern California Viterbi School of Engineering
Choma
NOISE IN COMMON GATE AMPLIFIER
The basic schematic diagram of the third canonic cell of analog MOS technology, the
common gate amplifier, appears in Figure (21a). Figure (21b) depicts the corresponding small
signal model. Like the previously considered source follower model, this model accounts for all
relevant noise sources, together with the surrogate noise generators used in the noise sensitivity
study of the amplifier. In the interest of clarity, the mean square value of the gate noise voltage
in the subject model is
+Vdd
Rl
Io
Routg
M
Vbias
Ring
IQ
Rs
Is
(a).
Routg
rgn
egn(t)
[Vgn]
*

V1

gmV1
bgmV2
ro
jdsn(t)
[Idsn]
Ios
Rl
jln(t)
[Iln]
 V2 
Ring
Rs
jsn(t)
[Isn]
Is
(b).
Figure (21). (a). Basic schematic diagram of a common gate amplifier. (b). Small signal model,
inclusive of relevant noise generators, of the amplifier in (a). Indicated in bracketed
concert with the noise generators are the surrogate voltage and current sources used to
ascertain the various transfer sensitivities with respect to the noise generators.
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
e
University of Southern California Viterbi School of Engineering
Choma
16kT
2
2
(t)  E
 4kT  r  f 
f ,
gn
gn
g
15g
m
(148)
while the input signal noise, which presumably arises from thermal noise in source resistance Rs,
projects a mean square current of
4kT  f
2
2
(149)
j (t)  J

.
sn
sn
R
s
As usual, Egn and Jsn in the foregoing two expressions represent RMS noise voltage and RMS
noise current values, respectively. In addition, the mean square value of the noise current associated with the load resistance, Rl, is
4kT  f
2
2
j (t)  J 
,
(150)
ls
ln
R
l
while the channel noise has a mean square current of
 2
f

2
2
j (t )  J
 4kT  g r   g  1  cs
dsn
dsn
m
f
 m g

2f 


  Δf  4kTg m  1  c  Δf .
3f 
 

(151)
The input and output resistances, Ring and Routg, respectively, can be straightforwardly
evaluated through appropriate applications of the mathematical ohmmeter method to the model
in Figure (21b). In particular[7],
ro  Rl
1
1
Ring 


,
(152)
1   1  λb  g m ro
1  λb  gm gm
and
Routg  Rs  1   1  λb  g m Rs  ro   1  λb  1  g m ro  Rs  g m ro Rs .
(153)
Since the common gate input resistance is approximately the inverse of the forward transconductance for the transistor utilized in the amplifier, it is relatively (or at least potentially) small. In
contrast, the driving point output resistance per (153) can be very large, particularly if the applied input signal emulates a high impedance current source. These musings suggest that unlike
the common source and source follower stages, the common gate current gain, say Aig, is generally a more meaningful measure of I/O properties than is voltage gain. To this end, it is easily
shown that[7]
I
I
g R
R
m s 
s
 os  A 
(154)
A  on
,
sn
ig
1
V 0, I 0

I
I
1
g
R
gn
s
R 
sn
s
m s
s g
I 0, I 0
dsn
m
ln
which is essentially a current divider between the Norton representation of the applied signal
source and the input port of the common gate amplifier. We note that the current gain is a positive number that is smaller than one, much like the voltage gain of a source follower is a positive,
less than unity number. But if the input signal is a current, source resistance Rs can be expected
to be large, which foretells a common gate current gain that closely approaches one. This
observation is sensible in that the gate of the common gate transistor draws neither quiescent current nor signal current.
The output noise current sensitivities to each of the four respective noise generators in
the subject model derives from straightforward circuit analyses. In particular,
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511

sn
A
I
University of Southern California Viterbi School of Engineering
on
I
V
sn
I
gn
g R
os  A 
m s ,
ig
I
1 g R
s
m s

0, I 0
dsn
I
Choma
s
0, I 0
(155)
ln
where Ion identifies the RMS value of the total output noise current conducted by the terminating
load resistance, Rl. The transfer sensitivity to the noise current, Isn, is identical to the current
transfer function, Aig, of the common gate stage because the source noise current generator, jsn(t),
is directly in shunt with the signal current generator, Is. As is the norm for noise sensitivity studies, the polarities of all surrogate noise sources, inclusive of Isn, are inconsequential if all
observable noise sources are uncorrelated.
Since the load noise current, jln(t), shunts the channel noise generator, jdsn(t), the transfer sensitivities, say Aln and Adsn, of output noise current to each of these noise sources are the
same. Thus,
R
I
I
outg
on
A  on
 A


 1 , (156)
ln
dsn
V 0, I 0
V 0, I 0
I
I
R
R

gn
s
gn
s
ln
I
dsn
0, I
sn
dsn
0
I 0, I
ln
sn
0
outg
l
where we have presumed that the common gate output resistance, Routg, is invariably much larger
than the resistance, Rl, of a reasonable load termination. Finally, the transfer sensitivity, Agn, to
the gate noise is
I
 on
gn
V
gn
A
I 0, I 0
sn
s
I
0, I 0
dsn

g r
mo
R
outg

R
l
1
,
R
(157)
s
ln
where we have exploited (153) subsequent to once again invoking the assumption, Routg >> Rl.
The immediate ramification of the foregoing transfer sensitivity stipulations is that the
mean square value of the net output noise current is, with all noise sources presumed uncorrelated,
2
on
i (t)  I


2
2 2
2
2
2
2 2
 A J  A J J
 A E .
on
ig sn
ln ln
dsn
gn gn
Recalling (148) through (151),
 A2

2f  

1
4
ig
2

c
I
 4kT 


 g 1 
   f
on
m
2
R
R
3f
15g R


l
 s
m s

(158)
(159)
 1 

2f  

4
1

 4kT   1 
 g  1  c   f .
m
3f  
 Rs  15g m Rs  Rl



where the indicated approximation invokes the simplifying assumption of unity current gain,
which is reasonable when the common gate cell is driven by a signal current (as opposed to a signal voltage). It follows that the noise factor, Fg, of the common gate amplifier is
F
g

I2
on


A2 4kT 1 R  f
ig
Electronic Circuit Noise, Part II
s
 1
R
2f 

4
 s  g R 1  c  .
m s
15g R
R
3f 

m s
- 50 -
(160)
l
August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
Choma
An inspection of (160) confirms a common gate noise factor that approaches infinity
for a signal source resistance, Rs, of zero or infinity. Accordingly, for a fixed signal frequency or
for higher frequencies that appreciably exceed the corner frequency, fc, there exists a physically
realizable optimal source resistance, say Rsopt, for which the common gate noise figure is minimized. This optimal source resistance is easily found by setting to zero the partial derivative of
Fg in (160) to zero, with the result that
2R
g R
l
m l
R

 2R
,
(161)
ing
sopt f  2 f / 3
15
1

g
R
15g
R
1

g
R
c
m l

m l


m l

where have exploited the approximate form of (152). The corresponding minimal noise factor,
say Fgmin, follows as


g R
1
 1  g m Rl

m l
 1  2


F
 . (162)
gmin f  2 f / 3
15g R

15
1
g
R

15g
R
1
g
R

m l
c
m l 
m l
m l

As we might have expected in light of our previous discovery that large forward transconductance in amplifiers generally results in laudable noise performance, the minimum noise figure is
disconcertingly large for very small gm and specifically, for small gmRl. But for very large gmRl,
the subject noise factor converges to the acceptably small result of
1
F
 1 4
 2.03 .
(163)
gmin f  2 f c / 3
15




g R 1
m l
Noise Factor & Resistance
3
2.5
Noise Factor
2
1.5
1
Optimum Source Resistance
0.5
0
0
5
10
15
20
25
gmRl
Figure (22). Normalized plot, as a function of gmRl, of the optimum source resistance and corresponding minimal noise factor in a common gate amplifier.
Unfortunately, the impressive noise factor witnessed in (163), which indeed corresponds to large
gmRl, begets, from (161) a corresponding optimum source resistance that is usually smaller than
the Thévenin or characteristic impedance of the signal source. This fact is graphically portrayed
in Figure (22), which plots the optimum source resistance, normalized to the input resistance,
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
University of Southern California Viterbi School of Engineering
Choma
Ring, of the common gate amplifier, as a function of the dimensionless product, gmRl. Also plotted in this figure is the minimal noise factor corresponding to the optimized source resistance of
(161). Note in Figure (22) that for most practical values of gmRl, the optimum source resistance
is at least a factor of two smaller than the input resistance. This observation confirms suspicions
to the effect that an optimization of noise performance does not generally synergize with circuit
optimization in the sense of achieving maximum signal power transfer from the applied signal
source to the amplifier input port.
Figure (23) displays the two-port equivalent noise representation for the input port of
the subject common gate amplifier. An inspection of this diagram shows that with the source
noise generator, jsn(t), set to zero, the equivalent input noise current, jn(t), flows into the input
port of the amplifier if source resistance Rs is infinitely large. If the RMS value of jn(t) is designated as In, the mean square value of jn(t) derives from (159) and (155) as
+Vdd
Rl
jon(t)
Routg
M
Vbias
en (t)
*
Ring
jsn(t)
Rs
eni (t)
jn (t)
Figure (23). The input port noise model of the common gate amplifier.
It is presumed that the transistor, together with its load
termination is noiseless in that all intrinsic noise is referred
to an equivalent input noise voltage, en(t), and an equivalent
input noise current, jn(t), at the input port. Current jon(t) abstracts the net output noise current conducted by the load/
1
I2
2f  

2
2
j (t)  I  on
 4kT   g  1  c    f .
n
n
m
3f  
 Rl
A2


ig R 
(164)
s
The result at hand shows that noise associated with the load resistance refers directly to the input
port as a component of the equivalent input noise current. Moreover, the output noise current
ramifications of gate noise, in addition to flicker phenomena, similarly translate in approximately
a 1:1 fashion to the equivalent input noise current. Because the input resistance of the amplifier
is generally very small, the equivalent input noise voltage usually bears no particular significance
herewith.
Electronic Circuit Noise, Part II
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August 2011
Technical Report #03-0511
5.0.
University of Southern California Viterbi School of Engineering
Choma
REFERENCES
[1]. J. Choma, “Electronic Noise Characterization − Part I: System Concepts and Theory,” University of Southern California Tech. Rep. #USC 02-511, July 2011, available at
http://www.jcatsc.com/.
[2] W-K. Chen, Passive and Active Filters: Theory and Implementations. New York: John Wiley
and Sons, 1986, pp. 51-58.
[3]. J. Choma, “The Metal-Oxide-Silicon Field Effect Transistor,” University of Southern California, EE 536a Course Notes #01, 2010-2011, available at http://www.jcatsc.com/.
[4]. J. Choma, “Circuit Level Models and Basic Applications of MOS Technology Transistors,”
University of Southern California, EE 536a Lecture Aid #1, 2010-2011, available at
http://www.jcatsc.com/.
[5]. W. Liu, MOSFET Models for SPICE Simulation, Including BSIM3v3 and BSIM4. New York:
Wiley Interscience, 2001, pp. 247-252 and p. 256.
[6]. H. Schichman and D. Hodges, “Modeling and Simulation of Insulated-Gate Field-Effect
Transistor Switching Circuits,” IEEE J. of Solid State Circuits, vol. SC-3, pp. 285-289, 1968.
[7]. J. Choma, “Basic Circuit Cells of Analog MOSFET Technology,” University of Southern
California, EE 348 Lecture Supplement #6, 2010-2011, available at http://www.jcatsc.com/.
Electronic Circuit Noise, Part II
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August 2011