Symmetrical Hybrid Multilevel Dc-Ac Converters
Using the PD-CSV Modulation
G. Carmona, R. Ramos, D. Ruiz-Caballero*, S.A. Mussa** , T. Meynard ***
*P.
Universidad Católica de Valparaíso
School of Elec.Engineering – EIE
Power Electronic Laboratory – LEP
Av. Brasil 2147, P.O. BOX 4059,
Valparaíso, CHILE.
domingo.ruiz@ucv.cl
**Federal
University of Santa Catarina
Department of Electrical Engineering
Power Electronics Institute – INEP
P. O. BOX 5119 – 88040-970
Florianópolis – SC – BRAZIL
E-mail: samir@inep.ufsc.br
Abstract – In this paper will be studied the Phase Disposition
(PD) modulation with application of the modulation known as
Centered Space Vector (CSV PWM) to the hybrid multilevel
symmetrical inverter [4]. Using the generated distortion rate
obtained, a comparison with the PSD modulation originally
applied is made. The article included the results of an
experimental low-power prototype with its fast switches
operating at 1.6 kHz and the slow switches operating at 50 Hz.
The control circuit is implemented with DSP.
I.
INTRODUCTION
In the eighties Nabae and others [5], the interest in
converting high quantities of energy using multilevel
inverters raised as the NPC (Neutral Point Clamped) topology
were introduced. These converters are appropriate in high
voltage and high power applications, because of its capacity
of synthesize waveforms with lower harmonic distortion and
achieve high voltages using devices with a lower voltage [5].
The NPC topology can be applied to obtain a great number of
levels in the output. As this number increase, the output
waveform is composed of more steps, and approaches even
more of a sinusoid. Theoretically is possible to obtain a signal
with zero harmonic distortion, using an infinite number of
levels. Unfortunately, the output level number is limited due
to different restrictions as the voltage unbalance at the output
capacitors, circuit layout and restrictions on packaging.
In the last years, lots of topologies have been
introduced and studied [3-7], as the Flying Capacitor, the
cascade inverters with separated CC sources and, inside this
last, the Asymmetrical Multilevel Hybrid Inverter. Recently,
another topology has been introduced, named Symmetrical
Multilevel Hybrid Inverter, shown in Fig. 1 in its one-phase
form [4]. This circuit is modulated by Phase Shifting
Disposition (PSD), obtaining a low harmonic distortion. Also,
it has shown a good alternative to the conventional Hybrid
converter developed by Manjrekar and Lipo [9]. In this work,
it will be applied the Phase Disposition modulation (PD) with
application of the modulation known as Centered Space
Vector (CSV PWM), obtaining the generated distortion rates
to compare with the PSD modulation originally applied.
***LAPLACE,
UMR CNRS N°5213
2 Rue Camichel – BP7122
31071 Toulouse – FRANCE
meynard@laplace.univ-tlse.fr
II. SYMMETRICAL HYBRID MULTILEVEL INVERTER
The symmetrical hybrid multilevel inverter, shown in
Fig. 1, acts as an one-phase inverter with five output voltage
levels. The three-level cell (CT) switches can operate in a
maximum voltage value of ‘E’, and, with an adequate
modulation technique, they operate in high frequency (few
kHz). In the other way, the switches (S5, S6, S7 e S8), which
compose the H-bridge, must support a maximum voltage
level of ‘2E’. These switches operate at low frequency with
zero-voltage turn-on and turn-off. You could say the
proposed inverter can also be classified within the group of
multilevel hybrids inverter.
As shown in [7], the cascaded conventional symmetrical
multilevel inverters based in H-bridge have an output voltage
number given by 2N+1. To the studied case, the output levels
are obtained following the same law. Then, there are 2N+1
levels in the load, where N is the number of CC sources.
D S1
S1
x
E
S7
DS7
S8
DS8
S2
DS2
S3
D S3
E
S5
DS5
S6
D S6
y
DS4
S4
Load
b
a
(a)
vab(t)
2E
S1,S4
E
S2 S1 S2
S3 S3 S4
0
S2
S4
S5-S8 ON
S6-S7 OFF
S5-S8 OFF
S6-S7 ON
S1
S3
S2
S4
S2 S1 S2
S3 S3 S4
S1
S3
t
-E
S1,S4
-2E
(b)
Fig. 1. (a) One-phase symmetrical hybrid multilevel inverter. (b) Output
voltage waveform.
Patent Pending
If three inverters output were connected in wye, feeding
a three-phase load connected in wye, the result is a threephase symmetrical hybrid multilevel inverter, as shown in
Fig. 2. Also, is it possible to arrange a version as a delta-delta
connection or as delta-wye connection.
Lo
: Load’s equivalent inductance
fs
: Switching frequency
O
S1a
E
DS1a
S1b
S7a
DS7a
S2a
DS2a
S5a
DS5a
S8a
DS8a S3a
DS3a S
6a
DS6a
E
E
DS1b
S1c
S7b
DS7b
S2b
DS2b
S5b
DS5b
S8b
DS8b S3b
DS3b S6b
DS6b
E
E
S4a
DS4a
DS1c
S7c
DS7c
S2c
DS2c
S5c
DS5c
S8c
DS8c S3c
DS3c S6c
DS6c
(a)
E
S4b
DS4b
S4c
DS4c
Inverter leg
U
V
W
N
Fig. 2. Three-phase proposed circuit.
III. APPLIED MODULATIONS
A. Phase Shifting (PSD) Modulation Strategy
The modulation strategy to drive the fast switches is
based in the PWM sinusoidal modulation known as Phase
Shifted Disposition (PSD). In this modulation, the output
signal is obtained from the comparison between a rectified
sinusoid and the carrier waveform, which has two triangular
signals, with 180 degrees of phase difference, as shown in
Fig. 3(b).
The modulator circuit is composed by three reference
signals, sinusoidal signals rectified and with 120 degrees of
phase difference, which are compared to the two triangular
carriers. The common point between the inverters will be
named as ‘o’, and the common point in the load wye
connection as ‘n’. Each connection point between the onephase inverters and the load will be named as ‘u’, ‘v’ and ‘w’.
With this modulation scheme, the command signals
generated to the switches are shown in Fig. 4.
(b)
Fig. 3. (a) Command circuit to the switches (b) Modulator and carrier
signals.
Fig. 4. Command signals to the switches.
In the circuit simulation all components are considered
ideal. Figure 5 shows the waveforms of the phase voltage,
line-to-line voltage (bottom), and phase current (top) in
steady-state. It can be seen that the number of levels in lineto-line voltage is nine, but their utilization is not optimal
since there are many switching periods where three different
levels are used. In this case, the current ripple is clearly
visible.
A.1 Simulations of the Symmetrical Hybrid Multilevel
Inverter using PSD
In this section are shown the results obtained from digital
simulation of the circuit in Fig. 4, using the PSD modulation,
with the following specifications: 2E 3kV ,
f 0 50 Hz .
P
KW
120
,
,
L
=51mH
,
(
,
1
o
f s 1600 Hz ),
mi 0.94
Ro 21.33
m f 32
cos( )
0.8 .
Where:
Po
: Output power
f0
: Fundamental frequency at the load
Vf1
: Fundamental RMS voltage
cos( )
mi
: Load’s power factor
: Modulation index
mf
: Frequency index
Ro
: Load’s equivalent resistance
Patent Pending
Fig. 5. PSD sinus modulation waveforms: (top) Phase current, (bottom)
phase voltage and line-line voltage
Figure 6 shows the frequency spectrum of these
voltages. The high frequency components appear in wide
groups centered around multiples of 3.2kHz which is twice
the switching frequency; the fact that it is the double of the
switching frequency is due to the interleaved control of the
two cells of a same leg. It can also be observed that the shape
of the spectrum of the line-line voltage of the three-phase
inverter is not very different from that of the phase voltage.
Fig. 7. Implemented model in Simulink to the simulations.
B1. Implemented Models to the digital simulation
Fig. 6. (top) Frequency spectrum of the phase voltage of the inverter vun(t).
(bottom) Frequency spectrum of the line-line voltage of the three-phase
inverter vuv(t).
The utilized model of the inverter was developed in
reference [4]. The circuit implemented can be seen in Fig. 7.
The final reference signals defined by Equations (1), (2)
and (3), are constructed using the blocks represented in
Figures 8, 9 and 10.
B. Centered Space Vector (CSV-PWM) Modulation Strategy
Refa
Product
1
Refa
Va'
Vref_a
Add14
The centered space vector PWM derives from the study
realized in [1]-[2], and consists in having N-1 carrier signals
with same amplitude, phase and frequency, where N
represents the level number of the inverter.
The reference signals are superposed over the carrier
signals, and the intersection point of both signals determines
the switches’ voltage level in the output, to each transition
cycle or operating state.
The Phase Disposition modulation can be extended to
CSVPWM, initially adding an offset that contains the all zero
sequence components to voltages references, Vk (k a, b, c)
then:
[max(Va , V , Vc ) min(Va ,V , Vc )]
b
b
V k
2
V'
k
Refb
Refb
Vb'
Product 1
Refc
Refc
Product 2
Vc '
Voff
Subsistema
Vk'
Out 2
[V '
k
( N 1)VDC / 2] mod VDC
Vc '
offset 3
Fig. 8. System to generate the reference signals, in phases A, B and C.
1
Refa
Add 4
2
Refb
VREF _ K
2
[max(Va'' , V '' ,Vc'' ) min(Va'' ,V '' ,Vc'' )]
b
b
2
Add 5
3
Refc
4
Voff
3
Vc'
Add 2
Add 6
max
MinMax 1
-K -
min
Gain
MinMax
Fig. 9. Model to generate the signal with zero sequence component.
1
Va'
mod
(3)
V'a''
Add7
max
Mod 1
2
Vb '
MinMax 3
mod
Vb''
-K-
Add8
Mod 2
3
Vc'
Add9
Mod 3
1
offset 1
Add10
Vc ''
Gain 1
min
1/4
MinMax 2
0.5
offset
Fig. 10. Model to obtain the output offset.
Patent Pending
2
Vb '
Add 1
mod
VDC
1
Va'
Add
(2)
The presented equation is used because in multilevel
inverters, it is necessary to identify which reference signal is
responsible for the beginning of the vector sequence that is
present in each semi-cycle of the carrier signal.
The absolute value of the offset guarantees that half of
the spatial vectors remain centered during the operating
period of the switch. Finally, the reference signal that
incorporates the offset optimizing the spectrum in certain
regions [2] is defined by:
V'
k
Voff ''
Vb'
Voff
Add 3
V ''
k
3
Vref_c
Add16
Va'
(1)
A modulus function that identifies which of the reference
signals is the responsible for the first and last transition of the
switch in each interval; hence the voltages references are
given by:
2
Vref_b
Add15
offset 2
Add17
1
Voff''
In Figure 11, the reference signals are shown over the
complete modulation depth range. In particular, the regions
where a DC offset is added are clearly visible.
For carrier generation, the system in Fig. 12 can be
implemented, which consists of four triangular signals that
have the same disposition of phase, frequency and amplitude,
as explained before. The multilevel waveform in each phase
is then generated by comparing the reference to each carrier
and summing the four 2-level results to obtain a five-level
signal.
As explained in [8], this 5-level signal can be used as an
input for a state machine (Fig. 13). It should be noted that
this part of the controller is the only one that is specific to the
Hybrid Multilevel Inverter. The only input of this state
machine is the multilevel waveform, and all the transitions in
it are defined by the comparison of the input signal with
thresholds 0.5, 1.5, 2.5, 3.5 and 4.5.
As can be seen from Fig. 14, accounting for the basic rules of
power electronics and commutation cells, only 3 logic inputs
can be used to control this converter. These three binary
signals form a vector that can take 8 different values, but 12
states are required for the state machine which indirectly
corresponds with the memory of former states.
Fig. 13. State machine used to generate the control signals.
Fig. 14. The three effective control signals of the Hybrid MultiLevel
Converter.
Fig. 11. Sinusoidal references Va,Vb,Vc and derived references VREF_a,
VREF_b, VREF_c for PDCSV (Modulation depth ramping from 0 to 1.15).
1
In 1
>
double
triangular 1
0.5
Constant 2
>
+
+
double
Triangular 2
<
+
+
double
Triangular 3
.5
Constant 1
<
double
Triangular 4
1
Constant 3
<=
0
double
gate S
Constant
Fig. 12. System used to generate the multilevel waveform in each phase.
Patent Pending
B.2 Digital Simulation with CSVPWM Modulation applied to
the Symmetrical Hybrid Multilevel Inverter
The design specifications are the same as those of the
PSD modulation. The results of the digital simulation of the
circuit in Fig. 7 are presented, with the project data specified
to PSD modulation. Ideal components were considered.
Figure 15 shows the load current (top), line-to-line
voltage obtained in the inverter’s output, and the phase
voltage (bottom) in the load. Compared with Fig. 5, the load
current ripple has been greatly reduced. It can also be
observed that the line and phase voltages are respectively five
and nine level waveforms, like in figure 5, but the levels are
now better used; only two adjacent levels are used over each
switching period, and this statement applies to the phase
voltage as well as to line-line voltage.
Figure 16 shows the four carrier signals and the phase
voltage reference. In this simulation, natural sampling is used
but it is clear that the experimental setup will use sampling
synchronized with carrier peaks (either at the carrier
frequency or at double the carrier frequency) to avoid extra
commutations, and short pulses.
IV. EXPERIMENTAL RESULTS
Fig. 15. (top) Load current, (bottom) phase voltage and line-line voltage.
Fig. 16. Reference and carriers with PD-CSV PWM technique.
To validate the proposed topology, an experimental
prototype of the three-phase symmetrical hybrid multilevel
inverter, is being built. Figure 18 shows the prototype of the
inverter, built and tested in the laboratory. The modulation
strategy that goes with the switches is based on the Phase
Disposition Centered Space Vector (PD-CSV) PWM
technique and PSD, which has been implemented employing
a DSP. The DSP TMS320F2812 was used to generate the
signals required for the control of the inverter. In Fig. 19 the
block diagram of the DSP implementation modulation
software.
In Fig. 20 and 21, are shows de experimental results of
the switched voltages and frequency spectrum of both
modulations strategy.
Fig. 18. Photograph of the implemented three-phase prototype.
Figure 17 shows the frequency spectrum of the phase
voltage and line-to-line voltage. Unlike Figure 6, there is only
one harmonic in the phase voltage spectrum around 3.2 kHz
and its amplitude is very high. This harmonic is generated by
the switching, and because the carriers are all in phase, its
amplitude is maximized and its phase is directly imposed by
the carriers. The same carriers being used for the three phases
of the converter, this component is present on all phases and
cancels in the line-line voltage, which can be seen in the same
figure.
Comparing these two modulation strategies, it can be
seen in the time domain as well as in the frequency domain
that PDCSV gives better results than Sinus PSD.
Fig. 17. Frequency spectrum of the phase (top) and line-to-line (bottom)
voltage of the three-phase inverter, in percentage of the fundamental.
Fig. 19. Block diagram of the DSP software implementation.
Patent Pending
V. CONCLUSIONS
50
Amplitude(V)
40
30
20
10
0
0
1000
2000
3000
4000
5000
6000
Frequency (Hz)
7000
8000
9000
10000
1000
2000
3000
4000
5000
6000
Frequency (Hz)
7000
8000
9000
10000
50
Amplitude(V)
40
30
20
10
0
0
Fig. 20. Experimental switched phase and line-line voltages (top) and
frequency spectrum of the phase and line-to-line (bottom) using PSD
modulation.
This article presented the single-phase and three-phase
symmetrical hybrid multilevel inverter circuit and the
associated modulation technique. Both single and three-phase
circuits are characterized by operating with fast switches in
the inverter cell and with slow switches in full-bridge
configuration, to transfer the energy to the load
It has been shown how standard multilevel control
strategies can be applied to this converter, and in particular, it
has been shown how a state machine can help applying threephase operation to the symmetrical hybrid multilevel inverter.
With this approach it is very easy to switch from one strategy
to the other, and for example comparing sinus PSD and PDCSV becomes simpler. Studying other variants or the
influence of a single characteristic of the control is possible.
For example, the influence of zero sequence components
injection only, PD only, or DC offset only is possible and this
allows a better understanding of the different characteristics
of this optimized control.
The main disadvantage is that with modulation PD-CSV,
regarding to PSD, the natural balance voltages in the
capacitors is lost. So with these modulation techniques
become necessary controls to maintain balanced these
voltages.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
50
Amplitude(V
40
30
[7]
20
10
0
[8]
0
1000
2000
3000
4000
5000
6000
Frequency (Hz)
7000
8000
9000
10000
50
Amplitude(V)
40
[9]
30
20
10
0
0
1000
2000
3000
4000
5000
6000
Frequency (Hz)
7000
8000
9000
10000
Fig. 21. Experimental switched phase and line-line voltages (top) and
frequency spectrum of the phase and line-to-line (bottom) using PD-CSV
modulation.
Patent Pending
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