Application Note for
Surface Mount Assembly of Amkor’s
Eutectic and Lead-Free CSPnl™
Wafer Level Chip Scale Packages
Contents
1.0
INTRODUCTION………………………………………………………………………………………… 2
2.0
PRINTED CIRCUIT BOARD…………………………………………………………………………..
2.1
Land Pattern Recommendations…………………………………………………………..
2.2
Board Material………………………………………………………………………………..
2.3
Board Thickness……………………………………………………………………………..
2.4
Conductor Finish……………………………………………………………………………..
2.5
Solder Mask…………………………………………………………………………………..
2.6
Quality Control………………………………………………………………………………..
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2
3
3
4
4
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3.0
SURFACE MOUNT ASSEMBLY……………………………………………………………………..
3.1
Stencil Design…………………………………………………………………………………
3.2
Solder Paste…………………………………………………………………………………..
3.3
Package Placement………………………………………………………………………….
3.4
Reflow………………………………………………………………………………………….
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4
4
5
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4.0
REWORK………………………………………………………………………………………………..
4.1
Component Removal Guidelines…………………………………………………………..
4.2
Site Redressing………………………………………………………………………………
4.3
Component Replacement…………………………………………………………………..
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1.0 INTRODUCTION
Amkor's wafer level packaging service meets the industry's growing demand for full turnkey assembly and
test solutions for CSP (Chip Scale Package) products. Through the acquisition of Unitive, Amkor has
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adopted the CSP ™ as its standard wafer level package offering. CSP ™ represents the next level in
wafer level chip scale packaging (WLCSP) as demonstrated by its proven benchmark reliability. The
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CSP ™ has been widely adopted as the industry standard for cost effective, reliable, high performance
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wafer level CSP applications. CSP ™ is ideal for portable communications and related applications that
require a low cost packaging solution with small form factor and improved signal propagation
characteristics. EEPROM, flash, DRAM, integrated passive networks, and standard analog devices are
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all technologies that benefit from the CSP ™ package attributes. End products include mobile phones,
PDAs, laptop PCs, disk drives, digital cameras, MP3 players, GPS navigation devices, and other portable
products.
One of the key failure mechanisms impacting the reliability performance of any WLCSP package is solder
fatigue, which is affected by many variables, such as the board design, including the composition
(number of copper layers), thickness, composite coefficient of thermal expansion; the size of the pad on
the board compared to the wetted area on die; the solder composition and material properties, such as
elastic modulus, plasticity, CTE, creep; the temperature range and the dwell at temperature extremes;
and finally, the ball size and the distance from the center of the array to the furthermost ball. Thus, it is
critical to use the optimum parameters for board design and assembly to achieve the desired reliability
performance. In this application note, the recommended board design, component assembly and rework
guidelines are discussed.
2.0 PRINTED CIRCUIT BOARD
2.1 Land Pattern Recommendations
For printed circuit board (PCB) fabrication, two types of pads/land patterns are used for
surface-mount assembly (Figure 1):
1. Non-Solder Mask Defined (NSMD)—The metal pad on the PCB (to which a package
I/O will be attached) is smaller than the solder mask opening.
2. Solder Mask Defined (SMD)—The solder mask opening is smaller than the metal pad.
Figure 1. NSMD and SMD Land Patterns
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For the CSP ™ package, the NSMD pads/land patterns are recommended. The NSMD
configuration provides a more robust solder joint than their SMD equivalents because the
edge of the solder mask could be a stress initiator at the base of the solder ball, which can
result in solder joints cracking. Also, for the NSMD configuration, the solder wets the sides of
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the copper pads, improving the strength of the solder joint between the CSP ™ package and
the PCB. This can be seen through improved die shear and tensile pull strength values and
thermal cycling reliability (compared to SMD). NSMD requires the solder-wetted area to be
determined by the defined copper area, not by the solder mask. This is an advantage
because of the tighter control on copper etch process than the solder mask develop operation.
Further, the smaller pad size in the NSMD definition also provides for more room for tight
pitch routing on the PCB.
When designing the board, the solder mask registration capability of the board manufacturer
should be checked to ensure that the correct solder mask opening dimension is 50 m either
side of the copper pad. The actual size of the used copper pad should be between 80% and
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100% of the diameter of the CSP ™ solder ball. The design guidelines for the NSMD land
pattern are shown below in Figure 2. To achieve higher standoff, the copper layer thickness
should be 1 oz. (30 m) or less. A copper layer greater than 1 oz. (30 m) will result in
lowering of the effective stand-off, which may compromise solder joint reliability. Copper pads
should be finished with Organic Solderability Preservative coating (OSP). Further, the soldermask thickness should be less than 1 mil (.001in). The trace routing away from WLCSP
device should be balanced in x and y directions to avoid unintentional component movement
as a result of unbalanced solder wetting forces. Circuit traces routed away from PCB land
pads should be less than 100µm wide in the exposed area inside the solder mask opening.
Wider trace widths will reduce device stand-off and impact reliability.
Pitch
Nominal Sphere Diameter (µ
µm)
UBM Diameter (µ
µm)
Bump Height (µ
µm)
Bump Diameter (µ
µm)
PCB Design Parameters
Solder Pad Width (µ
µm)
Solder Mask Opening (µ
µm)
Solder Mask Thickness (µ
µm)
Copper Trace Thickness(µ
µm)
Copper Trace Width (µ
µm)
0.4 mm
0.5 mm 0.65 mm
250
205
210
260
300
250
250
310
350
250
305
360
225
325
25
30
100
275
375
25
30
100
275
375
25
30
100
Figure 2. Design Guidelines for the NSMD Land Pattern
2.2 Board Material
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Standard epoxy glass substrates are compatible with the CSP ™ assembly. The high
temperature FR4 material is preferred over the standard FR4 material, for improved package
reliability. This is because the coefficient of thermal expansion (CTE) of the high temperature
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FR4 substrate (12-16 ppm/ C) is lower than that of the standard FR4 substrate (14-18
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ppm/ C) and is thus closer to that of silicon (~ 3 ppm/ C). The actual CTE value of a board is
design dependent. Numerous factors such as number of metal layers of the PCB, the trace
density, laminate material, population density, and the operating environment affect the
thermal expansion. For best reliability results, the PCB laminate glass transition temperature
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should be above the operating range of the intended application (Tg > 170 C recommended).
2.3 Board Thickness
Board thickness values currently used in the industry range from 0.016” to 0.093” (0.4 mm to
2.3 mm). Thinner boards are more flexible, resulting in greater reliability during thermal
cycling and improved thermal fatigue life in comparison to thicker boards. Similarly, thinner
packages also contribute to improved package thermal fatigue performance at the board level.
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2.4 Conductor Finish
The recommended technique to protect the copper from oxidation is to use a suitable OSP
finish, especially for lead-free bumps. In Amkor's board designs, the OSP material used is
ENTEK®-PLUS Cu 106A, a product of Enthone-OMI, Inc., which is a simple spin-on material.
OSP is preferred for HASL (Hot Air Solder Level) for maintaining CSP flatness and control of
paste printing process. The ENTEK®-PLUS Cu 106A requires a maximum reflow
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temperature to be lower than 225 C in an air environment. If a nitrogen environment (<500
ppm O2) is used in the reflow oven, then adherence to this temperature specification is not
crucial.
2.5 Solder Mask
A properly-defined solder mask opening helps to control the actual wettable area of the Cu
conductor. Typical solder mask materials used for printed circuit boards are Probimer 5 or
Taiyo PSR 4000. However, with the use of non-solder mask defined (NSMD or etch-defined)
pads, the choice of solder mask material is less significant. It is imperative to prevent the
solder mask from overlapping the copper pad. To ensure a well defined wettable area, a
solder mask diameter should be at least 4 mils larger than the Cu pad. Further, solder-mask
thickness should be less than 1 mil (.001in) on top of the copper circuit pattern.
2.6 Quality Control
PCB boards should meet the solderability requirements in ANSI/J-STD-003. Warping
tolerance should be indicated in the board fabrication specifications.
Pre-assembly
inspection is recommended. Inspect for Cu pad cleanliness, absence of residual solder mask
on CSP pads, and adequate clearance between solder mask and Cu pads.
3.0 SURFACE MOUNT ASSEMBLY
3.1 Stencil Design
The stencil design should follow standard industry recommendations such as the IPC-7525
Stencil Design Guidelines. The best solder stencil performance is achieved using laser cut
stencils with electro-polishing. The use of chemically etched stencils results in inferior solder
paste volume control. The solder stencil opening should be identical for all solder pads in the
WLCSP array. Square-shaped apertures are preferred over round apertures for better solder
release, especially in thicker stencils. The corners of the square apertures may be rounded to
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minimize clogging. The apertures should be given a positive taper of about 5 with the
bottom opening larger than the top to improve solder release. A 1:1 aperture to solder pad
ratio is recommended. Suggested stencil design guidelines are shown below in Table 1.
Pitch
Nominal Sphere Diameter (µ
µm)
Solder Pad Width (µ
µm)
Stencil Opening (µ
µm)
Stencil Thickness (µ
µm)
0.4 mm
250
225
225x225
100-125
0.5 mm
300
275
275x275
100-125
0.65 mm
350
275
275x275
125-150
Table 1. Design Guidelines for the Solder Paste Stencil
3.2 Solder Paste
The best board level reliability performance is achieved when maximum device standoff
exists, which is obtained with maximum manufacturable solder paste volume. The solder
paste volume is the best predictor of the finished board quality, and a thorough inspection for
solder volume uniformity is highly recommended. A no-clean solder paste with a maximum
particle size of 40 m or finer paste (Type 3) is recommended. Because of potential corrosion
issues, it is not advisable to use solder paste with active flux.
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3.3 Package Placement
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Typical surface mount placement equipment can assemble the CSP ™ packages. The
package provides robust self-alignment, and will re-center with up to 150µm of displacement.
Additional recommendations concerning placement force for best success with component
placement processes are:
• On equipment without component force adjustments, the Z placement height should
be set to avoid overdriving the board location. Optimally, the Z height should be set at
one-half the printed solder paste height.
• On equipment with component placement force adjustments, the maximum
recommended placement force is 35g/bump. Exceeding this force level can reduce
reliability due to excessive silicon impact stress and subsequent damage.
3.4 Reflow
A typical temperature/time profile for the eutectic solder and the corresponding critical reflow
parameters are shown in Figure 3. A maximum reflow temperature of between 235ºC to
240ºC on the surface of the device is recommended with a nitrogen purge. Also, the oxygen
content of the furnace must be monitored and kept below 100 ppm. Actual reflow
temperatures need to be determined by the end user based on thermal loading effect
measurements within the furnace.
Process Step
Ramp Rate
Pre-Heat
Time above Liquidus, 183°C
Peak Temperature
Time within 5°C of Peak Temperature
Ramp Down Rate
Eutectic Solder
3°C/sec Maximum
165°C, 60 to 120 seconds
30 to 90 seconds
235°C
10 to 20 seconds
6°C/sec Maximum
Figure 3. Reflow Profile and Critical Parameters for Eutectic (63/37 Sn/Pb) Solder
For the lead-free (SnAgCu) solder, the reflow profile is a critical consideration. The SnAgCu
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solder alloy melts at ~ 217 C, and the reflow temperature peak at joint level should be 15 to
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20 C higher than melting temperature. Higher reflow temperatures can cause package
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delamination if the package is not qualified for higher temperature. Most of Amkor’s CSP ™
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packages are qualified at 260 C reflow with moisture sensitivity level varying between Level 1
and Level 3.
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A typical temperature/time profile for the lead-free (SnAgCu) solder and the corresponding
critical reflow parameters are shown in Figure 4. The actual profile depends on many factors
such as the complexity of products and components, oven type, solder type, temperature
difference across the board, oven tolerance and the thermocouple tolerance.
Process Step
Ramp Rate
Pre-Heat
Time above Liquidus, 220°C
Peak Temperature
Time within 5°C of Peak Temperature
Ramp Down Rate
Lead-Free Solder
3°C/sec
150°C to 180°C, 60 to 180 seconds
30 to 90 seconds
255°C ±5°C
10 to 20 seconds
6°C/sec Maximum
Figure 4. Reflow Profile and Critical Parameters for Lead-free (SnAgCu) Solder
4.0 REWORK
4.1 Component Removal Guidelines
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The CSP ™ WLCSP rework is similar to that of a ball grid array. Prior to the rework, the
board should be baked to make the assembly moisture-free, to prevent moisture damage on
rework. The board should be uniformly supported since a tilt may result in solder bridging.
The under-board preheating is required per the following guidelines:
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• 100-110 C for 32-62 mil thick boards
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• 120-125 C for 125 mil or densely populated boards
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• 150-170 C for lead-free solder
If the component needs to be re-used, a three stage (ramp-hold-ramp) reflow profile is
required for component removal. Otherwise, a direct ramp-up can be used for shorter
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throughput. The peak temperature should be 200-205 C for eutectic solder and 240-250 C
for lead-free solder. The time above liquidus should be 45-60 seconds for eutectic solder and
up to 90 seconds for lead-free solder. The temperature change across the solder joints
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should be less than 10 C. The temperature around the rework component should be less
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than 150 C. The component top temperature should be less than 220 C for eutectic solder
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and less than 260 C for the lead-free solder. Flux is not recommended since it adds process
step and cost. The air velocity should be as low as possible to avoid component skew (e.g.,
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500 FCH for top heater, 100 FCH for bottom heater). A nitrogen atmosphere is recommended
for better heat distribution and removal. A zero-force vacuum pick-up is required during
transition to cool-down to avoid bridging of reflowed balls.
4.2 Site Redressing
Typical methods for site redressing are soldering iron with solder wick, vacuum de-soldering
and hot air scavenging. Solder wicking with flux using a 30 mil wide wick is recommended.
4.3 Component Replacement
The rework site must be cleaned with solvent prior to component replacement to remove any
surface contamination and oxide. For the solder paste/flux application, a mini stencil with
squeegee of same width as the stencil should be used. Align the apertures with pads under
50-100X magnification before paste printing. A split-beam optical system, using 50-100X
magnification, is recommended for the component alignment. The placement machine
should allow fine adjustments in X, Y, and rotational axes. The paste manufacturer’s
recommendation should be followed for the reflow profile, with the maximum temperature not
exceeding the package qualification level. The profiles developed during initial placement or
rework can also be used. The three stage (ramp-hold-ramp) profile may result in smaller
temperature distribution across the site.
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