
SZZA015
April 1999
1

2
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright

1999, Texas Instruments Incorporated

Title Page
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Power Dissipation for Voltage-Regulator Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mounting Effects on Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2
3
Thermal Test Procedures and Mounting Techniques
Test Setup
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
4
Thermal-Resistance Measurement Results
Thermal Resistance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Effects of Different Land Patterns on Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
6
Board-Level Assembly Guidelines and Solder-Joint Reliability
Experimental Results
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
9
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
9
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Land Patterns, Mechanical Dimensions, and Tape-and-Reel Specifications . . . . . . . . . . . . . . . . . . .
A–1
A–1
Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
Appendix C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C–1
Figure
1 PowerFLEX Package Family
Title Page
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Maximum Power Dissipation for Voltage Regulator Radiating in Free Air . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Maximum Power Dissipation for Regulator Mounted on PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Multilayer, Two-Signal, Two-Plane Test-Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Multilayer PCB Cross Section Showing Cu and Dielectric Thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Still-Air Junction-to-Ambient Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Junction-to-Ambient Thermal Resistance Under Various Airflow Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Land Patterns Used to Model Effects of Footprint Size on Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Comparison of SOT-223 and KTP Land Patterns Required for Equivalent Thermal Performance
10 Relationship Between Thermal Performance and Pad Size for KTP Package
. . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7
11 PCB Land Patterns Used for Board-Level Assembly
A–1 2KTP PowerFLEX
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
A–1
A–2 3KTE/5KTG PowerFLEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–2
A–3 KTP PowerFLEX Plastic Flange-Mount Package
A–4 KTE PowerFLEX Plastic Flange-Mount Package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–4
A–5 KTG PowerFLEX Plastic Flange-Mount Package
A–6 Reel Dimensions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A–5
A–6
A–7 Tape Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A–7
B–1 IR Reflow Profile Used for PowerFLEX Board-Level Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B–1
C–1 X-Rays of KTP Packages After Temperature Cycling (–65
°
C to 150
°
C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C–2 SEM Photographs of KTP Packages After 3500 Temperature Cycles (–65
°
C to 150
°
C) . . . . . . . . . . . . . . . . . . .
C–1
C–2 iii

iv

The Texas Instruments (TI

) PowerFLEX

family of voltage regulators offers surface-mount packages with high thermal-dissipation capability that can be mounted using standard techniques and equipment. This application report addresses power dissipation characteristics, footprint sizes, and land patterns; provides mechanical dimensions and tape-and-reel packing information; and illustrates solder-joint reliability of PowerFLEX packages over a wide range of temperature and cycles.
The thermally enhanced PowerFLEX family offers a surface-mount alternative to larger through-hole power packages, such as the TO-220, while maintaining high thermal-dissipation capability. PowerFLEX packages are available in a variety of footprints and pin counts and can be mounted using standard printed circuit board (PCB) mounting techniques and equipment.
This application report focuses on the 2-pin KTP, 3-pin KTE, and 5-pin KTG members of the PowerFLEX package family used as voltage regulators (see Figure 1).
TO-220
2-Pin KTP 3-Pin KTE 5-Pin KTG
Figure 1. PowerFLEX Package Family
The main topics addressed in this application report are:
•
Power dissipation characteristics of voltage-regulator packages
•
Thermal effects of mounting a package on a PCB
•
Test procedures, hardware, and mounting techniques used to determine junction-to-ambient thermal resistance and to obtain optimal thermal performance
•
Comparison of the thermal characteristics and footprint sizes of the PowerFLEX family to other popular power packages
•
Recommended land patterns, tape-and-reel packing information, and mechanical dimensions
•
Board-level assembly guidelines and solder-joint reliability of PowerFLEX packages
PowerFLEX and TI are trademarks of Texas Instruments Incorporated.
1

2
Maximum Power Dissipation for Voltage-Regulator Packages
The efficiency of a regulator is defined as P out
/P in
= (P in
– P
Loss
)/P in
. The power losses of the regulator are converted directly to heat and must be dissipated by the package (see Figure 2). The maximum allowable power dissipation of a package radiating in free air can be defined as:
P
D(max)
+
T
J(max)
* T q
JA
A
(1)
Where:
P
D(max)
T
J(max)
T
A
θ
JA
= maximum allowable power dissipation (W)
= operating junction temperature (
°
C)
= ambient temperature (
°
C)
= junction-to-ambient thermal resistance of the package (
°
C/W)
Heat
TJ(max) = 125
°
C
TA = 25
°
C
TO-220
Two-Layer PCB q
JA
+
161.3
°
C ń
W P
D(max)
+
125
°
C
*
25
°
C
161
°
C ń
W
+
0.62 W
Figure 2. Maximum Power Dissipation for Voltage Regulator Radiating in Free Air
From Equation 1, the maximum allowable power dissipation is inversely proportional to the value of the thermal resistance.
If
θ
JA
is minimized, P
D(max) can be maximized. In the past, only large form-factor through-hole power packages, such as
TO-220, were capable of small values of
θ
JA.
The advantage of the PowerFLEX family of packages is that
θ
JA is kept low, while offering compact size and surface-mount capability.
An important thing to note about Equation 1 is that the user must select the operating junction temperature T sheets specify an absolute maximum junction temperature of 150
°
C. However, operating at this temperature can severely impact reliability; TI recommends a maximum operating junction temperature of 125
°
C for its regulators.
J(max)
. Most data

Mounting Effects on Thermal Resistance
When a package is mounted on the surface of a PCB (see Figure 3),
θ
JA can be described as the sum of several different elements of thermal resistance: q
JA
+ q
JC
) q
CH
) q
HA
(2)
Where:
θ
JA
θ
JC
θ
CH
θ
HA
= junction-to-ambient thermal resistance (
°
C/W)
= junction-to-case thermal resistance (
°
C/W)
= case-to-heat-sink thermal resistance (
°
C/W)
= heat-sink-to-ambient thermal resistance (
°
C/W)
TJ(max) = 125
°
C
TA = 25
°
C
KTP
Four-Layer PCB
(embedded copper ground plane acts like a heat sink) q
JA q
JA
+ q
JC
) q
+
30
°
C ń
W
CH
) q
HA
P
D(max)
+
125
°
C
*
25
°
C
30
°
C ń
W
+
3.33 W
Figure 3. Maximum Power Dissipation for Regulator Mounted on PCB
Most of the regulators available in PowerFLEX packaging have the die pad (metal tab) in electrical contact with ground. This presents an advantage to the designer by allowing thermal vias to be placed on the surface of the PCB that are connected electrically to an embedded ground plane. Direct electrical connection lowers the thermal resistance between the case and the heat-spreading copper (Cu) layer of the ground plane,
θ
CH
. This results in a lower
θ
JA
, and improves overall power-dissipation capability. For other fixed and adjustable regulators where the bias current flows through the output, the die pad must be isolated electrically from the ground plane. The high thermal resistance of the PCB reduces the amount of heat transfer between the case and the Cu plane. For devices of this type, thermal vias cannot be used, and the benefits of direct electrical connection are not available.
3

Test Setup
The thermal resistance of the PowerFLEX packages and the other packages discussed in this application report were measured and/or modeled according to JEDEC standards (JESD 51, JESD 51-1, JESD51-2, and JESD 51-6). For measured data, the packages were soldered directly to the PCB. The test board used for the measured data meets the JEDEC standards for multilayer, direct-thermal-attachment test boards (JESD 5-7, JESD 5-5) and has the following characteristics:
•
FR-4 PCB material (see Figure 3 for dimensions)
•
Two embedded 1-oz Cu planes and one floating lower Cu plane (see Figure 5)
•
Supplier-recommended land patterns on the top surface of the board (2-oz Cu)
•
Thermal vias connecting the upper Cu plane to the package thermal pad where applicable
A = 101.6 mm
1 mm
1 mm 99.6 mm
B = 114.3 mm
E = 2.39 mm
D = 3.96 mm
F = 74.17 mm
C = 9.53 mm
Figure 4. Multilayer, Two-Signal, Two-Plane Test-Board Dimensions
Component Trace, 2 oz†
A Vias
1.6 mm
A
0.25 mm
≤
A
≤
0.50 mm
† Finish thickness: 1 oz/ft2 = 0.036 mm, 2 oz/ft2 = 0.071 mm
Plane 1, 1 oz, Solid†
Plane 2, 1 oz, Solid†
Backside Trace, 2 oz†
Figure 5. Multilayer PCB Cross Section Showing Cu and Dielectric Thickness
Still-air
θ
JA measurements were performed with the test board in a 1-ft
3
box. Forced-airflow measurements were made in a calibrated wind tunnel. All measurements were performed at ambient temperature. Conditions used for the measured data also were used for the modeled data. The PowerFLEX data shown in this application report consists of both measured and modeled values; other package data was only modeled. All modeled data was gathered using Thermcal

, a proprietary program used internally by TI. The modeled PowerFLEX data is accurate to within 5% of the measured values.
Thermcal is a trademark of Texas Instruments Incorporated.
4

To maintain consistency between the thermal models, an array of 0.33-mm (0.013”) diameter vias on a 1.27-mm (0.050”) pitch grid was used. The vias extend from the top surface of the PCB to the first of two 1-oz buried Cu planes. These via grids are arranged within the recommended footprint for each package (see Appendix A). Vias were not placed outside of the recommended footprint when a larger Cu land pattern was used on the top surface of the PCB for enhanced thermal performance.
Thermal Resistance
Still-air
θ
JA values are shown in Figure 6 for the KTP, DPAK (TO-252), SOT-223, and KTE packages. The KTP and DPAK thermal resistances are virtually the same, and their
θ
JA values are 30% lower than for the SOT-223.
Because of the reduction in
θ
JA
, the KTP package has better power-dissipation capability than the SOT-223. The KTP package has the same
θ
JA as the DPAK, but has slightly smaller dimensions and a thinner profile.
40
35
30
25
20
15
10
5
0
SOT-223 KTP DPAK
Package Type
KTE
Figure 6. Still-Air Junction-to-Ambient Thermal Resistance
In addition to still-air measurements, the value of
θ
JA was modeled for forced airflow conditions. Figure 7 shows the results for the KTP, DPAK, SOT-223, and KTE packages.
40
30
20
SOT-223
KTP
DPAK
KTE
10
0
0 150
Airflow – lfm
250 500
Figure 7. Junction-to-Ambient Thermal Resistance Under Various Airflow Conditions
The SOT-223 package has much higher values of
θ
JA than the KTP and DPAK packages. The KTE package has a lower
θ
JA than SOT-223, KTP, and DPAK packages because of its larger form factor. Thus, the PowerFLEX devices have improved power-dissipation capability compared to the SOT-223 and DPAK packages.
5

6
Effects of Different Land Patterns on Thermal Resistance
Still-air
θ
JA values were modeled for the KTP package using four different PCB land patterns (see Figure 8). The four land patterns selected represent approximate Cu footprint sizes for KTP, DPAK, KTE, and TO-220 packages. A thermal-test chip with dimensions of 3 mm (0.12”) square was assembled in the test packages.
0.242 (6.15)
0.052 (1.32) TYP
0.242 (6.15)
0.046 (1.17) TYP
Cu Pattern
0.054 (1.37)
0.038 (0.96) TYP
0.170 (4.32)
0.090 (2.29) TYP
Pattern 1 (KTP)
Solder Mask
Over Cu
Cu Pattern
0.038 (0.96) TYP
0.054 (1.37)
0.150 (3.81)
0.090 (2.29) TYP
Pattern 2 (DPAK)
0.400 (10.16)
0.125 (3.18) TYP
0.079 (2.01) TYP
0.360 (9.14)
0.105 (2.67) TYP
0.059 (1.50) TYP
Cu Pattern
Solder Mask
Over Cu
0.100 (2.54)
Solder Mask
Over Cu
Cu Pattern
0.100 (2.54)
0.054 (1.37) 0.054 (1.37)
0.038 (0.96) TYP
0.150 (3.81)
0.090 (2.29) TYP
Pattern 3 (KTE)
0.038 (0.96) TYP
See Appendix A for Recommended PowerFLEX Land Patterns
0.150 (3.81)
0.090 (2.29) TYP
Pattern 4 (TO-220)
Figure 8. Land Patterns Used to Model Effects of Footprint Size on Thermal Resistance
The measured thermal resistance values for the land patterns shown in Figure 8 are:
Pattern
θ
JA
(
°
C/W)
1 30.5
2
3
4
29.4
27.2
25.8

Although power dissipation can be improved by increasing the size of the Cu land pattern on the top side of the PCB, the size of the land pattern may become impractical for smaller form-factor packages. For example, to obtain the same thermal performance of the KTP, the SOT-223 must use a Cu pattern that is at least four times the standard KTP land pattern (see
Figure 9). With this enlarged pattern,
θ
JA
for the SOT-223 is lowered to 32–33
°
C/W, but is still slightly higher than the
30
°
C/W of KTP using the standard recommended pattern.
2
KTP
3
SOT-223
Figure 9. Comparison of SOT-223 and KTP Land Patterns
Required for Equivalent Thermal Performance
Figure 10 shows the estimated land pattern required for various values of
θ
JA using the KTP package. As the area of the pattern is increased, the value of
θ
JA
decreases; therefore, the maximum allowable power dissipation increases.
36
34
32
30
28
26
24
22
20
Power
θ
JA
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
6 12.5
L – Pad-Side Length – mm
20
Figure 10. Relationship Between Thermal Performance and Pad Size for KTP Package
7

The Morgan Newton Co., Garland, Texas, provided TI with their recommendations for stencil design, solder-paste type, and infrared (IR) profile. A board-level evaluation of the KTP package was performed using these recommendations. The objectives of the evaluation were:
•
Show that the KTP package can be mounted onto the standard DPAK land pattern with no board-level reliability issues.
•
Show that a solder mask applied over an enlarged Cu land pattern can provide improved thermal performance with no board-level reliability issues.
The stencil parameters, materials, etc., used for this experiment include:
•
Solder paste type
•
Alloy type
No clean
Sn62/Pb36/Ag2
•
Solder past particle size 325 to 500
•
Stencil type
•
Stencil thickness
•
Squeegee type
•
IR reflow profile
301 stainless steel, laser cut
8 mil
Metal
See Appendix B
Three different land patterns were used for board-level assembly of the KTP package: the KTP pattern, the standard DPAK pattern, and a modified KTP pattern with a larger area and solder mask over the Cu for improved thermal performance (see
Figure 11).
0.242 (6.15)
0.052 (1.32) TYP
0.360 (9.14)
0.105 (2.67) TYP
0.059 (1.50) TYP
Cu Pattern
Cu Pattern
Solder Mask
Over Cu
0.100 (2.54)
0.054 (1.37)
0.054 (1.37)
0.038 (0.96) TYP
0.170 (4.32)
0.090 (2.29) TYP
KTP Pattern
0.038 (0.96) TYP
0.150 (3.81)
0.090 (2.29) TYP
Modified KTP Pattern
0.200 (5.08)
Cu Pattern
0.118 (3.00) TYP
0.063 (1.60) TYP
0.193 (4.90)
0.90 (2.29) TYP
Standard DPAK Pattern
See Appendix A for Recommended PowerFLEX Land Patterns
Figure 11. PCB Land Patterns Used for Board-Level Assembly
8

Experimental Results
Solder-joint inspections and electrical tests were made on all three copper patterns every 500 temperature cycles up to
3500 cycles. No solder-joint anomalies or opens were found.
X-rays of the solder joints at various stages of the temperature-cycle tests and scanning electron microscope (SEM) photos of cross-sectioned KTP packages (3500 temperature cycles) are shown in Appendix C.
The PowerFLEX voltage-regulator packages offer excellent thermal performance for medium- to high-power applications.
The packages maintain low junction-to-ambient thermal resistance, while providing the added benefit of surface-mount capability. The KTP package has equivalent thermal performance to the DPAK (TO-252) package and improved thermal performance over the SOT-223 package. In addition, the PowerFLEX packages can be mounted using standard PCB mounting techniques and equipment. The KTP package can easily be soldered onto the standard DPAK footprint. Package land patterns with solder mask over an enlarged copper area offer improved thermal performance with no decrease in board-level reliability.
The authors of this application report are Patrick Griffith and Craig St. Martin. Terrill Sallee provided assistance for board-level assembly and reliability testing of PowerFLEX products; Doug Romm for thermal-impedance model generation of all packages discussed in this report; and Paul Hundt for thermal-impedance measurement of two PowerFLEX units on various land patterns.
EIA/JESD 51, Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device).
EIA/JESD 51-1, Integrated Circuit Thermal Measurement Method – Electrical Test Method (Single Semiconductor Device).
EIA/JESD 51-2, Integrated Circuit Thermal Test Method Environmental Conditions – Natural Convection (Still Air).
EIA/JESD 51-5, Extension of Thermal Board Standards for Packages With Direct Thermal Attachment Mechanisms.
EIA/JESD 51-6, Integrated Circuit Thermal Test Method Environment Conditions – Forced Convection (Moving Air).
EIA/JESD 51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
Texas Instruments, Thin Very Small-Outline (TVSOP) Application Report, literature number SCBA009.
Texas Instruments, PowerFLEX

Surface-Mount Power Packaging Application Report, literature number SLIT115.
9

10

X2
Y2
Solder Mask Over Cu
(optional)
Y1
Z
W
X1
L
P
PINS
2
PACKAGE
CODE
KTP
L P W X1 X2 Y1 Y2 Z
1.37
2.29
0.96
3.81
6.15
4.79
1.3
9.9
NOTES: A. All dimensions are in millimeters (mm).
B. Publication IPC-SM-782 is recommended for alternative designs.
C. Solder mask placed over Cu can be used for improved thermal performance.
Figure A–1. 2KTP PowerFLEX
A–1

X4
X3
X2
Solder Mask Over Cu
(optional)
Y3
Y2
Y1
Z
X1
L
P
(N places)†
W
PINS
3
5
PACKAGE
CODE
KTE
KTG
L N
1.37
2
1.37
4
P W X1 X2 X3 X4
2.54
0.96
6.4
0.76
0.79
9.5
1.72
0.96
6.4
0.76
0.79
9.5
Y1 Y2 Y3 Z
5.56
1.3
1.56
11.4
5.56
1.3
1.56
11.4
† N = number of leads
NOTES: A. All dimensions are in millimeters (mm).
B. Publication IPC-SM-782 is recommended for alternative designs.
C. 3-pin PowerFLEX shown.
D. Solder mask placed over Cu can be used for improved thermal performance.
Figure A–2. 3KTE/5KTG PowerFLEX
A–2

KTP (R-PSFM-G2) PowerFLEX

PLASTIC FLANGE-MOUNT PACKAGE
0.243 (6,17)
0.233 (5,91)
0.228 (5,79)
0.218 (5,54)
0.130 (3,30) NOM
0.080 (2,03)
0.070 (1,78)
0.010 (0,25) NOM
0.215 (5,46)
NOM
0.381 (9,68)
0.371 (9,42)
0.100 (2,54)
0.090 (2,29)
0.090 (2,29)
0.180 (4,57)
0.247 (6,27)
0.237 (6,02)
0.287 (7,29)
0.277 (7,03)
0.032 (0,81) MAX
0.031(0,79)
0.025(0,63)
0.010 (0,25) M
0.005(0,13)
0.001(0,02)
Seating Plane
0.004 (0,10)
0.047 (1,19)
0.037 (0,94)
Gage Plane
0.010 (0,25)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Figure A–3. KTP PowerFLEX Plastic Flange-Mount Package
2
°
– 6
°
4073388/K 10/98
PowerFLEX is a trademark of Texas Instruments Incorporated.
A–3

KTE (R-PSFM-G3)
0.295 (7,49)
NOM
0.420 (10,67)
0.410 (10,41)
0.100 (2,54)
0.200 (5,08)
1
0.375 (9,52)
0.365 (9,27)
0.360 (9,14)
0.350 (8,89)
0.220 (5,59)
NOM
PowerFLEX

PLASTIC FLANGE-MOUNT PACKAGE
0.080 (2,03)
0.070 (1,78)
0.050 (1,27)
0.040 (1,02)
0.010 (0,25) NOM
Thermal Tab
(See Note C)
0.320 (8,13)
0.310 (7,87)
0.360 (9,14)
0.350 (8,89)
3
0.025 (0,63)
0.031 (0,79)
0.010 (0,25) M
Seating Plane
0.004 (0,10)
0.005 (0,13)
0.001 (0,03)
0.010 (0,25)
NOM
Gage Plane
0.041 (1,04)
0.031 (0,79)
3
°
– 6
°
0.010 (0,25)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. The center lead is in electrical contact with the thermal tab.
D. Dimensions do not include mold protrusions, not to exceed 0.006 (0,15).
Figure A–4. KTE PowerFLEX Plastic Flange-Mount Package
4073375/E 05/98
PowerFLEX is a trademark of Texas Instruments Incorporated.
A–4

KTG (R-PSFM-G5)
0.295 (7,49)
NOM
0.420 (10,67)
0.410 (10,41)
0.067 (1,72)
0.268 (6,81)
1
0.375 (9,52)
0.365 (9,27)
0.360 (9,14)
0.350 (8,89)
0.220 (5,59)
NOM
PowerFLEX

PLASTIC FLANGE-MOUNT PACKAGE
0.080 (2,03)
0.070 (1,78)
0.050 (1,27)
0.040 (1,02)
0.010 (0,25) NOM
0.360 (9,14)
0.320 (8,13)
0.350 (8,89)
0.310 (7,87)
Thermal Tab
(See Note C)
5
0.031 (0,79)
0.025 (0,63)
0.010 (0,25) M
Seating Plane
0.004 (0,10)
0.005 (0,13)
0.001 (0,03)
0.010 (0,25)
NOM
Gage Plane
0.041 (1,04)
0.031 (0,79)
3
°
– 6
°
0.010 (0,25)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. The center lead is in electrical contact with the thermal tab.
D. Dimensions do not include mold protrusions, not to exceed 0.006 (0,15).
Figure A–5. KTG PowerFLEX Plastic Flange-Mount Package
4073377/E 05/98
PowerFLEX is a trademark of Texas Instruments Incorporated.
A–5

A–6
2.0 MIN
Flange
Thickness
100
∅
33.0
±
2.0
G
T MAX
20.2 Diameter MIN 1.5 MIN
Three Slots Through
13.0 + 0.2 Diameter
Through Hole
NOTE A: Dimensions are in millimeters (mm).
PACKAGE PINS
KTP
KTE
KTG
2
3
5
TAPE WIDTH
(G)
(mm)
16
DIMENSIONS
REEL THICKNESS
(T)
(mm)
20
24
24
28
28
PARTS
PER
REEL
2500
1000
1000
Figure A–6. Reel Dimensions

2.0
±
0.1 TYP
4.0 TYP
P TYP
∅
1.5
+0.1
–0.0
TYP
1.75
F
W
BO
KO
K
0.3 TYP Wall
∅
1.5 MIN
AO
Device Orientation
User Feed Direction
NOTE A: Dimensions are in millimeters (mm).
PACKAGE PINS
KTP
KTE/KTG
2
3/5
WIDTH
(W)
16
24
POCKET
PITCH
(P)
12
16
DIMENSIONS (mm)
POCKET
WIDTH
(AO)
6.50
POCKET
LENGTH
(BO)
10.0
POCKET
DEPTH
(KO)
2.20
9.80
11.0
2.20
TAPE
DEPTH
(K)
2.60
2.60
DIMENSION
(F)
7.50
11.50
Figure A–7. Tape Dimensions
A–7

A–8

Company: Morgan Newton Co.
Process: CONC
Printed:
Site:
06/25/1998
Cambridge
Product: PR2001-E
Line Speed: 25 in/min
1 2 3
200
4
150
TI_FLEX
5 6 7
Time Above 183
°
C = 93 s
Time Above 160
°
C = 199 s
End
Time Above 200
°
C = 60 s
100
50
0:00.0
0
Speed
25 in/min
ZONE
Upper
Lower
1
140
140
2:00.0
50
2
190
190
4:00.0
Distance – inches
100
3
210
210
4
180
180
5
190
190
6
255
255
Figure B–1. IR Reflow Profile Used for PowerFLEX Board-Level Study
6:00.0
150
7
220
220
B–1

B–2

500
Land Pattern #3
Number of Temperature Cycles
2000 3500
Land Pattern #2
Land Pattern #1
Figure C–1. X-Rays of KTP Packages After Temperature Cycling (–65
°
C to 150
°
C)
C–1

Pattern 1
Cu Leadframe
Solder
Cu Land Pattern
Pattern 2
Solder
Cu Leadframe
Cu Land Pattern
Pattern 3
Cu Land Pattern
Cu Leadframe
Solder
Solder Mask
C–2
Figure C–2. SEM Photographs of KTP Packages After 3500 Temperature Cycles
(–65
°
C to 150
°
C)