Non-Volatile Register based on hybrid Spintronics/CMOS technology
Weisheng Zhao 1, 2*, Eric Belhaire 1, 2, Claude Chappert 1, 2, Virgile Javerliac 3 , Pascale Mazoyer4
1 IEF~ CNRS~ Orsay~ F-91405
2 Univ Paris-Sud~ UMR 8622, Orsay, F-91405
3 Crocus Technology, Grenoble, France
4 STMicroelectronics, 850 rue Jean Monnet 38926 Crolles, France
*Email: weisheng.zhao@u-psud.fr
Abstract
In this paper~ we present a non-volatile register based
on hybrid Spintronics/CMOS technology, which can
store securely and non-vocatively all the intermediate
data in the logic circuits as FPGA and ASIC. The
non-volatility of this register allows to power down the
circuits keeping the data thereby reduce significantly the
standby power and accelerate the chip re (boot) latency.
Based on STMicroelectronics 90nm design kit and a
complete MT J Spice model for MRAM development,
the delay propagation of this register is lower than
500ps. We propose also the solutions to overcome the
high sensitivity issue for this non-volatile register.
1. Introduction
The leakage currents have become one of the most
critical issues since CMOS fabrication technology scaled
down to 90nm or below, and they can be increased
exponentially for the next MOS shrinking [1]. Thereby
they cause the standby power to become more important
than the active power and the major dissipation source~
especially in the latch register which memorizes the
intermediate data in the logic circuits [2]. The
conventional register is based on the charge data storage
principle and requires power to keep the data even if it is
in "idle" state [3]. If the power is removed from the
circuits, the charge quickly drains off, destroying any
data that the charge represents. There is an urgent
requirement for the non-volatility of register; in this
case, the circuits in '''idle'' state can be powered down
completely and the standby power may be reduced down
to nearly zero.
The high speed and infinite endurance requirements 0 f
register limits most of the present non-volatile storage
technology as Flash, Phase Change RAM (PCRAM) and
Ferroelectric RAM (FRAM) etc [4]. Magnetic Tunnel
Junction (MTJ) [5], the basic element for Magnetic
RAM (MRAM) is the only candidate to bring the
non-volatility into the register (see Table 1). Benefiting
from the high sensing speed ofMTJ, the chip (re)boot
latency can be down to sonle hundred pico second.
Magnetic Non-Volatile Flip-Flop (MNVFF) [6] has been
proposed to memorize securely and synchronize the
intermediate data after the computing units in the logic
circuits as FPGA and demonstrated the data restoring
latency lower than 200ps. Ho\vever MNVFF \vorks
always synchronously~ driven with clock signal; while
there are many applications requiring the simple
non-volatile register or latch to save the intermediate
data securely, such as in the asynchronous chips.
Therefore we design the non-volatile register to address
these applications.
Another advantage of hybrid MTJ/CMOS technology
is that the storage element MTJ does not consume much
die area as its vertical structure allows it to be processed
above the transistor level integration in the back-end
process (see Fig.1) [7]. The dimension of an MTJ is as
well as very small (e.g. 75nm x 120nm).
Table 1. Non-volatile Storage Technology@IMHz
Technology
Endurance
Lifetime@I MHz
Flash
10e6
Impossible
(limited speed)
PCRAM
IOe12
11,57 days
FRAM
IOeI3
115,7 days
MTJ
Infinite
Infinite
Figure.I MTJ is composed of three principle layers: an
oxidation barrier, such as MgO and AlxOy; a Pinned
layer and a storage layer, which are ferromagnetic
Materials (e.g. CoFeB). The spin direction in pinned
layer is fixed, but can be changed in the storage layer,
there are so that two states of MTJ: parallel and
anti-parallel when the spin direction in pinned layer and
free layer are in the same direction or the opposite
direction.
The body of this paper includes three parts, in the first
section, the design of Magnetic Non-volatile Register
(MNVR)
will
be
introduced,
based
on
STMicroelectronics 90nm design kit [8] and a complete
MTJ spice model [9], and we have also simulated the
transient response of this logic component. In the second
section, we present the stability optimization methods at
last we discuss and conclude.
978-1-4244-2186-2/08/$25.00 ©2008 IEEE
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2. Magnetic Non-Volatile Register (MNVR)
2.1 Design ofMNVR
We design the Magnetic Non-volatile Register
(MNVR), which is transparent and independent with any
clock signal. Fig.2 shows the schematic of the MNVR,
which is composed by four parts of circuits~ the tirst one
is the write circuit (see Fig.3) the same as that used in
MNVFF, based on four NMOS transistors generating the
high current in dual directions; the second is two PMOS
transistors (MPO, MP 1) polarized with the control signal
"'Enable", which enables the sensing circuit: the third
part of MNVR is the four transistors based current
comparator sense amplifier (MP2~3 and MN2,3), it
detects and amplifies the different currents passing
through the two MT1s and the last one is a simple
inverter amplifier (MN4 and MP4), which output the
amplified signal in logical level. It is important to
mention that the power source of the sensing and
switching circuits Vdd_Logic, Vdda should be different
to optimize the area performance of the MNVR, because
improving the voltage supply of NMOS transistor allows
to reduce its width keeping the same drain current [3]. In
our design based on 90nm technology, they are set to
1.2V and 3.3V respectively, the die area of the switching
circuit can be thus economized up to about 60%.
This circuit is suitable for the Field Induced Magnetic
Switching (FIMS) [10] and Thermally Assisted
Switching (TAS) [11] MTl switching approaches, but
not for Spin Transfer Torque (STT) [12] as the switching
and sensing of the couple of MTl device should be able
to operate at the same time in this register. In the STT
switching approach, the current passing trough the MTl
write and read it in different direction [13], thereby the
two operations should be fully separated.
Vdd_IoP
Figure 2. The sensing circuit of MNVR, which are
composed of three parts of circuits
Figure 3. The switching circuit ofMNVR, each time two
NMOS are active and the others are inactive.
Figure.4.1 The propagation delay is lower than 500ps (350ps for MTl switching and 150ps for data sensing)
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2.2 Transient simulation of MNVR
In MNVR, the output can be induced directly by the
input without other control signal; thereby the delay
includes only the switching, sensing time of MTJ device
and the circuit logic delay. Based on STMicroelectronics
90nm design kit and a complete MTJ spice simulation
model, the whole propagation delay of this register is
found less than 500ps (see Fig.4.1).
As all the data sensing amplification circuit, One of
the most critical issue for this MNVR is that it is very
sensitive to nlismatch variation due to the comparator
sense amplifier circuit where all the four transistors
operate in saturation mode and the low bias voltage
between the two MTJs, about 30% errors are found in
the output with the Monte Carlo analog statistical
simulation as the TMR of MTJ is set to 100% and the
resistance of MTJ is 30KOhm (see Fig.4.2), therefore
MNVR should be optimized before its wide applications.
barrier. Before the using of MgO crystalline barrier since
2004, the best TMR ratio with conventional AlxO
amorphous barrier is 70% at most. The recent
experiments demonstrated that the TMR may be up to
500% at room temperature [16].
Figures 5.1 and 5.2 demonstrate the error percentage
of the MNVR can be greatly reduced by the increasing
of resistance and TMR ratio of MTJ respectively,
however it is not sufficient for practical applications
because there are still about 5% errors in the output even
the TMR ratio is set up to 600%, therefore we should
continue the second step to reduce further the errors.
R(O)
lox
=
223.76x qJ
R(V") =
Statistical Analysis for the til NVR
-]/2
xexp(1.025xloxXqJ)
-1/2
2
R(~)
.fox Xe Xm
1+(
-2
_
4xh x({J
TMR
1.0
x surface
)X
(1)
V2
(2)
= TMR(O)
real
V'2
1+2
Vh
.75
52
.5
~
.25
50
~
48
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46
Q.
Q)
£; 44
10.1
10.2
10.3
time (ns)
10.4
10.5
10.6
Figure.4.2 Transient response of statistical analysis for
the MNVR, 3 outputs in error are found for 10 run due to
the mismatch variation.
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2.3 Stability optimization
In order to improve the stability of MNVR to
mismatch variation, we propose two steps. The first step
is to increase the resistance of MTJ device and TMR
ratio thereby larger the bias voltage difference between
MTJI and MTJO. There are two methods, obtained from
the model of Brinkman (1) [14] able to higher the
resistance, either scale down the dimension of MTJ
(surface) or raise the thickness of oxide barrier (tox). As
the shrinking of MTJ will lead to the fabrication
difficulty, the most efficient way is to manipulate the
thickness of oxide barrier; furthermore no extra cost will
be required. However, there is a limit for the improving
of resistance, because the higher resistance will increase
the bias voltage 0 f MTJs and reduce the real TMR ratio
(2) [15]. Vh is the bias voltage when the real TMR ratio
is 50% of that with zero bias voltage. The raising of
TMR ratio is not easy as the resistance, because it
depends mainly on the material composition of oxide
34
10K
20K
40K
50K
80K
100K
120K
Resistance of MTJ(Ohm)
Figure. 5.] The stability of MNVR improves with the
increasing of resistance (TMR ratio=50%, all the
transistors are at minimum size)
The second step is to define the fit transistor size for
the comparator and inverter amplifier, in this case, the
die area will be enlarged but the circuit can be more
stable to mismatch variation. For example, in the inverter
amplifier (MP4 and MN4), if the two transistors are at
the minimum size the voltage of operating point will be
close to the Vdd_logic and this may lower the sensing
margin. In order to improve the stability of this
amplifier, we should change the size of MOS to set the
operating point to be equal to 0.5*Vdd_Iogic and realize
the maximum margin. Figure 6 demonstrates that the
errors can be lower than t % as the size of transistors is
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the sixth Framework, Contract Number 510993:
MAGLOG. The views expressed are solely those of the
authors. and the other Contractors and/or the European
Community cannot be held liable for any use that may be
made of the information contained herein.
enlarged and the TMR ratio increases up to 350%.
40
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References
o
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Q)
0>
n:I
C
Q)
~ 10
Q)
a.
D
~
0
100
200
300
400
500
600
700
800
TMR ratio(%)
Figure. 5.2 The stability of MNVR improves with the
increasing of TMR ratio (Rmtj=50KOhm. all the
transistors are in minimum size)
40
t"5
Q.
"5
•
\
\
30
o
Q)
£
.!; 20
Q)
0>
C
~Q)
-\•
\
n:I
10
a.
D
-~
'. --------~
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50
100
150
200
250
300
350
TMR ratio (%)
Figure. 6 The stability of MNVR improves with the
increasing of TMR ratio (Rmtj=50KOhm. all the PMOS
and NMOS in the comparator and amplifier are 1,05um
and 0,35um respectively. MPO and MPI are 0.5um)
3. Conclusion
The MVNR detTIonstrates high speed, low propagation
delay and data non-volatility. therefore it promises to
bring the non-volatility or security for the intermediate
data in the logic circuits. As its switching and sensing
operations are independent to the chip clock, it may be
advantageously used in the asynchronous logic chip. The
solutions addressing to the stability optimization have
been evaluated and simulated, which will be very useful
for the hybrid Spintronics/CMOS logic circuit designers.
Acknowledgments
The work and results reported were obtained with
research funding from the European Community under
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