9. Single-end operational
amplifier (OPA)
Kanazawa University
Microelectronics Research Lab.
Akio Kitagawa
9.1 Specification of OPA
2
Parameters of OPA
Parameter
Design constraint
Description
VDD (V)
max/typ/min
IBias (uA)
max
Total bias current
Open loop gain Ad (dB)
min
Differential gain
Sampling frequency fS (Hz)
max
For discrete CMFB OPA
GBP (Hz)
min
Unity gain frequency
SR (V/us)
min
>> 2*VDD/fS
Settling time (us)
max
< 2/fs
Phase margin (deg)
min
> 60 deg.
Common-mode input range (V)
min/max
Output swing (V)
min/max
Power supply voltage
> Differential input range
Input-referred noise level (uV @Hz)
max
In frequency range
Input-referred offset VOS (V)
max
CMRR (dB)
min
Common Mode Rejection Ratio
PSRR (dB)
min
Power Supply Rejection Ratio
Load resistance, capacitance (ohm, F)
typ
Possible external load
3
Sample Format of specification sheet
Parameter
Target
value
Simulation
min.
typ.
Measured value
max.
min.
typ.
Unit
Comment
max.
VDD
1.8
V
Bias current
312
uA
82
dB
320M
Hz
Load=100fF
Load=100fF
Open loop gain
GBP
SR
244
V/us
Settling time
24n
us
CMRR
-185
dB
PSRR
-150
dB
50
nV/Hz0.5
upper
-0.5
V
lower
0.9
V
Noise level
Commonmode input
range
Estimated from the host system of the circuit
No input
Error 1%
@1MHz
4
Circuit configuration of OPA
Phase compensation
Differential amp. Voltage amp. Output buffer
2 stage voltage amplifier
(CS + CS or CS + CG)
Class A or AB output buffer
The output buffer may be omitted to reduce the power consumption,
if the OPA drive only the capacitive load or operate with high loop
gain.
5
AC characteristic of OPA
Placed by the phase
compensation at u < p2
RF C F
Vin
|A|
+
Vin
+
A
- d
-
u（GBP）
1
Av
-20dB/DEC
CL
Vout
+
p1
Small-signal
V1
Vin
Rout 1
+
RF C F
Rout 3
CL
+
-
+
-
Ad (Vin -Vin )


Vout
AVV1
+
V2
1
1
V2 
V2
1  j  Rout 3C L
1  j /  p 2

-40dB/DEC
Placed by CF
Rout 2
+
Vin
V2
p2
Vout
+

0
-90
Depending on CL

-180
The phase margin is decreased
6
for the very large CL.
9.2 Analysis of 2-stage CS OPA
7
Structure of 2-stage OPA
M4
M3
M1
in
M6
Cc
M2
+
in
out
M7
Bias
M5a
M5b
Differential amplifier CS amplifier
Ad  g m1  (rds 2 // rds 4 )  g m 6  (rds 6 // rds 7 )
(without the output
buffer)
8
Bias current dependence of the
differential gain
Differential amplifier stage
AV 1   g m1  (rds 2 // rds 4 )
g m1  21 I DS1
CS amplifier stage
AV 2   g m 6  (rds 6 // rds 7 )
g m 6  2  6 I DS 6
rds 2 
1
1

2 I DS 2 2 I DS1
rds 6 
1
1

6 I DS 6 6 I DS 6
rds 4 
1
1

4 I DS 4 4 I DS1
rds 7 
1
1

7 I DS 7 7 I DS 6
Total gain
Ad  AV 1 AV 2 
2 1 6
g m1 g m 6

( g ds 2  g ds 4 )( g ds 6  g ds 7 ) (2  4 )(6  7 )
1
I DS1 I DS 6
9
Phase compensation (1)
Constraint for p2 and u
Cannot used for the NFB circuit
0
V
-20dB/Dec
-40dB/Dec
0dB

p1’
p1
Phase compensation
u’ p2 u



 p1   p 2  u (bad stability)
(good stability)
 p1  u   p 2 ･p2
Margin
･p2
Phase rotation
10
Phase compensation (2)
Constraint for z and u
Constraint for p2 and z
V
-20dB/Dec



 z  10  u
(The generation of zero is inevitable in the
feedback phase compensation circuit.)
-40dB/Dec
0dB

 p 2  2  u
p1
u p2 Z
Phase margin °
2 times
10 times

 p1   u   p 2   z 11
Miller capacitance phase
compensation technique
c
V1
V2
L
gs6
o1
o2
The input parasitic capacitance of M6 is Cgs6, but the input capacitance of
the 2nd amplifier is controlled by the Miller capacitance CM.
C M  AV 2  CC  C gs 6  AV 2  CC
12
Design of the frequency response
Pole and Zero frequency and the circuit parameters
 p1 
1
( AV 2CC )  Ro1
  p1 
u  AV 1  AV 2 (Miller effect)
AV 1
g
 m1
CC  Ro1 CC
(Miller effect)
Z 
g m6
CC
(Feed forward through Cc)
 p2 
g
1
 m6
C L  Ro 2 C L
(The output capacitance of 2nd amplifier)
In the frequency range more than u, the input signal and output signal
level is comparable, approximately, AV2=Gm2･Ro2= -gm6･Ro2≒ -1.
13
Constraint of the phase compensation
60°Phase margin
Separation between z and u
 p 2  2 u
 Z  10 u
g m6
g m1
2
CL
CC
g m6
g m1
 10
CC
CC
Phase compensation
Constraint
g m 6  10 g m1
CC  0.2C L
14
Location of the zero (1)
The phase compensation using CC requires the constraint
gm6 > 10gm1 to remove the influence of ωZ. this method
requires the very large gm6. RC phase compensation can be
used to evade this problem.
ZC
vout
vin
1
RO g m (1  j  CC
)
gm

1  j  CC RO
add Rc
vout

vin
1
)
ZC gm
R
1 O
ZC
RO g m (1 
15
Location of the zero (2)
ZC
vout

vin
1
)
ZC gm
R
1 O
ZC
RO g m (1 
1
 RC )}
gm
1  j  CC ( RO  RC )
RO g m {1  j  CC (
Z 
1
1
CC (
 RC )
gm


RO g m {1  j /  Z }
1  j /  p 3
Method (1) : If RC = 1/gm, ωZ → ∞ (Nulling the zero)
Method (2) : If RC > 1/gm, ωZ is located in the left half plane (the
phase turns counterclockwise.)
16
Practical Rc implementation by
MOSFET output conductance
Same size
I DS 6 
From
Differential
Amp.
S
D
g m6
p
(VGS 6  VTp ) 2
2
I
 DS 6   p (VGS 6  VTp )
VGS 6
1 2
I DS _ MC1   p {(VGS _ MC1  VTp )VDS _ MC1  VDS
_ MC1}
2
I DS _ MC1
g ds _ MC1 
  p (VGS _ MC1  VTp )
VDS _ MC1
VDS _ MC 1  0
M7 and MC4 are the same size.
M6, MC1, MC2, and MC3 are the same size.
gm6 = gds_MC1, z→ ∞
(see slide 16)
VGS_MC3 + VGS_MC2 = VGS6 + VGS_MC1
VGS_MC1 = VGS_MC3 + VGS_MC2 - VGS6 = VGS6 + VGS6 - VGS6 = VGS6
17
Indirect phase compensation (1)
Blocking the feedforward path by the feedback buffer amplifier
C
1
Feedback path
-A
＝
in
out
iin  j  C (vin  vout )
vout   A  vin
iin
 j  C (1  A)
vout
18
Indirect phase compensation (2)
Source follower feedback buffer
Common-gate feedback buffer
1
C
out
Bias
Advantages:
• High SR, High p2, High u, small Cc
Disadvantage:
• Additional power consumption
19
Indirect phase compensation (3)
100/1
100/1
100/1
Common gate feedback buffer
100/2
100/1
100/2
Long L will help the adjustment
of the output offset voltage.
50/2 50/2
200/4
200/4
200/4
200/4
50/2
50/2
The cascode current mirror load is used in place of the feedback buffer.
There is no additional power consumption.
20
9.3 Optimization of MOSFET size
21
ISS and SR
Vin＋－Vin－
VCap
I DS 5
t
CC
t
t
VCap
I DS 5
1

I
dt

t
DS 5

CC
CC
SR 
I DS 5
CC
out
c
in
VCap
+
in
-Iout
IDS5
Bias
SR is limited by the current ISS (IDS5) and Iout.
22
Saturation of M4 (1)
GS4
VDS 3  VGS 3  VTp   OV 3
DS4
GS6
M3 always operates in the saturation region.
VDS 4  VGS 6
out
c
in
+
in
If VGS 4  VGS 6 ,
Bias
VDS 4  VGS 6  VGS 4  VGS 4  VTp   OV 4
M4 always operates in the saturation region.
MOSFET size should be optimized for VGS4 = VGS6.
23
Saturation of M4 (2)
If VGS 4  VGS 6 ,
I DS 6
I DS 4
W

L

W

L


6


4
VGS 5  VGS 7 W 
 
I DS 7  L  7

I DS 5  W 
 
 L 5
GS4
GS6
out
+
in
in
c
-
Bias
GS5
GS7
24
Saturation of M4 (3)
I DS 6  I DS 7
I DS 5  2 I DS 4
GS4
GS6
I DS 6
I DS 7
2
I DS 4
I DS 5
Saturation condition of M4
W 
W 
 
 
 L 7
 L 6
2
W 
W 
 
 
 L 4
 L 5
out
in
+
in
c
-
Bias
GS5
GS7
25
Systematic offset (1)
IDS6
VA
VB
Systematic offset
Current balance of M6 and M7
Random offset
Process variation of VT
IDS7
When VA = VB ( differential input = 0),
the output current = 0 or IDS6 = IDS7.
26
Systematic offset (2)
I DS 3 
I DS 5 
I DS 6 
I DS 7 
3
2
5
2
6
2
7
2
(V A  VTp ) 2
(VBias  VTn ) 2
(VB  VTp )
2
(VBias  VTn ) 2
When V A  VB ,
I DS 6  I DS 7
I DS 3 
I DS 5
2
slide 26
This constraint is same as the
saturation constraint of M4.
6
7
2
3
5
W 
W 
 
 
 L 7
 L 6
2
W 
W 
 
 
 L 4
 L 5
27
Input-referred noise (1)
Channel noise model of MOSFET
Thermal noise Flicker noise
Vn 2 (f)
K p/n 1
g ds
V ( f )  4kT 2 
(V 2 / Hz )
2
g m WLCOX f
2
n
 = 2/3 (Long Channel)
1 (Short Channel)
The channel noise is observed in
the output terminal, but the noise
PSD is normally described as a
input-referred noise PSD.
K p  10 24 (V 2 / F )
K n  10  23 (V 2 / F )
NOTE: Large L is better
for the low noise amplifier,
because of large L*W.
28
Input-referred noise (2)
Intrinsic noise density of the differential amplifier
Thermal noise
Vn2 ( f )  4kT (
Flicker noise
Vn2 ( f ) 
g
1
 m2 3 )
g m1 g m1
(Total noise from M1 and M3)
K p W1 L1 1
Kn

(
1
)
2
K n W3 L3 f
W1 L1COX
NOTE: Assuming that the differential pair consists n-ch MOFET
and current mirror load consists p-ch MOSFETs.
29
Mismatch of MOSFETs by the
process
variation
 V V
V
OS _ 1 2
GS 1
 VTn1 
Vout
GS 2
I DS 5
1
 VTn 2 
 (VTn1  VTn 2 ) 
1
 (VTn1  VTn 2 ) 
2
 VTn1 2 
I DS 5
1
I DS 5
2
[1 
1
]
2
I DS 5 1   2
[
]
1
1
Vin1 – Vin2
VOS

VGS 1  VTn1 

[
]1 2  VTn1 2  OV 1 [
]1 2
1
2
2 1
VOS _ 3 4  VGS 3  VGS 4
VGS 3  VTp 3 


 VTn 3 4 
[
]3 4  VTn 3 4  OV 3 [
]3 4
3
2
2 3
VOS  VTn1 2 
 OV 1 

g

[
]1 2  m 3 [VTn 3 4  OV 3 [
]3 4 ]
2 1
g m1
2 3
30
Optimization for the noise and
process variation
• Thermal noise
– Differential pair MOSFETs: Large W/L
– Current mirror load MOSFETs: Small W/L
• Flicker noise
– Differential pair MOSFETs: Large W*L
– Current mirror load MOSFETs: Large W*L
• Mismatch offset
– Differential pair MOSFETs: Large W, L
– Current mirror load MOSFETs: Small W/L (Small gm3/gm1)
NOTE: Consider that the L and W influences the frequency response too.
31
Design constraints
(1) Phase compensation -1
(4) Maximum common-mode input, Thermal noise
(6) Open loop gain/
Phase compensation
(3) GBP
(5) Minimum common-mode input
(2) Slew Rate
(7) Systematic offset
32
9.4 Design example of a singleend OPA
33
Circuit topology
2 stage OPA without zero-canceling
34
Specification
Power supply voltage
Open loop gain
GBP
Phase margin
Slew rate
Load capacitance
Output voltage swing
Maximum common-mode voltage
Minimum common-mode voltage
Input-referred noise
Power consumption
VDD/VSS
Ad
fu
PM
SR
CL
Voutp-p
Vinmax
Vinmin
vn2
PW
2.5V/-2.5V
> 95dB
100MHz
60°
> 100 V/us
1.0 pF
> 4.2 V
> 2.1 V
< -1.4 V
< 500 uV (BW=1Hz~1MHz)
< 10 mW
35
Parameters of MOSFET
Parameter
VT
[V]
COX [A/V2]

[1/V]
n-ch
0.78
98u
0.0186
p-ch
-0.86
33u
0.0114
The parameters are extracted from 10um/2um MOSFETs for
OV =0.2V.
36
Cc, ISS
(1) Phase compensation -1
Load capacitance
Phase compensation constraint
CL = 1.0 pF
CC  0.2C L
CC = 0.2 pF
(2) SR
SR 
I DS 5
CC
I DS 5  SR  CC  100 MV/s  0.2pF  20 uA
I DS 3  I DS 4  I DS 1  I DS 2 
I DS 5
 10 uA
2
37
M1, M2
(3) GBP
g m1
u 
CC
g m1  CC u  0.2p  2 100 M  126 uS
(2) IDS1 & (3) gm1
W 
g m1  2 1 I DS 1  2  n COX   I DS 1  126 uS
 L 1
2
2
g m1
(126 u )
W  W 

 8.1  10
    
 L 1  L  2 2  n COX I DS 1 2  98u 10u
 OV 
2 I DS 1
1

2 10u
 0.143V
98u 10
38
M3, M4
(4) Maximum common-mode input
Vinmax  VDD   OV 3  VTp  VTn
 OV 3 
3 
2 I DS 3
3
 VDD  VTp  VTn  Vinmax
2 I DS 3
(VDD  VTp  VTn  Vinmax ) 2
2 I DS 3
1
W  W 
    
max 2
 L 3  L  4  p COX (VDD  VTp  VTn  Vin )

2 10u
1
 5.9  6
2
33u (2.5  0.86  0.78  2.1)
39
M5
(5) Minimum common-mode input
Vinmin  VSS  VTn   OV 1   OV 5
 OV 5 
 OV 1 
5 
2 I DS 5
5
2 I DS 1
1
 Vinmin   OV 1  VTn  VSS

2 10u
 0.143V
98u 10
2 I DS 5
(Vinmin   OV 1  VTn  VSS ) 2
2 I DS 5
1
W 
  
min
2
 L 5  n COX (Vin   OV 1  VTn  VSS )
2 10u
1

 6.51  8
2
98u (1.4  0.143  0.78  2.5)
40
M6 (without zero cancellation)
(6) Phase compensation -2
g m 6  10 g m1
 10  2 1 I DS 1
 10  2  98u 10 10u
 1.40mS
Bias condition:

138
I DS 6  6 I DS 4 
10u  230uA
4
6
 OV 6 
2 I DS 6
6

2  230u
 0.318V
33u 138
If VGS 4  VGS 6 ,
I DS 6  6

I DS 4  4
g m 6  2  6 I DS 6
6  g m6
4
2 I DS 4
g m6
W 
  
 L  6  p COX
4
2 I DS 4
1.40m 33u  6
33 10 6 2 10u
 133.48  138

41
M7
(7) Systematic offset (Saturation of M4)
W

1 W   L
W 
    
 L 7 2  L 5  W

L
1 138
 8
 92
2 6


6


4
The circuit parameters
are determined. Check
the other specification.
42
Output swing
min
out
V
 VSS   OV 7
2 I DS 7
 VSS 
W 
 n COX  
 L 7
2  230u
98u  92
 2.5 
 2.27 V
max
 VDD   OV 6
Vout
 VDD 
2 I DS 6
W 
 p COX  
 L 6
2  230u
 2 .5 
33u 138
 2.18　V
Output voltage swing Vout, p-p = 4.45 V
43
Open loop gain
Ad  AV 1  AV 2
 g m1 (rds 2 // rds 4 )  g m 6 (rds 6 // rds 7 )
2 1 I DS1
2  6 I DS 6


I DS1 (n   p ) I D 6 (n   p )
2  98u 10
2  33u 138
10u
230u

(0.0186  0.114) (0.0186  0.0114)
 466  210
 97749  99.8dB
44
Flicker noise (1)
K p W1 L1 1
Kn
2
V 
{
1

}
(
V
/Hz)
2
K n W3 L3 f
W1 L1COX
2
nf
fu
NL2f   Vnf2 df 
fl

COX 
K p W1 L1
Kn
(
1

) ln( f u / f l ) (frequency range　f u ~ f u )
2
K n W3 L3
W1 L1COX
K p W1
Kn
(
1

) ln( f u / f l ) (for L1  L3 )
2
K n W3
W1 L1COX
 0 Si
tOX
 2.5 10 3 F/m 2
The parameter COX can be loosely estimated for nCOX or pCOX.
Say n~ 400 cm2/Vs and p ~ 130 cm2/Vs.
45
Flicker noise (2)
Based on the specification sheet, at fu = 1 MHz, Vnf =
500 V.
(500uV ) 2  NL2f
2.5 10
7
10
10  24


) ln(1 10 6 / 1 10 1 ) V 2
(
1
0
.
1
3 2
W1 L1  (2.5 10 )
6
3.009 10 18

W1 L1
W1 L1  1.203 10 11 m 2
W1
 10 L1
 L1  1.096um
2um
46
Thermal noise
1
8
g
Vnt2  kT (
 m2 3 ) V 2 /Hz
3
g m1 g m1
g
8
1
NL2t  kT (
 m2 3 )f　(frequency range 0 ~ fu )
3
g m1 g m1
g m1  2 1 I D1  2  98u 10 10u  140uS
g m 3  2  3 I D 3  2  33u  6 10u  62.9uS
at T = 300K
8
1
62.9u
NL2t  1.38 10  23  300
(1 
)f　 (500uV) 2
3
140u
140u
Δf　 2.187GHz  1.0MHz
47
Completion
Power consumption Pw = (230 + 3･10)･5.0V = 1.3 mW
48