Unified Power Quality
Conditioner (UPQC) for
Power Distribution Systems
Shyama P. Das
Department of Electrical Engg.
IIT Kanpur
E-mail: spdas@iitk.ac.in
Introduction
Motivation
Design, Simulation and Hardware Implementation of
Unified Power Quality conditioner (UPQC)
(Single phase and Three phase)
Optimum UPQC
Conclusion and Scope of future research
1
Power Quality:
Quality Measure of proper utilization of power by
customers
“Electrical Pollutant” vs “Clean Utility”
Advent of wide spread use of high power high frequency
switching devices
Additional System required to maintain quality
Deregulation, tariff
Power Supply
Authority
Power
Quality
Consumer
2
PCC
Line Impedance
L
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A
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Voltage
Voltage
Polluting Load
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Harmonic Polluting Loads
• Computers
• Computer controlled machine tools
• Photo-copying machines
• Various digital controllers
• Adjustable speed drives
• PLCs
• Uncontrolled or phase controlled rectifiers
.
Some Important Observations of
Power Quality(PQ) Surveys
More low r.m.s. voltage sag occur at the PCC
Majority of voltage sag are 10-20%
More disturbances occur above 70% of nominal line
voltage
The occurrence of most severe sag events are least
frequent.
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PCC
Local
Solution
Load/
Equipment
PCC
OTHER LOADS
Load/
Equipment
Global Solution
(Series/Shunt)
=
5
(a) Providing ‘ride-through’ capability to the
equipment so that they can be protected against
certain amount of voltage sag and swell
(b) Equipment are provided with an arrangement
so that they draw low reactive power and
harmonics
(c) Disadvantage of this approach is that it cannot
take care of existing polluting installations and
further it is not always economical to provide the
above arrangement for each and every equipment
(a) Here independent compensating devices are
installed at PCC so that overall PQ improves at
PCC.
(b) Advantages of this approach are
Individual equipment need not be designed
according to PQ standards
Existing Polluting installations can be taken
care of.
6
#
a)Shunt (parallel) Active Filter (STATCOM)
b) Series Active Filter (DVR)
STATCOM
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STATCOM
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STATCOM Control Strategy
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DVR (Dynamic Voltage Restorer)
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Reactive Power Transfer
Vs2=VL2-2VLVdvr Sin +V dvr2
In-Phase Compensation
11
Phase cum Magnitude Compensation
Load harmonic and VAR compensation
Voltage sag mitigation and unbalanced voltage
correction
Fast dynamic response, and steady state accuracy
12
Unified Power Quality Conditioner
(UPQC)
!
is
Vinj
i_load
Load
Injection
Transformer
Utility supply
Low Pass
Filter
Inverter- I
Inverter- II
ic
LSLC
Cdc
Synchronous
Link Inductor
Inverter-I compensates for sag through a tuned filter and voltage
transformer
Inverter-II (SLCVC) Synchronous Link Converter VAR
Compensator provides VAR to the load, isolates load current
harmonics, makes input power factor unity
SLCVC maintains the charge of the dc link capacitor
(
13
Quadrature Compensation UPQCUPQC-Q
Phasor diagram of UPQC-Q for fundamental power frequency, when θ <Φ
Φ
.
Quadrature Compensation UPQCUPQC-Q
V inj = V s1 2 − V s 2 2
2V inj = mV dc / 2
m = 2 2 . x ( 2 − x ) .V s1
Where, x is p.u. sag
From power balance
Is 2 = Il 2
cos φ
cosθ
m = Modulation Index (max MI=1)
and transformer ratio 1:1
/
14
,45 # %
3 2 :2
Series VA loading of UPQC-Q
1
p.f.=0.25
VA p.u.
0.8
p.f.=0.5
0.6
p.f.=0.6
0.4
p.f.=0.7
p.f.=8
0.2
p.f.=0.9
0
0
0.1
0.2
0.3
0.4
p.u. Sag
0
,45 # %
3 2 :2
Shunt VA loading of UPQC-Q
1.2
p.f.=0.9
VA p.u.
1
p.f.=0.8
0.8
p.f.=0.7
0.6
p.f.=0.6
0.4
p.f.=0.5
0.2
p.f.=0.25
0
0
0.1
0.2
0.3
0.4
p.u. Sag
=
15
$
#,45 # %
3 2 :2
VA p.u.
Combined Loading of UPQC-Q
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
p.f.=0.9
p.f.=0.8
p.f.=0.7
p.f.=0.6
.
p.f.=0.5
p.f.=0.25
0
0.1
0.2
0.3
0.4
p.u. Sag
16
Four Modules
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Vinj
Vs
Peak
Detector
Ckt. Filter
N-L Load
is
Vs_peak
Gate
Drive
Gate
Drive
Hysteresis
Control
is*
SPWM
is
DA1
DA0
is*
DA1
Vdc
Vs_peak
v75
v90
vsec
pwm
modulating
signal ( m3)
DA0
AD0
AD1
PCL-208
AD2
AD3
AD4
[ADC, DAC,
Timer, DIO]
Computer
Fig.3.15 Block diagram of hardware implementation
17
Fig. 3.21 Experimental result of
supply current and load current
X axis : 5 ms/divY axis: 5 A/div
Supply current ( is)
Load current (iL)
Fig. 3.22 Simulation result of
supply and load current
corresponding to Fig. 3.21
X axis = 5 ms/div Y axis =
5 A/div
Relative Percentage
!
120
100
80
60
Fig. 3.23 Load current
(i_load) spectra
(Experimental)
40
20
0
1
5
9
13 17 21 25 29 33 37 41 45 49
Harmonic Number
Fig. 3.24 Supply
current ( is) spectra
(Experimental)
Relative Percentage
120
100
80
60
40
20
0
1
5
9
13 17 21 25 29 33 37 41 45 49
Harmonic Spectrum
(
18
Fig. 3.25
Experimental results
of supply current (is)
and supply current
reference (is*)
X axis : 5 ms/div Y
axis: 10 A/div
Fig. 3.26 Simulation
results of supply
current (is) and
supply current
reference (is*)
X axis : 5 ms/div Y
axis: 10 A/div
.
Fig. 3.27 Experimental result of vL,
vs and vsec
Trace-1: Load voltage (vL)
y axis : 50 v/div
Trace-2: Supply voltage (vs)
y axis : 50 v/div
Trace-3: Series injected voltage
(vsec) /38.
y axis : 1 v/div
x axis : 20ms/div
Load voltage
Source voltage
Injected voltage
Fig. 3.28 Simulation result
of vL, vs and vsec
Trace-1: Load voltage (vL)
y axis : 50v/div
Trace-2: Supply
voltage(vs)
y axis :
50v/div
Trace-3: Series injected
voltage ( vsec) /38.
y axis : 1v/div
/
19
120
Relative Percentage
100
80
60
THD = 3.6%
40
20
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Harmonic Number
Fig. 3.29 Load voltage (vL) spectra
0
Dc link voltage (vdc)
Fig. 3.30 Steady state experimental
results of DC link voltage (Vdc),
supply ( is) and load current ( iL)
X axis : 50ms/div Y axis : vdc
20V/div, is, iL 5A/div
Supply current (is)
Load current (i_load)
Fig. 3.31 Steady state
simulation results of DC
link voltage (Vdc/1000),
supply (is) and load
current ( iL)
X axis : 50 ms/div Y axis :
Vdc .1 V/div, iL = 2 A/div
, is = 10 A/div
=
20
secv
is
3-φ
AC
Source
i_load
3-φ
Nonlinear
Load
ic
Low Pass
Filter
LSLC
Vdc
Series
Compensator
SLCVC
AD0
vdc
Vs_peak
secv_a
AD1
AD2
AD3
AD4
AD5
v90-A
secv_b
v90-B
AD6
secv_c
PCL-726
PCL-208
6 ch-DAC,
DIO
ADC,DAC,
COUNTER
TIMER, DIO
m1-A
DA0
Computer
DAC1 DAC2 DAC3 DAC4 DAC5
DA1
PI-outA PI-outB PI-outC
(m2-A) (m2-B) (m2-C)
m1-B
isa*
isb*
secv_a
Vsa
N
isa
secv_b
Vsb
isb
secv_c
Vsc
isc
3-φ
N-L Load
Peak
Detector
Ckt. Filter
Vs_peak
isa
Gate
Driver
Gate
Driver
Hysteresis
Control
isa*
isb*
isb
isc
isc*
SPWM
5 kHz
m3-( A B C)
21
isa
Fig. 4.20a Experimental results of
supply current and load current of
phase-A
X axis: 50 ms/div, Y axis: 5 A/div
for isa, 2 A /div for i_loada
i_loada
Fig. 4.20b Simulated results of
supply current and load current of
phase-A
Fig. 4.21a Experimental results of
supply current and supply voltage of
phase-A
X axis: 50 ms/div, Y axis: 5A/div for
isa, 20 V/div for vsa
Fig. 4.21b Simulated results of supply
current and supply voltage of phase-A
22
Harmonic
order
Load Current (A-phase)
Supply current ( A-phase)
Magnitude
% fundamental
Magnitude
% fundamental
1st
1.645 A
100
2.652 A
100
5th
313.47 mA
19
38.989 mA
1.46
7th
204.86 mA
12.45
19.43 mA
0.73
11th
113.09 mA
6.87
23.4 mA
0.88
13th
80.05 mA
4.86
10.18 mA
0.38
17th
31.43 mA
1.91
16.68 mA
0.62
19th
28.13 mA
1.71
15.76 mA
0.59
23rd
13.674 mA
0.83
12.3 mA
0.46
25th
9.159 mA
0.5
10.1 mA
0.38
THD
Displacement
Factor
23.28%
2.957%
0.768
0.992
!
sag
Peak of supply voltage (A)
Fig. 4.23a Experimental result of peak of
supply voltage and load voltage of phaseA
X axis: 100 ms/div, Y axis: 50 V/div for
v_loada, 10.48 V/div for Vsa_peak,
Load Voltage (a)
Fig. 4.23b Simulated result of peak of
supply voltage and load voltage of
phase-A
(
23
Fig. 4.24a Experimental result of peak
of supply voltage and supply current of
phase-A
X axis: 100 ms/div, Y axis: 20.96
V/div for Vsa_peak, 2 A/div for
i_loada
Fig. 4.24b Simulated result of peak
of supply voltage and supply
current phase-A
.
Fig. 4.25a Experimental result of peak of
supply voltage and injected voltage and
supply voltage of phase A, X axis: 10
ms/div, Y axis: 10 V/div for secv_a,
50 V/div for vsa, 52.4 V/div for Vsa_peak
Fig. 4.25b Simulated result
of injected voltage and
supply voltage of phase-A
/
24
Fig. 4.26a Experimental result of
peak of supply voltage and injected
voltage and supply voltage of phaseB, X axis: 10 ms/div, Y axis: 50
V/div for vsb, 10 V/div for secv_b,
52.4 V/div for Vsa_peak
Fig. 4.26b Simulated result of
injected voltage and supply
voltage of phase-B
0
Conventional UPQC-P
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VA p.u.
Se rie s VA loading of UPQC-P
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
p.f .=0.25
p.f .=0.5
p.f .=0.6
p.f .=0.7
p.f .=0.8
p.f .=0.9
0
0.1
0.2
0.3
0.4
p.u. Sag
!
26
,45 # %
32 :
Shunt VA loading of UPQC-P
1.2
VA p.u.
1
p.f.=0.9
0.8
p.f.=0.8
0.6
p.f.=0.7
0.4
p.f.=0.6
0.2
p.f.=0.5
0
0
0.2
p.f.=0.25
0.4
p.u. Sag
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32 :
VA p.u.
Combined Loading of UPQC-P
1.4
1.2
1
0.8
0.6
0.4
0.2
0
p.f .=0.9
p.f .=0.8
p.f .=0.7
p.f .=0.6
p.f .=0.5
0
0.2
0.4
p.f .=0.25
p.u. Sag
!
27
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DVR Control Strategy
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Source voltages during normal and sag condition
Sag end
Sag start
Simulation
!0
Results
Load voltages during normal and sag condition
Sag end
Sag start
Simulation
(=
Results
30
Case Study (Optimized UPQC)
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1. UPQC can mitigate voltage sag.
2. Hybrid (combined analog and digital) control
implemented, the control scheme is applicable for
both single phase and three phase.
3. No additional energy storage device required for sag
compensation, long duration sags and under voltages
can also be compensated.
4. Dynamic response is fast.
(
31
5. UPQC can supply VAR to the load.
6. It isolates the load current harmonics from flowing to
the utility.
7. It maintains input unity power factor at all conditions.
8. Optimized UPQC leads to minimum VA loading of the
converters.
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