Microcomputer Speaking:
Pulse Width Modulation
Lecture 20
EE 383
Microcomputers
Learning Objectives
What is PWM?
Which port is used for PWM?
What is the mechanism of PWM?
How to design a PWM signal generation
system?
Pulse Width Modulation
A series of pulses generate a rectangular waveform which
looks something like the following.
Each pulse is characterized by two parameters: period (T)
and duty cycle (D)
T may be any length of time
D may be any value in the range 0 D 1
Pulse width modulation allows for the automatic
generation of a pulse train with specified T and D
D*T
T
Period vs. Frequency
The waveform below has a period specified as “T”.
Periods are measured in units of time per cycle.
An alternative way of specifying the properties of the
waveform is by using frequency, specified as “f ” which is
expressed in cycles per unit of time.
The quantities “T” and “f ” are inversely related:
T = 1/f or f = 1/T
D*T
T
Period and Frequency
Frequency is most often specified in units of Hertz
(Hz) where: 1 Hz = 1 cycle/second
For the Dragon12, the master system clock
frequency is set at 24 MHz = 24000000 Hz =
24000000 cycles/second
The period for one Dragon12 clock cycle (by
T=1/f ) is therefore:
T = 1/(24000000 cycles/second) = 4.1667 * 10-8
seconds/cycle = 41.667 ns/cycle
PWM on the MC9S12DP256B
The MC9S12DP256B contains an 8-bit, 8-channel PWM
system.
The datasheet for the PWM is available on the class
website as S12PWM8B8CV1.pdf
When active, the PWM outputs through Port P
The control registers for the PWM unit are located at
addresses $00A0-$00C7 by default
The Dragon12 port chart shows bits 0-3 of Port P as
controlling the cathodes for the 7-segment digit display.
This leaves bits 4-7 of Port P available for PWM output.
Port P pins 4-7 on the Dragon12 have been brought to a
special set of headers suitable for controlling servo motors.
Port P “Servo” Headers on
Dragon12
MC9S12DG256 Port usage on the Dragon12-Plus board
Assumes factory-default jumper settings
Bit Number
68HC12 Port
A
7
keypad_row_3
6
keypad_row_2
5
keypad_row_1
4
keypad_row_0
B
discrete LED 7 and 7segment DP anode
discrete LED 6 and 7segment G anode
discrete LED 5 and 7segment F anode
discrete LED 4 and 7segment E anode
E
unused
unused
unused
unused
DIP Switch 7
IIC SCL - 24LC16 and
DS1307
J
LCD RW (if jumperenabled)
K
DIP Switch 6
IIC SDA - 24LC16 and
DS1307
DIP Switch 5
unavailable
M CS for SPI0 header (J10)
SPI CS for LTC1661
H
P Servo control header J9 Servo control header J8
SPI0 SS* (routed to SPI0
header)
SPI0 SCK
S
T
AD0
BDM OUT BKGD* or
Pulse Accumulator A
Potentiometer VR2
BDM OUT RESET*
Low Battery Detect for
DS1307 RTC
3
keypad_col_3
discrete LED 3 and 7segment D anode or HBridge control
2
keypad_col_2
discrete LED 2 and 7segment C anode or HBridge control
1
keypad_col_1
discrete LED 1 and 7segment B anode or HBridge control
0
keypad_col_0
discrete LED 0 and 7segment A anode or HBridge control
DIP Switch 4
Opto-Coupler (output)
DIP Switch 3 and
pushbutton 3
Relay (output)
DIP Switch 2 and
pushbutton 2
XIRQ - "Abort" Switch
DIP Switch 0 and
pushbutton 0
unavailable
unavailable
unavailable
unavailable
IRQ
DIP Switch 1 and
pushbutton 1
discrete LED cathode
enable - active low
LCD DB7
CS for FM28256 (if
installed)
Servo control header J7
or Piezo Speaker (if
jumper selected)
LCD DB6
CS for SD Card (if
installed)
LCD DB5
Card Detect for SD Card
(if installed)
LCD DB4
Write Enable for SD
Card (if installed)
LCD E
LCD RS
Servo control header J6
LED Digit 0 cathode
control - active low
RXCAN0
LED Digit 3 cathode
control (active low) or
EN12 for H-Bridge
SPI0 MOSI
SPI0 MISO
SCI1 TX
LED Digit 1 cathode
control - active low
SCI1 RX (device selected
by jumper)
TXCAN0
LED Digit 2 cathode
control (active low) or
EN34for H-Bridge
SCI0 TX
SCI0 RX
Piezo Speaker (if jumper
selected)
Temperature Sensor
(MPC9701A)
alternate IR TX (J27)
Light Sensor
(Phototransistor Q1)
alternate IR RX (J27)
Alarm Trigger 2
Alarm Trigger 1
RS485 DIR control
Rotary Encoder Phase A
Rotary Encoder Phase B or Pulse Accumulator B
Operating System mode Operating System mode
select switch
select switch
Z Axis for Accelerometer Y Axis for Accelerometer X Axis for Accelerometer
AD1
Comments
All MC9S12DP256B port pins directly available from headers surrounding CPU and breadboard.
Port B can be connected/disconnected to/from 7-segment anodes using jumper J24A and to/from discrete LEDs using jumper J24B.
CAN transceiver factory installed for CAN0 (Port M pins 0-1) by default. Transceiver for CAN1 may or may not be not factory installed.
SPI0 factory connected to LTC1661 with Port M pin 6 acting as CS. SPI0 also connected to 10-pin header J10 with Port M pin 7 available for CS.
Jumper J27 switches the IR transmitter/receiver between connection to SCI1 (Port S 2-3) and connection to Port T 3-4
Jumper J23 selects serial device for SCI1 among RS-232, RS-485, IR, and RF
Port T Pin 0 may be connected internally to Pulse Accumulator B. This pin may be used for other purposes but it is recommended to be left available for pulse accumulation.
Port T Pin 7 may be connected internally to Pulse Accumulator A. This pin is used for BDM OUT in POD mode.
Connections in Bold with gray background should not be altered
Solid black boxes indicate no physical connection for these pins
Underlined items are new or modified on the Dragon12Plus compared with the Dragon12
Enabling PWM
The PWM enable register (PWME) is at address
$00A0
Setting a bit in PWME enables the corresponding
PWM output
PWM Pulse Polarity
The PWM polarity register (PWMPOL) is at
address $00A1
The value of the bit in PWMPOL determines the
output value during the duty cycle portion of the
pulse
PWM Clocking
There are four possible PWM clock
generators named A, B, SA, and SB.
The clocks SA and SB are scaled versions of
the clocks A and B
Each PWM channel may select one of the
clocks using the PWM clock select register
PWMCLK ($00A2)
PWM Clocks
Master System Clock
(24MHz on Dragon12plus)
Clock A Scale
20 - 27
PWMPRCLK
Clock SA Scale
2 – 512 (by 2)
PWMSCLA
Clock SA
Clock SB Scale
2 – 512 (by 2)
PWMSCLB
Clock SB
Clock A
Master System Clock
(24MHz on Dragon12plus)
Clock B Scale
20 - 27
PWMPRCLK
Clock B
PWM pins 0,1,4,5 use A/SA and pins 2,3,6,7 use B/SB
PWMCLK
PWM channels 0, 1, 4, and 5 select between clocks A
and SA
PWM channels 2, 3, 6, and 7 select between clocks B
and SB
A zero (0) in the PWMCLK indicates the the channel
uses the standard clock (A or B) and a one (1) in
PWMCLK indicates the scaled clock (SA or SB)
Clock A and B Speed
PWM clocks A and B are based on the main system bus
clock.
Their speed is determined by PWMPRCLK ($00A3)
If the 3-bit scale factor for a clock is called N, the
corresponding clock speed is the main bus clock divided
by 2N. This yields scale factors from 1 (20) to 128 (27).
Clock SA and SB Speed
PWM clocks SA and SB are based on the PWM clocks A
and B.
The speed of SA is determined by PWMSCLA ($00A8)
The speed of SA is equal to the speed of A divided by
(2*PWMSCLA). When PWMSCLA=$00, it is treated as 256
to avoid dividing by 0.
The speed of SB is determined by PWMSCLB ($00A9)
The speed of SB is equal to the speed of B divided by
(2*PWMSCLB). When PWMSCLB=$00, it is treated as 256
to avoid dividing by 0.
Generating a PWM signal (one
channel)
System Clock
Scale Factor
PWMPRCLK
PWMCLK
Period PWMPER
When PWMCNT = PWMPER,
reset PWMCNT to 0
PWM Clock A/B
Clock
MUX
Scale Factor
PWMSCLA/
PWMSCLB
PWM Counter Register
PWMCNT
PWM Clock SA/SB
Duty Cycle PWMDTY
While PWMCNT < PWMDTY
then output = PWMPOL else
output = NOT(PWMPOL)
PWM Period and Duty Cycle
The PWM period registers PWMPER0 ($00B4) to
PWMPER7 ($00BB) determine the number of clock cycles
of the corresponding PWM clock are in the period (T) of
the modulated pulse
The PWM duty cycle registers PWMDTY0 ($00BC) to
PWMDTY7 ($00C3) determine the clock cycle within the
period at which the output changes value.
The PWM counter registers PWMCNT0 ($00AC) to
PWMCNT7 ($00B3) count the clock pulses from the
selected PWM clock to measure the period and duty cycle.
PWM Example 1 part 1
Desired: a waveform with 200 s period and 20% activehigh duty cycle.
The bus clock is 24 MHz (0.04167 s). 200 s
corresponds to 4800 bus cycles. This cannot be counted
with an 8-bit register.
If we scale the clock by a factor of 64 so that each PWM
clock period is 2.667 s, then 1.5ms is 75 PWM clock
cycles.
If the total period is 75 PWM clock cycles, then the 20%
duty cycle corresponds to 15 clock cycles.
For this example, we select PWM channel 4
PWM Example 1 part 3
BSET
BSET
BCLR
MOVB
MOVB
MOVB
PWME, #%00010000
;ENABLE PWM CHANNEL 4
PWMPOL, #%00010000 ;CHANNEL 4 ACTIVE HIGH
PWMCLK, #%00010000 ;CHANNEL 4 CLOCK A
#$06,PWMPRCLK ;PWM CLOCK A SCALE=64
#75,PWMPER4
;CHANNEL 4 PERIOD = 200us
#15,PWMDTY4
;PWM CHANNEL 4 DUTY CYCLE
;IS 15/75 CLOCKS = 20%
PWM Example 2 part 1
Desired: a waveform with 0.2 second period and 15% active-low duty
cycle.
The bus clock is 24 MHz (0.04167 s). 0.2 s corresponds to 4800000
bus cycles. This cannot be counted with an 8-bit register.
If we scale the clock by a factor of 128 so that each PWM clock period is
5.333 s, then 0.2 s is 37500 PWM clock cycles. This is still too large
for an 8-bit counter.
If we use a scaled clock and divide the base PWM clock by 500, then 0.2
s is equal to 75 scaled clock cycles. This is possible.
If the total period is 75 scaled PWM clock cycles, then the 15% duty
cycle corresponds to 11.25 clock cycles. We are restricted to integers
so use 11.
For this example, we select PWM channel 6
PWM Example 2 part 2
BSET
BCLR
BSET
MOVB
MOVB
MOVB
MOVB
PWME, #%01000000
;ENABLE PWM CHANNEL 6
PWMPOL, #%01000000 ;CHANNEL 6 ACTIVE LOW
PWMCLK, #%01000000 ;CHANNEL 6 CLOCK SB
#$70,PWMPRCLK ;PWM CLOCK B SCALE=128
#250,PWMSCLB
;SB=B/(2*250)=B/500
#75,PWMPER6
;PWM CHANNEL 6 PERIOD = 2s
#11,PWMDTY6
;PWM CHANNEL 6 DUTY CYCLE
;IS 11/75 CLOCKS = 14.67%
;(close to 15%)
PWM Example 3 part 1
Desired: a waveform with 50Hz frequency and 10% active-high duty
cycle. (50Hz frequency
1/50 Hz = 20ms period)
The bus clock is 24 MHz (0.04167 s). 20 ms corresponds to 480000
bus cycles. This cannot be counted with an 8-bit register.
If we scale the clock by a factor of 32 so that each PWM clock period
is 1.333 s, then 20 ms is 15000 PWM clock cycles. This is still too
large for an 8-bit counter.
If we use a scaled clock and further divide the base PWM clock by
150, then 20 ms is equal to 100 scaled clock cycles. This is possible.
If the total period is 100 scaled PWM clock cycles, then the 10% duty
cycle corresponds to 10 clock cycles.
For this example, we select PWM channel 6
PWM Example 3 part 2
BSET
BSET
BSET
MOVB
MOVB
MOVB
PWME, #%01000000
;ENABLE PWM CHANNEL 6
PWMPOL, #%01000000 ;CHANNEL 6 ACTIVE HIGH
PWMCLK, #%01000000 ;CHANNEL 6 CLOCK SB
#$50,PWMPRCLK ;PWM CLOCK B SCALE=32
#75,PWMSCLB
;SB=B/(2*75)=B/150
#100,PWMPER6
;PWM CHANNEL 6 PERIOD =
;20ms
MOVB #10,PWMDTY6
;PWM CHANNEL 6 DUTY CYCLE
;IS 10/100 CLOCKS = 10%
Longer PWM Periods
By default, the MC9S12DP256B PWM system is set to
operate as 8 channels with 8-bit counters for period and
duty cycle.
The PWM system also allows for the option of
concatenating pairs of the 8-bit counters into 16-bit
counters.
In this way, the PWM system can be operated with up to
4 channels of 16-bit counters.
The longer counters are useful in cases when long periods
are needed or very small changes in duty cycle are
needed.
PWMCTL
Concatenating PWM channels
The CONxy bits in the PWMCTL register, when
set, cause the specified channels to be
concatenated.
For example, setting CON67 causes PWM
channels 6 and 7 to be concatenated.
The following PWM channels can be
concatenated:
6&7
4&5
Concatenation Details
For each pair of concatenated channels, The evennumbered channel control registers become the high
order byte and the odd numbered channel registers
become the low order byte.
The output is through the odd-numbered channel pin.
The details from the manual for CON01 are shown below.
PWM Example 4 part 1
Desired: a waveform with 20 second period and 1% active-high duty
cycle.
The bus clock is 24 MHz (0.04167 s). 20 s corresponds to
480000000 bus cycles. This cannot be counted with an 8-bit register.
If we scale the clock by a factor of 128 so that each PWM clock period
is 5.333 s, then 2 s is 3750000 PWM clock cycles. This is still too
large for an 8-bit counter.
If we use a scaled clock and divide the base PWM clock by 500, then
2 s is equal to 7500 scaled clock cycles. This is not possible with an
8-bit counter but would be possible with a 16-bit counter.
If the total period is 7500 scaled PWM clock cycles, then the 1% duty
cycle corresponds to 75 clock cycles..
For this example, we concatenate PWM channels 6 & 7
PWM Example 4 part 2
BSET
BSET
BSET
BSET
MOVB
MOVB
MOVW
MOVW
PWMCTL, #%10000000
PWME, #%11000000
PWMPOL, #%11000000
PWMCLK, #%11000000
#$70,PWMPRCLK
#250,PWMSCLB
#7500,PWMPER6
#75,PWMDTY6
;CONCATENATE 6/7
;ENABLE PWM CHANNEL 6/7
;CHANNEL 6/7 ACTIVE HIGH
;CHANNEL 6/7 CLOCK SB
;PWM CLOCK B SCALE=128
;SB=B/(2*250)=B/500
;PWM CHANNEL 6/7 PERIOD=20s
;PWM CHANNEL 6/7 DUTY CYCLE
; IS 75/7500 CLOCKS = 1%