Merits in VLSI Circuits and Design
FUNCTIONALITY
E
CO NERG
NSU
Y
MP
T IO
N
A
ARE
DESIGN
RELIA
BILITY
PER
High speed or throughput;
wide bandwidth; and
low delay, latency, or
response time
NCE
MA
R
FO
PERFORMANCE
ITY
IONAL
T
C
N
U
F
Ability to produce
proper outputs from
given inputs
ENERGY CONSUMPTION
Low power to allow portability and
avoid costly cooling systems
© Maitham Shams 2002
RELIABILITY
Robustness and noise
tolerance in adverse
conditions and
temperatures
AREA
Amount of
Silicon used and
processing cost
Noise in VLSI Circuits
VDD
Noise level increases by
frequency and slope of signals
di
v=L
dt
l In
a
u
t
Mu
ce
n
a
t
duc
ng
i
l
p
Cou itance
ac
Cap
ate
r
t
s
Sub
Ground
© Maitham Shams 2002
Power
Supply
dv
i=C
dt
Voltage Transfer Characteristic (VTC)
V OUT
V OUT
V IN
V OH
Slope = -1
V OUT = V IN
VM
Nominal
Output
Voltage
Levels
Switching Threshold
VM
Slope = -1
V OL
V OH
V OH
V OL
V OL
V IL
V IN
V IH
Maximum Input
Voltage Recognized Low
Minimum Input
Voltage Recognized High
© Maitham Shams 2002
VM
Noise Margins
A measure of circuit robustness and noise tolerance
OUT
IN
Power Supply Level
Noise Margin High
NMH = VOH − VIH
V OH
NMH
UNDEFINED
REGION
Noise Margin Low
NML = VIL − VOL
1
V OL
NM L
0
GND Level
© Maitham Shams 2002
Higher noise margin
means more reliability
V IH
V IL
There is no digital
signal in nature,
WE define a range
of analog signal to
be “1” and another
range to be “0”
Characteristics of an Ideal Logic Gate
V OUT
NMH = NML = VDD / 2
V OH = V DD
Directivity
is a characteristic of logic
gates that ensures signals are
propagated in only one
direction through the gate
dVout
= −∞
dVin
Rout = 0
Rin = ∞
V OL = 0
V IL = V IH =V DD / 2
V DD
V OL
Regenerative property of logic gates
ensures that a faulty signal converges
to a recognizable high or low signal after
passing through a number of gates
© Maitham Shams 2002
This allows for
infinite fan out
by not draining
any current from
the previous gate
This provides ideal
noise margins and
rail to rail output
voltage swing
MOS Transistors As Switches
NMOS PMOS
IN
OUT
OFF
OFF
ON
ON
GOOD GOOD
ON
ON
POOR POOR
© Maitham Shams 2002
IN
OUT
CMOS Inverter
Vin
Vout
VDD
Rail to Rail
Swing
Vout
For Symmetry, PMOS
made large than NMOS
by the ratio of electron
to hole mobility
0
1
OUT
1
0
VDD Vin
IN
0
High R in
Low R
out
© Maitham Shams 2002
Basic CMOS Logic Gates
NAND
NOR
A
A
Z
B
B
Z
A
Z = A• B
B
0
0
1
1
1
1
1
0
Z = A+ B
B
A
Z
A
Z
B
A
A
B
A
B
AND
B
0
0
1
1
0
1
0
0
OR
=
=
In Conventional CMOS Logic Gates only inverted functions of
primary inputs can be made in one stage
© Maitham Shams 2002
Complex CMOS Logic Gates
Scalability
Conventional Topology
Reliability
Fair
Speed &
Power
A
B
A
an
g
or
M
De
it y
l
a
Du
Z = A⋅ (B + C)
= A + (B ⋅ C )
A
B
B
C
= A ⋅ (B + C)
Symmetric respond
obtained by equalizing
pull-up and pull-down
delays
A
B
PMOS
Pull-Up
Network
Z
Dua
lity
Z
DeM
org
an
C
NMOS
Pull-Down
Network
C
Z
C
B
A
When there are more
than one possible case,
engineers design for
the worst case
© Maitham Shams 2002
Delay & Energy
Delay or Response Time
period from receiving an input to
producing the corresponding output
measured at half-swing points
CVDD
D=
2I
OUT
IN
C
Energy dissipation per cycle
Vout
DLH
DHL
Vin
D = ( DHL + DLH ) / 2
of a CMOS inverter is
independent of its size,
but depends on the size
of its load
E = CV
P = CV
2
DD
Dynamic Power consumption
solely indicates energy loss in a
period of time with no regard to
the value of the work
© Maitham Shams 2002
2
DD
f
Design with Equivalent Inverter
Equivalent Inverter
May be used to design a CMOS logic
gate to satisfy a delay requirement
CL VDD
IP =
2 Dr
WP
IN
OUT
WN
CL
≡
All paths in logic gate are sized to
have the same delay (or effective
width) as that of the inverter
D
C
WB = 2 WP
A
WC = WD = 2 WP
B
Z
CL
A
C
C V
I n = L DD
2 Df
WA = WP
B
D
© Maitham Shams 2002
Is there an
alternative
solution
WA = 2 WN
WB = 2 WN
WC = WD = 4 WN
Delay Analysis with Equivalent Inverter
Equivalent Inverter
May be used to estimate rising and
falling delays of a CMOS logic gate
D
C
A
B
Z
A
CL
C
B
D
≡
CL VDD
Dr =
2 IP
WP = min WA ,
OUT
CL
CL VDD
Df =
2 In
WC × WB WD × WB
,
WC + WB WD + WB
IN
WD × WC
W × WB
WD + WC
WN = min A
,
WA + WB W + WD × WC
A
WD + WC
For worst-case delay, transistor sizing
of equivalent inverter is based on the
longest or critical path of the logic gate
© Maitham Shams 2002
WA ×
Best-case delay is based
on all parallel paths being
active simultaneously
Transmission Gate
S=0
X
1
0
S
1
0
1
0
Y
=
X
S
Multiplexer (MUX)
S
B
B
1
S
Y
Y
X
S
S=1
X
1
Y
0
1
0
nts
r ese
rep ent”
TE
TGA tatem
“If s CMOS
in
+
1
X
0
Y
S
If (S == 1) Y=X
Z
If (S == 1) Z=X,
else Z=Y
Z = S • X + S •Y
0
A
A
B
Z
B
S
What logic function is this ...
S
© Maitham Shams 2002
Fan-In and Fan-Out
Delay increases linearly with fan-out
represented by a load capacitance
A
B
Delay increases rapidly with fan-in, if
same transistor sizing is maintained
E
D
C
Z
A
4.0
CL
C
E
F
3.0
Delay (ns)
D
Each additional transistor in
series means additional R and C
Delay may be
maintained
if one doesn’t
mind power
and area
Df
Rule of Thumb is not
to go beyond 4
transistors in series
D
2.0
ic
drat
a
u
Q
1.0
0.0
1
Dr
Linear
2
3
4
© Maitham Shams 2002
5
6
Fan-In
7
8
9
10
Dynamic CMOS Logic Gates
Operation divided
into precharge and
evalauate phases
Relies on load capacitor
to store output data
Z = A ⋅ (B + C)
Φ
Z
Φ
Φ
Z
A
B
C
D
PullDown
Network
A
B
C
D
Φ
B
PullUp
Networ
k
C
A
Z
Φ
Frequency of
operation is only
limited by logic
gate’s critical
pull-down path
Φ
Z
Φ N Style
Number of transistors for N
inputs is N +2 versus 2N for
conventional static CMOS
Φ P Style
Can one cascade
these circuits
A=1, B=1, C=0
Φ
Precharge
© Maitham Shams 2002
Evaluation
Reliability Problems with Dynamic Logic
Charge
Redistribution
Working with dynamic logic gate is tricky
Charge Leakage
Φ
Φ
Φ
Z
A
CL
1
t
Z
Precharge
Evaluate
Z
A
0
0
Φ
t
Due to charge leakage through the reversed-biased
and the transistor (subthreshold current), dynamic
circuits have a minimum clock frequency requirement
CL
B
Φ
One solution is to add
a minimum size PMOS
called bleeder; the
consequence is static
Clock Feedthrough
is another problem with dynamic gates, which could potentially power dissipation
forward bias the junction diodes and cause faulty operation
© Maitham Shams 2002