Basic CMOS Logic Design
Lecture 2
18-322 Fall 2003
Readings: 5.2
Overview
MOSFETs as switches
Ideal switches & boolean operations
CMOS logic gates
Basic/complex functions
Transmission gates
Pass transistors
Ideal Switches
Ideal switches
A=0
Assert-high
x
open
A=1
y
x
A=1
A=0
Assert-low
x
closed
closed
y=x
y
x
open
y
Ideal Switches (cont’d)
b
a
1
a
a ·1
a ·1
1
a
0
(a·1) · b
a· b
+
a ·0
y = a ·1 + a ·0 = a
(well-defined behavior)
MOS Transistor
Gate
Gate
Source
n
Source
Drain
Channel
0
n
p
Gate
Gate
Drain
Substrate
Copyright © by Maly 1997
Channel
VDD
p
n-doped semiconductor substrate
p-doped semiconductor substrate
Source
Drain
Source
Drain
Substrate
Logic Gates Built with Switches
s=0
a
b
a
"1"
b
s=1
a
"1"
"0 "
s=1
"0 "
a
s=0
a
s=1
a
s=1
"1"
"0"
s=0
s=0
"1"
"0"
Logic Gates Built with Switches
VDD
"1"
GND (0 V)
"0"
Floating
"HZ"
Between VDD and GND "X"
VDD
VDD
Out
s
Copyright © by Maly 1997
Out = 0 V
s=1
GND
VDD
Out = VDD
s=0
GND
GND
s
s
Logic Gates Built with Switches
VDD
Out = VDD
s1 = 0
s2 = 0 s1 = 1
GND
VDD
Out = 0 V
VDD
Out = 0 V
Out = 0 V
s2 = 1 s1 = 1
GND
GND
s2
Copyright © by Maly 1997
s1 = 0
s2 = 0
VDD
Out
s1
0
0
1
1
0
1
0
0
s2 = 1
GND
Logic Gates Built with Switches
VDD
VDD
Out = VDD
s1 = 0
Out = VDD
VDD
Out = VDD
Out = 0 V
s1 = 0
s1 = 1
s2 = 0
s2 = 0
GND
GND
Out
s2
0
1
s1
0
1
1
Copyright © by Maly 1997
VDD
1
1
0
s1 = 1
s2 = 1
s2 = 1
GND
GND
Review: NMOS Logic
“NMOS” Logic
VDD
Out = 0 V
s1 = 1
s2 = 1
GND
s2
Out
0
1
0
1
1
1
1
0
s1
NAND Gate
NMOS Logic
Cons:
Output Low consumes power
Pull-up “weaker” than pull-down
Need resistors
Pros:
For X inputs: X NMOS Transistors
Overview
MOSFETs as switches
Ideal switches & boolean operations
CMOS logic gates
Basic/complex functions
Transmission gates
Pass transistors
Review: CMOS Inverter
Out
s2
VDD
s=0
n
p
Out = 1 V
s=0
GND
VDD
s=1
n
p
Out = 0 V
s=1
GND
0
1
0
-
0
1
1
-
s1
s
s
CMOS Logic Design: NAND
s2
Out
0
1
0
1
1
1
1
0
s1
VDD
s1
pmos
VDD
s2
VDD
pmos
A
output
s1
B
out
A
nmos
B
s2
nmos
GND
A
B
out
CMOS Logic Design: NOR
s2
Out
VDD
s1
0
0
1
1
0
1
0
0
s1
pmos
s2
pmos
s1
nmos
GND
s2
nmos
GND
CMOS Logic Design: AND
VDD
s2
Out
s1
0
0
1
0
0
1
0
1
s1
nmos
s2
nmos
output
s1
pmos
s2
GND
DO NOT DO THIS!
THIS IS BAD
pmos
GND
Transistor Rules
NMOS Transistors
Pass 0
Don’t Pass 1 (‘weak’ 1s)
PMOS Transistors
Pass 1
Don’t Pass 0
CMOS Gates
PMOS Pull-up Network (PUN)
NMOS Pull-down Network (PDN)
VDD
PUN
“Dual” Networks
Input(s)
Output
PDN
GND
Inverting Logic
Input transition:
0 -> 1
1 -> 0
Output transition:
1 -> 0
0 -> 1
Input transition 0 -> 1 turns on NMOS
Input transition 1 -> 0 turns on PMOS
Examples: NAND, NOR, INVERT
Complex CMOS Design
F = ~((A + B + C) * D)
~D + ~A~B~C
AB
00
01
11
10
00
1
1
1
1
01
1
0
0
0
C
P
B
P
A
P
D
CD
11
10
0
1
0
1
0
1
D
P
N
0
A
1
CD + BD + AD
D (C + B + A)
N
B
N
C
N
CMOS Logic Gates
Pros:
No static power consumption
Pull-up symmetric with pull-down
No resistors
Cons:
X input gate: 2X transistors
Overview
MOSFETs as switches
Ideal switches & boolean operations
CMOS logic gates
Basic/complex functions
Transmission gates
Pass transistors
Transmission Gates
Static CMOS
Inputs -> transistor gates
Outputs have connection to supply
PUN
Input(s)
Output
PDN
GND
Use transistor to connect input to output?
NMOS Pass Gate
0
1
or
0
1
High-Z
0
0
1
1
Works like a switch
But NMOS doesn’t “pass 1’s”
1 (?)
Passing 1s
VDD
VDD
Vin
VDD - VT
Vout
0V
The NMOS shuts off as out -> VDD
Vout at least VTn less than VDD
0V
Transmission Gates
R(kΩ)
VDD
GND
The Symbol:
Rn
Rp
Req
Vout
Complementary
Inputs
Logic with T-Gates: XOR/XNOR
B
B
A
A
A⊕B
B
A⊕B
B
A
A
B
B
Summary
Discussed
Concepts
⌧MOSFETs as switches
⌧NMOS and CMOS
⌧Transmission gates
Examples
⌧Basic/complex functions using CMOS
More practice
Complex functions (transistor-level diagrams)