Use viciLab to read, rename, upload and configure a
viciLab reference design on remote FPGA
Fearghal Morgan
www.vicilogic.com
Three sections:
Import viciLab Reference Design into User Workspace
Upload viciLab Workspace Design To viciLogic Account
Configure Remote FPGA Prototype and GUI Operation
1. Invoke viciLab
Within the viciLab application folder, double click on the viciLab executable to invoke viciLab
console.
A help utility provides information on the viciLab toolsuite.
2. The viciLab toolsuite download includes completed reference designs (e.g, M21). You can
quickly control and visualise these demo using remote hardware FPGA prototype and Graphical
User Interface (GUI). viciLab also supports the use of a local Digilent Nexys3 Xilinx FPGA module.
This information describes how a user implements existing viciLab reference designs on a local or
remote Field Programmable Gate Array (FPGA). The example used is the 2-to 1 multiplexer
component, M21. For information on the operation of the M21 component, refer to the viciLogic
M21 module.
3. Upload the reference design (e.g, M21 used here) to your viciLogic account to enable remote
FPGA execution.
4. Use viciLab Project>Open saved project (*.vlw)
The folder vicilab/vl_wrap_projects opens by default
5. Select M21.vlw (vlw denotes ‘viciLab wrapper file’). The vlw files records all viciLab user project
build information, user design file locations, and GUI files.
6. Prior to upload of M21 to your viciLogic account, allocate a unique project name for the M21
design using Project>Edit Settings>
e.g, myM21
7. Also, optionally add some descriptive text in the text box and Save.
8. Save the new project. This adopts the newly specified (myM21.vlw) project name.
If you have previously used the project myM21, then select another unique name.
9. Verify that the .vlw contains all of the required information, including the GUI data.
Sometimes, the vlw may have been overwritten with GUI data removed.
If the GUI appears, all is well.
If not, obtain a new copy of M21.vlw from the vici:Lab release (folder
File M21.vlw
)
Upload viciLab Workspace Design To viciLogic Account
1.
2. Enter your viciLogic username and password. Register if required on http://vicilogic.com.
The upload process progresses automatically.
3. Check messages
If successful, the following viciLab message is provided (click ok)
A browser window may also open, indicating the design ID of the project (199 in image below).
If this appears, close this web page, ignore the message and return to the viciLab console.
If the project name is the same as a project name used previously on your viciLogic account,
then you will receive the following message
4. Use Project>Edit Settings> to modify the reference design name to a unique name and re-upload
to your viciLogic account.
5. Save the new viciLab project prior to upload in order that it will be recorded in your vici:Lab
workspace.
Configure Remote FPGA Prototype and GUI Operation
Assumes that the design has been read into the viciLab workspace.
1.
2. Select Remote FPGA option
Checks/reminders of steps to follow are included in the popup menu.
The remote FPGA configuration process proceeds through 3 stages:
3. FPGA signals sel, muxIn1, muxIn0 and muxOut (in this sequence) are connected to four Light
Emitting Diodes (LEDs) on the FPGA hardware module (LED(3:0)). These signals are also
connected to the 4 x 7-segment display components.
When sel is logic ’0’, the data on input muxIn0 is connected to M21 output signal muxOut.
Here, muxIn1 is asserted (i.e, logic ‘1’), so LED(1) turns on and LED(0) (signal muxOut) also turns
on.
Note that the two leftmost 7-segment displays also illustrate muxIn0 and muxOut assertion
(logic ‘1’).
Deasserting muxIn0 and asserting muxIn1, illustrates that only LED(2) and 7-segment display(2)
are turned on. Toggling signal sel toggles LED(3) and 7-segment display(3). LED(0) and 7-segment
display() also toggle illustrating that the state of signal muxIn1 is selected as muxOut.
This presentation demonstrates the M21 Graphical User Interface (GUI), containing the M21
component symbol, input and output signal names, and the prototype GUI control and
visualisation widgets, connected to a remote FPGA hardware operating in real time.
viciLab transfers the state of the prototype GUI input signal widgets to the local or remote FPGA
inputs. The state of FPGA output signals and selected internal FPGA signals is transferred to the
viciLab GUI and reflected in the state of signal widgets.