Soft-Switching in DC-DC Converters:
Principles, Practical Topologies,
Design Techniques, Latest Developments
Raja Ayyanar
Arizona State University
Ned Mohan
University of Minnesota
Eric Persson
International Rectifier
Some of the slides in this presentation are used for the course EE5741 Advanced Power Electronics given by Prof Robbins and Prof Mohan at the University of Minnesota
© 2002, N. Mohan, R. Ayyanar, E. Persson
APEC 2002
1
Objectives
• What is soft-switching?
• Basic principles
• Concentration on a few
popular topologies
• Design techniques
• Computer simulations
• New developments
2
What is Soft-Switching
• Switching transitions occur under favorable
conditions – device voltage or current is zero
• Reduced switching losses, switch stress,
possibly low EMI, easier thermal management
• A must for very high frequency operation,
(also medium frequency at high power levels)
• Usually involves compromises in conduction loss,
switch rating, passive components etc.
4
Relationship Between Efficiency
and Power Density
500
500
450
400
400
η=
350
300
Power Rating
300
∴ Pout
250
Ploss = 20W
200
200
Pout
Pout + Ploss
η
=
Ploss
1−η
150
100
100
Ploss = 10W
50
00
0.8
0 .8
0.82
0.84
0.84
0.86
0.88
0.88
0.9
0.92
0.92
0.94
0.96
0.96
Efficiency
5
Hard-Switching
iL
iT
+
vT
-
Vd
-+
vdiode
+−
iL ≈ Io
vgate
vT
iT
idiode
vdiode
Ploss
Psw ∝ f s ⎡⎣tc( on ) + tc( off ) ⎤⎦
6
MOSFET Characteristics
Output characteristics
Cross-sectional view of an n-channel MOSFET
gate
source
n+
Cgs
p
p
n+
Cgd
Cds
n−
Transfer characteristics
drain-body
depletion layer
n+
drain
7
MOSFET Characteristics
Df
Vin
C gd
Io
( )
iD = f Vgs
RG
VGG
C gs
MOSFET model valid in
active and cutoff regions
Variation of capacitances with Vds
8
Simulation of Hard Switching Converters
L2
40nH
I3
D2
1A
80
R3
1m
V1
R2
Ideal diode
M1
50V
IRF150
25.0
IRF150
0
20
vDS
10
vGS
iD
0
gate
input
-10
0s
V(M1:d)/4
0.5us
ID(M1)*2
1.0us
V(R2:2)
1.5us
V(V3:+)
2.0us
Time
2.5us
3.0us
3.5us
4.0us
9
Simulation of Hard Switching Converters
• Diode reverse recovery
55
PARAMETERS:
R_LOAD = 1
fs = 100k
40
5A
MUR2020R
vds
D5
V1
100
vgs
Io
MUR2020R
R2
ids
M1
10
0
-10
30.0us
30.4us
30.8us
31.2us
-I(R3)
V(M1:1)/2
V(M1:2)
I(I1)
31.6us
32.0us
32.4us
32.8us
33.2us
33.6us
34.0us
Time
38.5
38.5
vds
20.0
ids
vgs
Io
V4
vgs
ids
0
V1 = 0
V2 = 15
TD = 1u
TR = 1n
TF = 1n
PW = 2u
PER = {1/fs}
MTB20N20E
vds
20.0
MTB20N20E
20
Io
0
30.9154us
30.9500us
31.0000us
-I(R3) V(M1:1)/3 V(M1:2) I(I1)
31.0500us
Time
31.1000us 31.1299us
32.95us
33.00us
33.05us
-I(R3) V(M1:1)/3 V(M1:2) I(I1)
33.10us
33.15us
33.20us
33.25us
33.30us 33.34us
Time
10
I1
Problems of Hard-Switching
• Switching losses
• Device stress, thermal management
• EMI due to high di/dt and dv/dt
• Energy loss in stray L and C
Possible Solutions (combination)
• Snubbers to reduce di/dt and dv/dt
Þ usually no change in losses (unless loss recovery)
• Circuit layout to reduce stray inductances
• Gate drive
Þ circuit layout
Þ turn on / off speeds
• Soft switching to achieve ZVS and/or ZCS
11
Snubbers
• Passive components (R, L, C) and a diode to shape
switching trajectories
Turn-on snubber (seldom used)
Þ At turn-on
V
iT (t ) = d t
Ls
• low di/dt
iT
+v
T
-
Vd
Ls
Rs
Io
• lower turn-on losses in the device
• low reverse recovery current
Þ Price to be paid at turn-off
vT
0
iT
0
• 1/2 LI2 energy dissipated during off interval
t
t
• off interval > 2 to 3 times LS/RS time constant
• switch voltage rating increases by RSIO
12
Turn-off Snubbers
RS
iT
+ DS
vT
-
Vd
† At turn-off
iCS
CS
• while vT builds up
iT = Io − iCS
(iC flows through DS )
Io
S
• switch turn-off loss decreases
• lower dv/dt
iT
Io
† Issues at turn-on
CS = 0
00
C S3
C S1
C S2
Vd
C S3 > C S2 > C S1
vT
• 1/2 CV2 energy dissipated in RS and switch
• switch current rating increases by Vd / R S
• ON interval > 2 to 3 times RSCS time constant
13
Soft-Switching
• ZVS (Zero Voltage Switching)
• ZCS (Zero Current Switching)
Advantages
- Lower losses (may be !)
- Low EMI (may be !)
- Allows high frequency operation
14
ZVS (Zero Voltage Switching)
Turn ON
• Switch voltage brought to zero
before gate voltage is applied
• Ideal, zero-loss transition
Turn OFF
• Low-loss transition
• Parallel capacitor as a
loss-less snubber
• Preferred scheme for very high frequency
applications using MOSFETs
15
ZCS (Zero Current Switching)
Turn OFF
• Switch current brought to zero
before gate voltage is removed
• Ideal, zero-loss transition
Turn ON
• Low-loss transition
• Series inductor as a loss-less snubber
• Energy in junction capacitance is lost
Best suited for converters with IGBTs due to
tail current at turn-off
16
ZVS and Hard-Switched Waveforms
Zero-voltage switched
Hard-switched
12V
vdrain − source
vdrain − source
vgate− source
vgate − source
0V
−12V
0V
−12V
17
An Example: Zero Voltage Transition (ZVT)
Synchronous Buck Converter
( 0) = 0
v - ( 0 ) = Vd
C
v
C+
At t = 0 , T + is turned off
C+
T+
Vd
v
C+
i
C+
+v
C-
= Vd
iL
+
D
iL
+
0
A
−
T
−
i
C-
D
−
C
-
L
+
−
Vo
18
Zero Voltage Transition (ZVT)
Since v
C+
Cs
dv
C+
dt
∴ i
C+
T
Vd
+
−
C-
= Vd
C-
+ Cs
+i
Cs+
+
+v
dv
C-
dt
Also, i
C+
=0
∴ i
C+
C-
= -i
C-
= iL
=
iL
2
=0
∴v
=0
v
= Vd
C+
i
C+
C-
iL
D+
-i
Vd
0
A
T−
i
C-
D
−
Cs-
L
+
−
Vo
• At the end of this charge/discharge interval,
positive iL is carried by D −
• Subsequently, T − is turned on; iL must
reverse direction
19
Zero Voltage Transition
vvaA ((tt ))
T
Vd
Cs+
+
+
−
D
Vd
i
C+
iL
+
0
A
T−
i
C-
D
−
Cs-
L
+
−
Vo
t3
t0 t’0 t"0 t1 t1’ t2
Vo
t
iL
0
Conducting T +
Devices
t
D− T −
None
D+
None
T+
None
20
Simulation of a ZVT Buck Converter
PARAMETERS:
R7
PulseWidth = 4.5us
TDLY1 = 5.5us
M1
TDLY2 = 0.5us
V7
25
V1
Period = 10us
L1
IRF150
TD = {TDLY1}
21V
20uH
IC = 2A
R8
V8
25
M2
C2
1000uF
IC = 10V
R6
10.0
IRF150
TD = {TDLY2}
ZVT_buck.opj
0
20
10
gate
input
vDS
vGS
iL
0
iD
-10
-20
9us
V(M2:d)/2
10us
ID(M2)*2
11us
V(M2:g)
12us
I(L1)*2
V(V8:+)
13us
Time
14us
15us
16us
17us
21
Classification of
Soft-Switching Schemes
• Load Resonant Converters
• Converters with Resonant Switches (Quasiresonant, Multi-resonant)
• Resonant Transition Converters
– ZVT and ZCT
22
Phase Shift Controlled
Full-Bridge Converter (ZVT)
† Makes use of switch capacitances and transformer
leakage inductance and magnetizing current
TB+
TA+
Vd
+
D a+
A
a
−
TA−
TB−
B
D
−
a
D +b
Io
b
D −b
• Poles A & B switched at nearly 50% duty-cycle
• Output voltage regulation is achieved by phase
modulating the two pole outputs
47
Switching waveforms
vA
+
Vd +
2 −
ficticious Vin
0
Vd +
2 −
+
DA
+
A
T
D B+
+
B
T
vB
D a+
LlT
A
D −A
−
A
T
−
+
iAB
−
B
T
−
B
iL
v AB
vAB
D +b
a
Io
b
D −b
D a−
iAB
D B−
t
In pole A
T − to T
A+
⇒ v AB =0
A−
⇒ v AB =0
A
T
A+
to T
+Vd
In pole B
T − to T
B
-Vd
T
B+
B+
to T
B−
⇒ v AB = +Vd
⇒ v AB = -Vd
0
0
48
Transitions - Pole B
TB− to TB+
TB+
TA+
Vd
+
−
v AB
TB- to TB+
iAB
+
iL D a
a
A
B
Io
t
b
D −b
TB−
TB+ to TB-
• v AB = +Vd
• iL stays at I o
0
• v AB = -Vd
0
• iL stays at - I o
49
Transitions - Pole A
TB+
TA+
Vd
+
+
D
a
iL
v AB
Io
a
−
A
B
TA−
T
A+
to T
A−
⇒ v AB = 0
iAB
TA + to TA-
b
D −b
t
-Vd
• All four diodes conduct
• Leakage inductance resonates with switch capacitance
• Determination of Tdel critical for ZVS design
• Load dependent ZVS
50
Methods to increase ZVS range
• Use of external series inductor
+
Lo
iAB
Vin
A L
series
−
B
vrect
Vo
−
−
Disadvantages
† Loss of volt-sec
vAB
0
+
+
iAB
higher turns-ratio
higher
conduction loss
vrect
increased
VA ratings
† Load dependent ZVS
left-leg
51
Use of magnetizing current
+
i load + i mag
Vin
A
i mag
B
Disadvantages
† higher conduction loss due to
−
vAB
i mag
• peak circulating current
• current through right-leg
MOSFETs
• peak magnetizing current
independent of Vin
2
left − leg
52
Factors Affecting ZVS
™ ZVS Load Range
™ Capacitance across MOSFETs
– internal and external
™ Leakage inductance
™ Delay time
™ Magnetizing current
ƒ Design of other parameters like Lo, Co, transformer etc
identical to hard switched PWM
53
Designing for ZVS
MOSFET voltage during critical
turn-on transition
(
vds = Vin − I mag _ pk + I refl
ω=
)
Leq
2 Cds
vds
sin (ω t )
1
2π Leq Cds
π
2
t
LLk 2Cds
Conditions for ZVS
1.
( I mag _ pk + I refl )
2. Tdelay =
π
2
Leq
2 Cds
≥ Vin,max
Leq .2 Cds
54
Designing for ZVS
A Possible Design Approach Using MathCAD
• Sweep for all practical values of
Cds - based on limiting voltage rise during turn-off
Tdelay - as a percentage of switching period
• Calculate required Imag,pk and Llk for each set
• Calculate switch peak current and RMS current
Turn-off loss
Conduction loss
• Calculate total losses. Iterate for different ZVS ranges
55
Designing for ZVS
Total
Losses
(W)
j
i
j ⇒ Cds
i ⇒ Tdel
Total_loss
56