A Constant Frequency Resonant Transition Converter
A Thesis
Submitted for the Degree of
M.Sc. (Engg)
In the Faculty of Engineering
By
A. Rajapandian
Department of Electrical Engineering
Indian Institute of Science
Bangalore 560012
August 1995
ACKNOWLEDGEMENTS
I am grateful to Dr. V. Ramanarayanan, for giving me an opportunity to work on a
problem that was challenging and practically relevant, and for providing me with all the
needed facilities. I have learnt much from him and consider myself fortunate to have had the
opportunity to work with him.
I thank Dr. V. T. Ranganathan for the many useful discussions we have had.
I thank the Management and Staff of M/s. Electrohms Pvt. Ltd., Bangalore, for
sponsoring this project and for the support provided through each stage of its development. The
fabrication and a major part of the testing of the converter described in this report, were done
at their premises.
I thank Mr. Maruthi Shah for the neat photographs.
Finally, I wish to express my thanks and appreciation to my friends and members of the
Power Electronics Group for their help and support and for the pleasure of their company.
ABSTRACT
Switched Mode Power Supplies [SMPS], have become the natural choice for most of
the power supply problems, owing to their higher efficiency and increased power density.
Most of the present commercial SMPS, operate with a switching frequency of around 50 kHz,
using Hard Switching PWM topologies [1, 2]. Power densities of these SMPS, can be
increased manifold, if the switching frequencies are increased. Hence the technology is
evolving towards switching frequencies of the order of a few MHz. In the Hard switching
PWM topologies, the switching losses increase proportionately with the frequency, and hence
they are not practical at these frequencies.
This thesis, explains the mechanism of switching losses in the hard switched topologies
and briefly reviews the various Soft switching topologies that have been proposed to address
the problems of switching losses. In particular, the Resonant Load converters [3, 4] and
Resonant Switch [5, 6] converters are discussed, with respect to the mechanism of soft
switching and the cost associated with it, namely the higher switch stress, higher conduction
losses and variable frequency operation. Resonant Transition Converters [7] are introduced as
the next logical step in the evolution, as they combine the low switching loss characteristics of
Resonant converters and the low conduction loss and constant frequency characteristics of the
PWM converters.
The Phase Modulated Full Bridge Converter [PMC], which belongs to the class of
Resonant Transition Converters, is chosen for study and implementation. Its distinguishing
features are Zero Voltage Switching [ZVS] and constant frequency operation. The basic
principles involved in the operation of PMC are explained. A detailed analysis of a complete
cycle of operation is done by identifying the various distinct intervals, and establishing the
equivalent circuits and governing equations valid in each of them [9]. With these equations, the
operation of PMC is numerically simulated, using commercially available software packages.
The various parameters affecting ZVS are discussed and design equations to obtain
suitable values for these parameters, are derived. With these values as the initial estimates,
simulation is used iteratively, to obtain the most satisfactory design parameters. The many
trade-offs involved in the design are highlighted [10].
ii
The design and development of an off-line SMPS of 560 W rating (28V / 20A),
switching at 250 kHz, and based on the Phase Modulation controller IC - ML 4818 [20], are
discussed in detail. The experimental results are presented and are shown to match well with
those predicted by analysis and simulation. From the results, it is concluded that the Phase
Modulated full bridge Converter, is well suited for high power and high voltage applications
requiring high power densities.
iii
CONTENTS
CHAPTER 1
CHAPTER 2
CHAPTER 3
ACKNOWLEDGEMENTS
i
ABSTRACT
ii
INTRODUCTION
1
1.1 High Frequency Switching
1.2 Soft Switching
1.3 Resonant Converters
1.3.1 Resonant Load Converters
1.3.2 Resonant Switch Converters
1.3.3 Limitations of Resonant Converters
1.4 Resonant Transition Converters
1.5 Organization of the Report
1
4
5
5
7
9
9
10
BASIC PRINCIPLE OF OPERATION
11
2.1 ZVS By 50% Duty Ratio
2.2 Regulation By Phase Modulation
2.3 Analysis of a Complete Cycle of Operation
2.3.1 Positive Power Transfer Interval
2.3.2 Transition from Power Transfer
to Freewheeling Mode
2.3.3 Freewheeling Interval
2.3.4 Transition from Freewheeling
to Power Transfer Mode
2.3.5 Rectifier Intervals
11
12
13
14
15
DESIGNING FOR ZVS
23
3.1 Two Different Types of Transitions
3.2 Factors Affecting ZVS
3.2.1 Magnetizing Current
3.2.2 Leakage Inductance
3.2.3 Dead Time
3.2.4 Mosfet Output Capacitance
3.3 Design Strategy to Achieve ZVS
3.4 ZVS LIMIT
23
24
24
24
25
26
27
28
17
18
21
CHAPTER 4
CHAPTER 5
CHAPTER 6
CHAPTER 7
DESIGN AND DEVELOPMENT OF
A 250 kHz / 560 W CONVERTER
30
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
30
32
33
33
34
36
36
38
Specifications
Choosing the ZVS LIMIT
Design of Power Transformer and the Primary Inductors
Design of Filter Components
Semiconductor Selection and Thermal Design
Control Circuit
Dynamic Model and Compensator Design
Drive Circuit
SIMULATION AND EXPERIMENTAL RESULTS
39
5.1
5.2
5.3
5.4
5.5
5.6
39
40
41
44
45
45
Regulation by Phase Modulation
ZVS and Non-ZVS Turn-On Transitions
ZVS LIMIT and Mosfet Losses
Currents Through Left Leg and Right Leg Mosfets
Turn-Off Transition
Power Density
LIMITATIONS OF PMC AND SOME MODIFIED SCHEMES
46
6.1 Limitations of PMC
6.2 Schemes Extending the ZVS Range
6.2.1 Effective Use of Magnetizing Energy
6.2.2 Secondary Side Magamp Control
6.2.3 Modified Rectifier Configuration
6.3 PMC with Primary Side Clamp Diodes
46
47
47
48
50
51
CONCLUSIONS
52
REFERENCES
56
APPENDIX 1
58
CHAPTER 1
INTRODUCTION
Switched Mode Power Supplies [SMPS], with their higher efficiency and reduced size,
have almost totally replaced the traditional linear regulated power supplies. Significant
progress in the fields of circuit topologies, semiconductor power devices, control theory and
integrated circuits, have made the switch mode power supplies, with typical switching
frequencies of about 20 - 100 kHz, a mature technology [1, 2].
However, the recent remarkable advances in Integrated Electronics, have greatly
reduced the size of many electronic systems, and in order to fully utilize the advantages of
denser electronics, power densities (output power per unit volume) that are much higher than
what is possible with present SMPS technology, are being demanded. Computers, automotive
and telecommunication systems are a few examples, where the power supply has already
become the critical component, owing to its size.
It is well recognised that higher power densities are possible with higher switching
frequencies. Since the size of the main components in SMPS, like the power transformer and
energy storage elements, depend strongly on the switching frequency, significant savings in size
is possible at high frequencies. Hence the technology is evolving towards switching
frequencies in the order of a few MHz.
1. 1 HIGH FREQUENCY SWITCHING
'Frequency goes up, size comes down', is a belief that has been the main motivating
factor for switching at high frequencies. Up to frequencies of about 200 kHz, this relationship
between frequency and size is approximately true. Beyond this frequency, however, phenomena
not previously important, become significant, and size may very well begin to increase if these
are not taken care of. The most significant of these problems are the pronounced increase in the
switching losses and the adverse effect of the parasitic elements like the stray inductance of the
circuit and the junction capacitance of the devices.
In the Pulse Width Modulated [PWM], square wave converters widely employed at
present [1, 11], the power devices are required to turn on and turn off the entire load currents,
1
abruptly, during each switching. High device voltage and current, overlap during these
switching transitions, resulting in high switching loss and device stress.
Figure 1.1a shows the equivalent of the typical switching conditions encountered in
most PWM converters. The resulting switching waveforms along with the associated losses are
shown in Fig. 1.1b.
Vs
Vi n
Vi n
D
Is
I
I
Is
Conduction
S
(a)
loss
Turn-o ff
loss
Turn-o n
loss
(b)
Fig. 1.1 Switching transitions in PWM converters.
(a) Equivalent Circuit (b) Switching waveforms
As seen in the figure, during turn-off, the moment the current begins to fall, the voltage across
the switch rises to the maximum (since the freewheeling diode begins to conduct). During the
turn-on process too, the device voltage remains at its peak (again due to the conduction of
freewheeling diode), till the current rises to its maximum value. Hence, high device voltage
and current overlap during both the transitions resulting in significant losses.
The switching losses increase linearly with frequency, since switching transitions occur
more frequently in a given time. Even if the loss of efficiency, due to these losses, is not a
prime concern, the effect of these losses on the physical size is a major cause of concern. At
some point, the reduction in size gained by raising the frequency is more than offset by the
required increase in the heatsink volume.
The presence of the parasitic elements like the stray inductance of the circuit and the
junction capacitance of the semiconductor devices, force the devices to experience voltage
spikes during turn-off and current spikes during turn-on. Figure 1.2 shows the condition with
the parasitic components added. As seen in Fig 1.2b., during turn-off, the sharp fall of current
through the stray inductance results in high voltage spikes across the device. This problem
2
becomes severe at high switching frequencies, since the turn-off is made faster with a view to
reduce the switching loss.
Lp
Vi n
D
I
VS
IS
Turn-On
Turn-On
Turn-Off
S
Cp
Turn-Off
IS
Vdrive
VS
(a)
(b)
(c)
Fig. 1.2 Effects of Parasitic Elements during switching transients.
(a) Equivalent Circuit (b) Switching waveforms (c) Switching Loci
Similarly, the parasitic capacitance which comprises chiefly of the junction capacitance
of the switches, causes severe current spikes during turn-on. The reverse recovery
characteristics of the freewheeling diode also contributes to the current spike. Figure 1.2c,
shows the switching loci with all the parasitics considered. Because a large switch voltage and
switch current occur simultaneously, the switch must be capable of withstanding high switching
stress, with a large safe operating area (SOA). This requirement, demands over-designing of
the power semiconductor devices.
Apart from the device stress, the loss of energy trapped in these parasitic elements is
also a significant factor at high frequencies. In fact, for high voltage applications, using Mosfet
switches (the only practical switch at the frequencies of interest), the energy loss associated
with the junction capacitance, is the largest source of switching loss.
The losses in the drive circuit, which are usually negligible in the 50 kHz range,
become significant at higher frequencies. Apart from the loss, the increased power rating
needed for the drive circuit, makes the task of achieving higher power density difficult.
Another serious drawback of switched mode converters, is the Electro Magnetic
Interference [EMI] produced by the large di/dt and dv/dt during the switching transitions. At
higher switching frequencies, this problem becomes more severe. The EMI filters required to
meet the stringent EMI specifications, demand a substantial space of the power supply.
3
1. 2 SOFT SWITCHING
The promise of high power densities through high frequency switching, can be realised
only if the associated problems like the switching losses, switch stress and EMI, are overcome.
Snubber circuits [11], are effective, to a limited extent, in reducing the device stress during
switching transitions. However, they do not appreciably reduce the switching losses, as they
only shift the power loss from the switches to the snubber resistors.
With a combination of proper converter topologies and switching strategies, the major
problems of high frequency switching discussed so far, can be overcome. In order to achieve
this, a converter topology should have the following two features.
Switch transitions should occur only when either the device current and / or the device
voltage is zero
The energy stored in the parasitic elements are fully recovered.
The converter circuits that satisfy these conditions are known as Soft Switching
Converters. They can be broadly classified as Zero Current Switching [ZCS] converters and
Zero Voltage Switching [ZVS] converters.
In the ZCS converters, the current through the device is brought to zero by external
means (for example by LC resonance in resonant converters), just prior to turn-off. Thus the
turn-off losses as well as the voltage spikes due to stray inductance are totally eliminated.
During the turn-on process, the current rise is slowed down, again by external means, so that
the device voltage falls to zero before the current becomes appreciable. Figure 1.3a shows the
switching loci corresponding to the ZCS converters. As seen, the turn-off process (I-A1-A2-V)
is totally lossless and the turn-on (V-B1-B2-I) occurs with reduced losses.
I
I
A1
B2
A1
B2
A2
A2
B1
V
V
B1
(a)
(b)
Fig. 1.3. Switching Loci for Soft Switching Converter (a) ZCS (b) ZVS
4
In the ZVS converters, as shown in Fig. 1.3b, the device voltage is brought to zero just
prior to turn-on, thus totally eliminating the turn-on losses. During turn-off, the rate of voltage
rise is limited, so that the device current falls to zero before the voltage rises substantially.
1. 3 RESONANT CONVERTERS
Resonant converters achieve soft switching by suitably adding resonating LC tank
circuits to the original PWM topologies. The device current and / or the voltage is thus made
near sinusoidal. ZCS / ZVS is achieved by switching at the natural zero crossing of these
sinusoidal currents / voltages.
Resonant Converters, as applied to SMPS, are broadly classified as,
1. Resonant Load Converters
2. Resonant Switch Converters or Quasi-Resonant Converters.
1. 3. 1 Resonant Load Converters
In the resonant load converters, extra inductor and capacitor are added suitably to the
load, to form an under-damped RLC series resonant circuit. The current through the devices is
made approximately sinusoidal. Power flow to the load is controlled by the resonant tank
impedance, which in turn is controlled by the switching frequency in comparison to the LC
resonant frequency. Figure 1.4 shows the two main types of Load Resonant converters - the
Series Loaded Resonant [SLR] converters and the Parallel Loaded Resonant [PLR] converters,
obtained from the PWM half bridge topology.
Vdc
Vdc
D1
D1
Vo
S1
Vo
S1
Lr
Cr
Lr
Cr
D2
D2
S2
S2
(a)
Fig. 1.4 Load Resonant Converters
(b)
(a) Series Loaded
5
(b) Parallel Loaded
In both these converters, operation below resonance (i.e. with the switching frequency
less than the LC resonant frequency), results in Zero Current Switching. Figure 1.5a shows the
current and voltage waveforms of the switch S1 of Fig. 1.4a, corresponding the ZCS mode. As
seen, the switch turns off naturally at zero current (point A), as the inductor current through it
goes to zero and reverses through the freewheeling diode. During turn-on, however, the device
turns on with a finite current (point B). External series inductors may be added to limit the
switch current rise before the voltage falls to zero. The energy stored in this inductor is fed
back to the load before the next turn-off transition.
VS
1
VS
1
B
ID
IS
1
I S1
1
A
ID
1
IS
IS
2
2
S 2 Off
S1drive
(a)
C
S 1drive
(b)
Fig. 1.5 Waveforms of the Series Loaded Resonant Converter
(a) Operation Below Resonance (ZCS)
(b) Operation Above Resonance (ZVS)
Operation above resonance - i.e., the switching frequency is more than the resonant
frequency, results in ZVS. Figure 1.5b, shows the corresponding waveforms. As S2 is turned
off, the inductor current initially flowing through it is forced to flow through the diode D1, thus
bringing the voltage across S1 to zero. S1 is turned on at this instant (before point C), thus
achieving ZVS. The turn-off process is not totally lossless, as the switch is turned off with a
definite current. However, this loss can be reduced by adding extra snubber capacitance across
the switch, which limits the voltage rise, while the current is falling. The energy stored in this
capacitor is not lost but is fed back to the load / source before the next turn-on.
A detailed discussion and analysis of series resonant converters is given in reference
[12] and that of parallel resonant converters in [13]. Small signal stability considerations of the
resonant load converters are discussed in [14]. Various combinations of the basic series and
6
parallel resonant converters have been developed. The LCC type series-parallel resonant
converter discussed in [15], combines the favourable features of both the series and parallel
converters.
1. 3. 2 Resonant Switch Converters
The Resonant Switch Converters are obtained by simply replacing the controllable
switch(es) in PWM converters, with the Resonant Switch. The Resonant Switch is a subcircuit
consisting of semiconductor switches and resonant LC elements. The resonant elements shape
the device current / voltage waveforms, so that the switchings can be done under favourable
conditions. Depending on the arrangement of the resonant elements with respect to the
switches, either ZCS or ZVS conditions can be created for the switches. The basic resonant
switches are shown in Fig. 1.6.
Cr
Cr
Lr
S
Lr
S
(b)
(a)
Fig. 1.6. Basic Resonant Switches
(a) ZCS (b) ZVS
In the ZCS resonant switches, the resonant inductor is in series with the active switch.
Figure 1.7 shows the ZCS switch applied to a buck topology and the corresponding switch
waveforms. At turn-on, the rate of rise of the switch current is limited by the inductor L r The
current rises linearly till it reaches I o (point A), at which point the freewheeling diode
switches off. The inductor L r now resonates with the capacitor C r , making the switch current
sinusoidal. At point A, the switch current, which is the sum of the resonant current and the load
current, goes through its natural zero resulting in lossless turn-off.
Half-wave mode or full-wave mode operations are obtained, depending on whether S1,
is implemented by an unidirectional or bi-directional switch. Both these modes are fully
analysed in [5]. For full wave mode operation, the DC voltage conversion ratio and the small
signal transfer functions are similar to the PWM buck converter [6].
7
IS
Cr
Lr
S
Vd
Io
Lo
Io
Co
+
_
A
R
VS
Vdrive
(b)
(a)
Fig. 1.7 ZCS Resonant Switch Buck Converter
(a) Circuit Diagram (b) Switch Waveforms
The ZVS resonant switch converter is just the dual of the ZCS converter. The resonant
network shapes the voltage across the switch for Zero Voltage turn-on. Figure 1.8 shows the
ZVS resonant switch buck topology and the corresponding waveforms, for half-wave mode
operation. Detailed analysis of ZVS resonant switches can be found in [16].
IS
Cr
S
Vd
+
_
Lr
ID
Lo
VS
Co
D
R
Vdrive
(b)
(a)
Fig. 1.8 ZVS Resonant Switch Converter
(a) Circuit Diagram(b) Switch Waveforms
Above 1 MHz, ZVS topologies are preferred over the ZCS topologies, because they
eliminate the loss associated with the junction capacitance of the Mosfets, which is the most
significant loss at those frequencies. The demand on the reverse recovery characteristics of the
diode is also not as severe as in the case of Non-ZVS converters. In most cases the body diode
of the Mosfet (which has relatively poor reverse recovery characteristics) itself
satisfactory.
is
Multi-resonant switch converters provide favourable switching conditions for
the active switches as well as the diodes, and are discussed in detail in [17].
8
1. 3. 3 Limitations of Resonant Converters
The major drawbacks of the Resonant Converters are,
the ratio of installed VA to the output power in resonant converters is high, typically
around 4 to 5, due to extra resonant elements.
the peak current stress in the ZCS and the peak voltage stress in the ZVS converters are
much larger than the corresponding PWM topologies. The peak current in the ZCS
resonant switch converter is more by a factor of Vin
L C and the peak voltage stress
in ZVS resonant switch converters increases by a factor of I o . L C .
since the currents through the devices are near sinusoidal, the peak and rms. values of
these currents are larger compared to corresponding PWM topology. Hence conduction
losses are increased significantly. In ZVS resonant switch converters, the higher voltage
stress demands switches with high voltage rating which have higher RDS ON, contributing
to increased conduction loss.
a major disadvantage of resonant converters is the variable frequency operation. The
resonant converters achieve output control by varying the switching frequency [6]. The
disadvantages of variable frequency operation are,
sub-optimal utilisation of the output filter components. Whereas, the power devices,
drive circuit, magnetic core materials etc. have to be designed for the highest operating
frequency, the values of the output filter components have to correspond to the lowest
frequency. Hence the advantages of the high frequency switching are not fully utilised.
the variable frequency operation makes the design of EMI filters difficult.
the frequency control methods are not as well studied, documented and supported as
the duty ratio control, employed in PWM converters.
1. 4 RESONANT TRANSITION CONVERTERS
The Resonant Transition Converters, being proposed recently [7], combine the low
switching loss characteristics of the resonant converters and the constant frequency and low
conduction loss characteristics of the PWM converters. They are essentially square wave
converters for the most part, except during the resonant transitions. The resonant transitions are
achieved, relying mainly on the parasitic inductances and capacitances, and by adopting
suitable switching strategies.
The Phase Modulated Full Bridge Converter [PMC], which has been chosen for study
and implementation in this work, belongs to the class of resonant transition converters. Some of
the salient features of PMC are as follows.
9
Zero Voltage Switching for all the four Mosfets of the full bridge.
Constant frequency operation.
Soft switching is obtained relying mainly on the parasitic elements, like the magnetizing
and leakage inductance of transformer and the junction capacitance of the Mosfets. Hence
the ratio of output power to installed VA, is higher than the Load resonant or the the
resonant switch converters.
Phase shift control (explained in detail in Chapter 2) used in PMC, is identical to the
duty ratio control used in PWM converters. The small signal dynamic model of PMC
also is similar to that of the PWM full bridge converter. Dedicated control ICs are
available.
1. 5 ORGANIZATION OF THE REPORT
The basic principles of operation of the Phase Modulated Converter are discussed in
Chapter 2. The conditions to achieve ZVS, and the concept of phase shift control are explained.
Analysis of a complete cycle of operation is done by identifying the various distinct intervals,
and establishing the equivalent circuits and governing equations valid in each of them. With
these equations, the operation of PMC is numerically simulated and some of the simulated
waveforms are presented.
In Chapter 3, the various parameters affecting ZVS are studied, and design equations to
achieve ZVS are established. The concept of ZVS LIMIT is introduced. The various trade-offs
involved in the design, and the use of simulation in the design process are discussed.
In Chapter 4, the design and development of an Off-line 250 kHz / 560 W, Phase
Modulated Converter are discussed in detail. Step by step design procedures for the major
components, like transformer, filter components, control and drive circuits etc. are presented.
Experimental results obtained on the developed converter are presented in detail, in
Chapter 5. The results are compared with those predicted from simulation and analysis.
In Chapter 6, some of the drawbacks of the PMC are indicated, and a few modified
schemes of the basic PMC topology, which address these problems, are discussed.
In Chapter 7, on the basis of experimental and simulation results, it is concluded that the
Phase Modulated Converter, is well suited for high power and high voltage applications
requiring high power densities.
10
CHAPTER 2
BASIC PRINCIPLE OF OPERATION OF PMC
The main feature of the Phase Modulated Converter [PMC], as mentioned in Chapter 1
is the Zero Voltage Switching [ZVS]. In this chapter, the mechanism by which ZVS is achieved
in PMC is explained. The meaning and significance of Phase Modulation are discussed. The
various intervals in a complete cycle of operation are identified and the equivalent circuits and
the governing equations valid in each of them are derived. With these equations the converter is
simulated and some of the simulated waveforms are presented.
2. 1 ZVS BY 50% DUTY RATIO
ZVS means that the voltage across a switch is brought to zero by some means, before it
is switched on. In any double ended converter like the push-pull, half bridge and the full
bridge, it is possible to achieve ZVS, if the duty ratio is fixed at 50%. This is explained for the
case of a half bridge converter, shown in Fig. 2.1.
Consider S2 conducting initially, resulting
in the current I L as shown. As S2 is switched off,
the inductive nature of the load forces I L to
Vin
continue to flow in the same direction, but now
completing the path through D1 and C1 . Since D1
C1
D1
S1
is conducting, the voltage across the switch S1 is
IL
zero. Hence, turning on S 1 now, results in ZVS.
A
B
The duration for which D1 conducts depends on
the nature of the load and the energy stored in it.
Hence to reliably turn on S1 with zero volts across
C2
S2
D2
it, it is necessary that it is switched on after S2 is
switched off and while D
1
is conducting.
Similarly S2 should be turned on after S1 is turned
off and D2 is conducting. In a symmetrical half
bridge converter, this implies operating with fixed
duty ratio of 50%.
11
Fig. 2.1 Half Bridge Converter
The PWM converters control the output by varying the duty ratio. If the duty ratio is
fixed at 50%, with the aim of achieving ZVS, output regulation is not possible. Therefore
alternative methods have to be employed, to control the output. For the full bridge topology,
Phase Modulation is one such alternative.
2. 2 REGULATION BY PHASE MODULATION
The concept of Phase modulation in full bridge converters is explained with the help of
Fig. 2.2 below. Figure 2.2a, shows the simplified schematic of the full bridge converter. Each
S S2
3
VDC
Φ
S 1 S4
S3
S1
VA
IL
B
A
V
B
S2
S4
VAB
o
Phase Difference = 90
o
Phase Difference =180
(a)
(b)
Fig. 2.2 a) Schematic of Phase Modulated Converter.
b) Waveforms corresponding to different Phase Differences.
of the four switches (S1 to S4) is operated at 50% duty ratio. Hence the waveforms at points A
and B are square waves with 50% duty ratio as shown. Phase Modulation refers to varying the
phase difference Φ between these two square waves, i.e., between VA and VB , to achieve
output control. A phase difference of 1800 corresponds to the maximum output voltage. As the
phase difference is reduced, the output reduces proportionately. Figure 2.2 b. shows the output
for a phase difference of 900 and 1800.
12
2. 3 ANALYSIS OF A COMPLETE CYCLE OF OPERATION
The basic principle of PMC has been explained in the previous sections, assuming all
the components to be ideal. However, as mentioned earlier, PMC relies mainly on the
parasitic elements of the transformer and the Mosfets to achieve lossless transitions. Hence
these elements have to be considered in the analysis and design of the converter. This section
gives the complete analysis of the Phase Modulated Converter, taking into account the major
parasitic elements.
VDC
C3
S3
C1
D3
D1
S1
Im L
m
I pri
A
C4
C2
S2
D2
INVERTER
D4
Irefl
LLk
Dp
IL
L
Co
Vpri
B
Vo
m
LLk
S4
Dn
n:1
TRANSFORMER
RECTI
FIER
FILTER
LOAD
Fig. 2.3 Schematic Diagram of PMC used for Analysis and Simulation
Figure 2.3 shows the schematic diagram of the Phase Modulated Converter used in
analysis and simulation. Capacitors C1 to C4 represent the output capacitances of the Mosfets
together with any external snubber capacitors added. L m and L Lk represent the magnetizing
and leakage inductances respectively of the transformer. Zero voltage switching demands that,
before a Mosfet is switched on, its output capacitance be completely discharged. This
discharge is accomplished by the energy stored in the magnetizing and leakage inductances.
For the purpose of analysis, a complete cycle of operation is divided into 8 distinct
intervals for the inverter and 4 intervals for the secondary side rectifiers. The inverter and
rectifier intervals are inter dependant - the inverter currents (transformer primary currents) are
determined by the secondary side diode currents and the diode currents in turn depend on the
13
magnitude and polarity of the inverter voltages. However, for ease of analysis, they are
considered separately.
2. 3. 1 Positive Power Transfer Interval
The inverter intervals are determined solely by the switching sequence of the devices
[9,10]. In the first interval, known as the positive power transfer interval, the diagonal
switches S1 and S3 conduct, transferring power to the load. Figure 2.4 shows the PMC in
interval 1, highlighting the devices conducting and the current path.
VDC
C1
C3
S3
S1
Ipri
A
C2
C4
B
Im
I refl
IL
Vo
L
Lm
Co
Vpri
LLk
S4
S2
Dp
LLk
Dn
n:1
(a)
A
Vpri
IL/ n
Lm
I L L+L Lk
Co
+ Vpri
-----
Io
RL
n
B
(b)
--
Fig. 2.4 PMC in Power Transfer Interval
(a) Devices conducting
(b) Equivalent circuit
As may be seen, the primary current has two components - the reflected load current and the
magnetizing current. The magnetizing current is of importance in PMC, since it helps in
achieving ZVS at light loads, and hence has to be designed accordingly.
14
The following three equations are general and are valid in all the intervals.
Lm. d Im = Vpri
dt
(2.1)
Ipri = (Im + Irefl )
(2.2)
Irefl =  IDp − ID n  / n
(2.3)
By considering the devices conducting, as shown in Fig. 2.4a, the following equations, valid
in the first interval alone, can be obtained.
VC = VC = VDC
1
2
(2.4)
VC = VC = 0
3
4
(2.5)
Vpri = VDC
(2.6)
Since the primary voltage, and hence the secondary voltage is positive, diode Dp is forward
biased and Dn is reverse biased. This condition corresponds to the rectifier interval 1, which
is explained separately in section 2.3.5. The inverter interval 1 ends when S4 is switched off,
at an instant determined by the required phase difference [Φ ] .
2. 3. 2 Transition From Power Transfer To Freewheeling Mode
The second interval is the transition interval from power transfer mode to the
freewheeling mode. This interval begins when S4 is switched off. There are two important
factors to be considered in this interval.
1. Turn-off process of S4
2. Discharge of the capacitance across S1 , which is the next switch to be turned on.
As the gate voltage of S4 falls below the threshold level, the primary current which was
initially flowing through S4, now begins to flow through C4 and C1 as shown in Fig. 2.5a. By
proper design of the gate drive circuit and by adding external snubber capacitors across the
Mosfets, it can be ensured that the voltage across the device rises only to a small value, by the
15
time the device current becomes zero. Thus the turn-off losses are reduced. The significance of
PMC (or any other ZVS converter), is that the energy stored in these capacitances (intrinsic as
well as external) is not lost (as in the case of hard switched converters), but is fed to the load
/ source before the next turn on.
The voltage across S1, which is to be turned on next, is given by Eqs (2.7) and (2.8) As
seen the rate at which this voltage falls, is determined by the magnetizing current and the
reflected load current. Proper design ensures that this voltage eventually reaches zero and the
diode D1 begins to conduct. Figure 2.5b shows the equivalent circuit valid in interval 2.
VD C
D1
S3
C1
S1 A
LLk
Irefl
Dp
Im
I pri
A
C4
S4
S2
L
Vsec
Lm
B
IL
LLk
B
Vo
Co
Dn
(a)
A
VDC
Vpri
C1 L
m
I pri
L
1
B
IL L+LLk
L
Im IL/n
+
_+
Vpri
n
Co
Io
RL
C4
(b)
Fig. 2.5 PMC in interval 2.
(a) Devices Conducting
(b) Equivalent Circuit
From the equivalent circuit, the following equations are obtained.
Im+ Irefl
d V
=
dt C 4
2C
where, C = C 1 = C 2 = C 3 = C 4
VC = VDC − VC
1
4
(2.7)
(2.8)
16
Vpri = VC
1
(2.9)
Since the primary, and hence the secondary voltage remains positive during this
interval, Dp continues to conduct and Dn is still reverse biased. Therefore the reflected load
current (Irefl ), remains in the positive direction throughout the interval. This interval ends
when S1 is switched on. The instant when S1 is turned on, is determined by the dead time
T Delay . T Delay is defined as the dead time allowed between the turn-off of a Mosfet and the
subsequent turn-on of the complimentary Mosfet in the same arm. The design should ensure that
VC is completely discharged and D1 begins to conduct within this chosen T Delay .
1
2. 3. 3 Freewheeling Interval
This interval starts when S1 is turned on. Since the body diode D1 is conducting when
the gate drive to S1 is applied, this is truly a zero voltage turn-on transition. Even after gate
drive is applied to S1, the diode D1 continues to conduct. The magnetizing current and the
load current freewheel through D1 and S3 during this interval. The magnetizing current remains
at its positive peak throughout the interval.
VDC
D1
S3
S1
A
Im
Ipri
LLk
I refl
Dp
IL
Vo
L
Co
B
A
LLk
S4
S2
Dn
B
(a)
IL
A
IL /n
Co
L
Lm
B
L+LLk
Io
RL
(b)
Fig. 2.6 PMC in Interval 3 (a) Devices Conducting (b) Equivalent Circuit
17
From Figs. 2.6a and 2.6b, the following equations can be obtained.
Vpri = VC = VC = 0
1
3
(2.10)
VC = VC = VDC
2
4
(2.11)
Though the transformer voltages remain zero in this interval, the leakage inductance
L LK ensures that only Dp is forward biased and Dn reverse biased. Hence the reflected load
current still remains in the positive direction. The interval 3 ends when S3 is turned off. The
instant when S3 is turned off is determined by the clock pulse of the controller IC.
2. 3. 4 Transition From Freewheeling To Power Transfer Mode
The interval 4 begins when S3 is turned off. The turn-off process of S3 is similar to the
one explained in Section 2.3.2. It is a nearly lossless transition, as the output capacitances
limit the voltage rise while the current is falling.
From ZVS considerations, the Transition from the Freewheeling mode to the Power
Transfer mode, is the crucial interval. Figure 2.8 shows the PMC in this interval, along with
the equivalent circuits. Since S2 is the next switch to be turned on, C 2 has to be fully
discharged. This discharge process is assisted by the primary current, made of the load
component and the magnetizing component. So far this transition is similar to the Power
Transfer to Freewheeling Transition explained in section 2.3.2. But the crucial difference
between the two transitions is that, in the Freewheeling to Power Transfer transition, as C 2
begins to discharge, the transformer
voltages become
negative. The secondary side diode Dn, thus begins to
conduct. Due to the leakage energy, the diode Dp also
VAB
continues to conduct. The load component of the primary
Irefl
current which is proportional to the difference between
Im
Interval 4
these two currents, begins to reduce, and eventually
becomes negative, as shown in Fig. 2.7. The rate of this
reversal of the primary current is determined by the
leakage inductance. The magnetizing current component
6
B
6
Fig. 2.7 Reversal of reflected load
current in interval 4.
also
18
A
VDC
C3
Vpri
D1
S3
LLk
I refl
IL
I Dp
Im
L
Vo
Co
S1
LLk
Ipri
A
B
B
Rectifier during the overlap interval
C2
A
S4
S2
ID n
Im
IL
LLk
Irefl
L
LLk
Inverter
IDn
Rectifier after the overlap interval
(IDp _ ID n) / n
Vpri
VD C
A
IL / n
Vpri /n
C3
Co
B
(a)
B
Vo
L
IL
Co
+
+_
Lm
RL
C3
Lm
Vpri
VD C
C2 Ipri
ID p ID n
Vpri /n
B
A
L
+
_+
Co
Vo
RL
C2
(c)
(b)
Fig. 2.8 PMC in Interval 4
(a) Devices Conducting
(b) Equivalent Circuit in the Overlap mode
(c) Equivalent Circuit after the Overlap mode
reduces due to the negative voltage, but at a much slower rate, since the magnetizing
inductance is relatively large. The design of the magnetizing and the leakage inductances should
ensure that VC is completely discharged, before the sum of the magnetizing current and the
2
reflected load current becomes negative.
The equivalent circuit for this interval is shown in Fig. 2.8b. Note that since both Dp
and Dn conduct simultaneously, the transformer secondary is effectively short circuited through
the leakage inductances L Lk . More about this is explained later in Section 2.3.5. The overlap
interval ends when the current through Dp goes to zero. Depending on the magnitude of the load
current, this may or may not occur within the fourth inverter interval. Figure 2.8c gives the
equivalent circuit at the end of the Overlap Mode.
The governing equations for this interval are,
19
Ipri
dV
=
dt C 3 2C
(2.12)
VC = VDC − VC
2
3
(2.13)
Vpri = −VC
3
(2.14)
The duration of interval 4 is equal to the T Delay , and ends when S2 is switched on with
zero volts across it. As stated earlier, the design of the transformer inductances should ensure
that C 2 is completely discharged and D2 begins to conduct within this time interval.
The intervals 5, 6, 7 and 8 correspond to the negative half cycle and are similar to the
intervals 1, 2, 3 and 4 respectively. Table 1 below, lists the governing equations in all the
inverter intervals, along with the devices conducting and starting and ending of each of the
intervals.
U Devices From
ON
1 S3 , S4
To
S3 On S4 Off
VC
1
VDC
2 S3 C4 C1 S4 Off S1 On VDC − VC 4
S1 On S3 Off
0
4 D1 C3 C2 S3 Off S2 On
0
5 S1 S2
0
3 S3 D1
S2 On S1 Off
6 S2 C1 C4 S1 Off S4 On
7 S2 D4
S4 On S2 Off
8 S4 C2 C3 S2 Off S3 On
Lm. d Im = Vpri ;
dt
VC
2
VC
VDC
0
0
VDC
0
VDC
0
I
dV = pri
2C
dt
VDC
VDC − VC
3
−I
dV = pri
2C
dt
VDC
VDC
3
0
I
dV = pri
2C
dt
VDC
0
VDC
0
VDC
−i
dV = pri
dt
2C
Ipri = (Im + Irefl )
VDC − VC
2
;
VC
4
VDC
VC
1
0
VDC
−VC
3
VDC
−VDC
VDC − VC1 −VC
4
0
0
0
VC
Irefl = (IDp − IDn) n
Table 1. Inverter Intervals - Sequence and Governing Equations.
20
Vpri
2
2. 3. 5 RECTIFIER INTERVALS
There are just two types of rectifier intervals, the normal mode in which either Dp or
Dn conducts and the overlap mode in which both the diodes conduct simultaneously. The
equivalent circuits for these two types are shown in Fig. 3.6.
IL
L+LLk
Vsec
Co
_+
Io
IL
IDp
Vo
LL k
Vsec
L
_+
RL
Vo
Io
Co
RL
IDn
Fig. 2.9. Equivalent circuit of the secondary side rectifiers and filters
(a) Normal mode (b) Overlap Mode
The governing equations valid for both the rectifier intervals are,
C o d Vo = IL − Io
dt
(2.15)
L∗ d IL = Vin − Vo
dt
(2.16)
where L∗ and Vin depend on the particular interval and are listed in Table 2.
At the start of the cycle, the secondary voltage is positive and the diode Dp alone
conducts. This corresponds to the rectifier interval 1 and the equivalent circuit shown in Fig.
2.9a is valid in this interval. This interval lasts till the secondary voltage becomes negative and
the diode Dn gets forward biased. The condition for Dn to be forward biased is,
−Vsec ≥ Vsec − LLk d IDp
dt
(2.17)
The overlap interval begins when the above condition is met. Both the diodes conduct resulting
in a short circuit across the secondary, through the leakage inductances. The current through Dp
decreases at the rate given by,
V
d I
= sec
Dp
dt
LLk
(2.18)
The overlap interval ends when IDp reaches zero. In the next interval Dn alone conducts.
Table 2 lists the equations valid in each of the four rectifier intervals.
21
U devices
1
Dp
From
IDn ≤ 0
L Lk d
I
2 dt D p
IDp ≤ 0
Dn
IL
Vsec ≤
2 D p D n Vsec ≤ L Lk d I
2 dt D p
3
IDp
To
IDp ≤ 0
Vsec ≥
−L
4 D p D n Vsec ≥ Lk d ID
2 dt n
IL − IDn
−L Lk d
I
2 dt D n
IDn ≤ 0
0
d I = Vsec
dt
L Lk
IDn
Vin
L∗
0
Vsec
L+LLk
d I = −Vsec
dt
L Lk
IL
0
L
−Vsec
L+LLk
IL − IDp
0
L
L∗ d IL = Vin − Vo
C o d Vo = I L − Io
dt
dt
Table 2. Secondary Rectifier Intervals - Sequence and Governing Equations
The equations listed in Tables 1 and 2, are used to simulate the converter. Simulation is
used to study the steady-state as well as the dynamic performance of the converter. Figure 2.10,
shows the various waveforms of the PMC, in a complete cycle of operation.
VA
VB
VA B
IL
Irefl
Im
Ipri
Intervals
1
2
3
4
5
6
7
8 1
Fig. 2.10 Simulated Waveforms of PMC over a Complete Cycle
22
CHAPTER 3
DESIGNING FOR ZVS
In this chapter the various factors affecting zero voltage switching are
discussed. A design procedure to achieve ZVS is developed. The concept of ZVS LIMIT is
introduced. Use of numerical simulation in the design process is emphasized.
3. 1 TWO DIFFERENT TYPES OF TRANSITIONS
From the analysis of PMC in Chapter 2, it is important to note that there are two types
of transitions. One is from the power transfer mode to the freewheeling mode (inverter
intervals 2 and 6 explained in Chapter 2). The other transition is from the freewheeling to the
power transfer mode (inverter intervals 4 and 8). From the ZVS view point, these two
transitions are quite different. During the power transfer to freewheeling transition, shown in
Fig. 3.1b, the reflected load current is always in the proper direction to discharge the
capacitance of the Mosfet to be turned on. Hence the load current aids the magnetizing current
in achieving ZVS. In the freewheeling to power transfer transition, shown in Fig. 3.1c, the
reflected load current reverses direction, the rate of reversal being determined by the leakage
inductance. Once the load current reverses direction, it opposes the magnetizing current in the
discharge of the Mosfet capacitance. Hence the freewheeling to power transfer transition is
more critical from the ZVS viewpoint. The design equations are hence derived to achieve ZVS
in this transition, which automatically ensures ZVS for the other transition too.
VAB
VAB
b
Ir e f l
Ir e f l
Im
Ir e f l
Im
Im
VAB
c
(a)
6
B
(b)
6
6
B
(c)
6
Fig. 3.1 (a) Magnetizing and reflected load current during the two types of transitions.
(b) Power transfer to Freewheeling transition expanded
(c) Freewheeling to Power transfer transition expanded
23
3. 2 FACTORS AFFECTING ZVS
For any given line and load conditions the various factors affecting ZVS are, the
magnetizing current, the leakage inductance, the dead time T Delay , and the capacitance across
the Mosfet. The qualitative effects of each of them are discussed below.
3. 2. 1 Magnetizing Current
Figure 3.2 shows the primary voltage and the magnetizing current. As seen, during the
transitions, the magnetizing current always has the correct polarity to discharge the output
capacitance of the Mosfet to be turned on (Refer Fig. 2.3). Hence higher magnetizing current is
good from a purely ZVS point of view.
I refl
Im
VAB
VAB
6
B
6
6
Fig. 3.2 VAB Vs. Magnetizing current
B
6
Fig. 3.3 VAB Vs. Reflected load current
with low leakage inductance
However, higher magnetizing current results in higher peak and rms. currents through
the Mosfets, hence increasing the conduction losses. The design of magnetizing inductance
should be done considering these two conflicting requirements.
3. 2. 2 Leakage Inductance
As explained earlier, the leakage inductance helps to achieve ZVS, by slowing down
the reversal of reflected load current during the transition from freewheeling to power transfer
mode. This is explained in figures 3.3 and 3.4. Due to the low leakage inductance, the reflected
current shown in Fig. 3.3, changes direction quickly, whereas in Fig. 3.4, the large leakage
inductance slows down this process. Hence large leakage inductance is better from the ZVS
viewpoint.
24
Irefl
Vrect
VAB
VAB
Fig. 3.4 VAB Vs. Irefl for large LLk
Fig. 3.5 VAB Vs. Rectified Secondary Voltage
However, large leakage inductance results in longer overlap intervals. Figure 3.5
shows the primary voltage and the rectified secondary voltage. As seen, the secondary voltage
does not rise immediately after the primary voltage rises, (in either direction) but stays at zero
till the overlap interval is over. Hence the effective duty ratio seen by the output filter is
reduced. This loss of duty ratio, demands smaller turns ratio for the transformer, if regulation is
not to be compromised. This increases the primary current and hence the conduction losses.
3. 2. 3 Dead Time ( T Delay )
For ZVS to be achieved, the maximum allowable T Delay is the time in which the
primary current reverses direction. Figure 3.6, shows that the time taken for the reversal of the
primary current, is a strong function of load current. At light loads, the time taken for the
reversal is more compared to heavy loads. Therefore T Delay should preferably be made load
dependant - it should be high at light loads and small at higher loads.
Max. Load
Min. Load
Max. TD e l a y
allowable
Load
@ Max.
Min. Load
Fig. 3.6 Total Primary current at two different loads ( During Inverter Interval 4)
25
3. 2. 4 Mosfet Output Capacitance
Larger capacitance across the Mosfets, helps to reduce the turn-off losses by limiting
the voltage rise, while the device current is falling. Hence with a view to minimize turn-off
losses, external capacitors may be added, apart from the intrinsic capacitance COSS of the
Mosfets. However, during the turn-on process, larger capacitance demands more energy to be
stored in the magnetizing and leakage inductances, to be fully discharged. Hence from the ZVS
point of view, smaller capacitance is preferred.
The transformer primary voltage gives information about the turn-on transitions of all
the four Mosfets. Figure 3.7 shows the primary voltage and current, and explains how ZVS is
lost with insufficient magnetizing current or leakage inductance or by improper choice of
T Delay .
VAB
4
4
Ipri
3
3
1
1
2
2
(a)
(b)
4
4
3
3
1
1
2
2
(c)
(d)
Fig. 3. 7 Primary voltage and primary current
(1, 2, 3 and 4 represent the instants when S1 , S2 ,
S3 and S4 are turned on respectively.)
(a) Non ZVS due to less magnetizing current
(b) Non ZVS due to less leakage inductance
(c) Non ZVS due to small TDelay
(d) Non ZVS due to high TDelay
(e) ZVS for all the transitions
4
3
1
2
(e)
26
3. 3 DESIGN STRATEGY TO ACHIEVE ZVS
From
the
equivalent
circuit
LLk
corresponding to the fourth inverter interval
+ C3
(which is the crucial interval for ZVS), the
following expression for the voltage across the
Mosfet to be turned on ( VC ), is derived in
Lm
VD C
Ipri
n2
Lo
Co
Irefl
+ C2
2
Appendix 1.
Fig. 3.8. Eq. Circuit of PMC in Overlap Mode
VC = VDC − (Im + Irefl )
2
Leq
sin ωt
2C
(3.1)
where,
ω =
1
2 C Leq
Leq = L∗Lk Lm
C = C 2 = C3
; L∗Lk is the leakage inductance referred to the primary
; Capacitance across the Mosfet including the external capacitors
Im ; Peak magnetizing current
Irefl ; Reflected load current at the start of the fourth interval
From the above expression, it is clear that, the following two conditions have to be
satisfied to achieve ZVS, at any given load.
1. (Im + Irefl )
2. T Delay = π
2
Leq
≥ VDC
2C
(3.2)
2C Leq
(3.3)
The first condition ensures that the peak of the sinusoidal component of Eq. (3.1) is at
least equal to VDC , so that VC eventually reaches zero. If this condition is met, then the time
2
taken for VC to reach zero is equal to or less than one-fourth the resonant period (ω). The
2
second condition ensures that the Mosfet is switched on when VC is zero.
2
Hence the design strategy is to,
27
Select T Delay considering the switching frequency and Mosfet characteristics.
Calculate the value of L eq from Eq. (3.3), with the above value of T Delay . L ∗Lk is
approximately equal to L eq , since the L m is much larger than L ∗Lk .
With the above value of L Lk , calculate from Eq. (3.2), the peak magnetizing current
required at any load down to which ZVS is required. From the value of peak magnetizing
current (I m pk ), obtain the value of magnetizing inductance (L m ) needed.
Lm =
VDC max.T on min
2.Im pk
(3.4)
The design equations discussed so far, have been derived assuming that the operation
remains in the overlap mode, till the Mosfet capacitance is completely discharged. This may
not be strictly valid for all combinations of line and load conditions. Also, the selection of
T Delay , in the suggested design procedure, is made arbitrarily. Hence the values thus
obtained, for L m , L Lk and T Delay , do not represent the optimum solutions. However, they
serve as good initial estimates which may be used in simulation. From repeated simulation
runs, the most satisfactory design values for all the parameters may be obtained.
3. 4 ZVS LIMIT
From Eq. (3.2), it is clear that, at light loads, larger magnetizing current and leakage
inductance are needed to achieve ZVS. As discussed in Sections 3.2a and 3.2b, this results in
increased conduction losses, for any given load. More than the increase in the magnitude of
instantaneous switch currents, the main reason for the significant increase in conduction loss, is
that, in PMC, during the freewheeling period, the currents circulate in the primary switches,
whereas in PWM converters, the currents circulate only in the secondary, and not through the
primary switches. Figures 3.9, shows the primary voltage and primary current for the PWM full
bridge converter and Phase Modulated full bridge converter of similar specifications, and
under the same line and load conditions. As seen, not only is the peak current in PMC more
than the PWM case, but also it remains at this peak value throughout the freewheeling interval.
Hence the rms. and average switch currents are more in PMC. This increase is even more
significant at low duty ratios.
28
Ipri
VAB
Ipri
VAB
(a)
Fig. 3.9. Primary Voltage and Primary Current for
(b)
(a) PWM full bridge
(b) PMC
Hence, it is clear that, if ZVS is to be achieved right down to no load, it will be at the
cost of increased conduction losses. On the other hand, if the converter is designed to obtain
ZVS only at and near full load, the switching losses at light loads will be very large. Hence, the
Load down to which ZVS is obtained [ZVS LIMIT], is an important factor to be considered in
the design. Figure 3.10, shows the Mosfet losses (corresponding to the 560W/250kHz PMC
60
50
50
Losses (W)
60
40
30
al
T o t ction
20
Co
ndu
10
40
30
20
g
hin
itc
Sw
Losses (W)
discussed in Chapters 4 and 5) over the entire load range, for two different ZVS LIMITs.
Total
10
Switching
n
Conductio
0
0
2
4
6
8
10
12
14
16
18
20
2
Load Current (A)
4
6
8
10
12
14
16
18
20
Load Current (A)
(a)
(b)
Fig. 3.10. Mosfet Losses at Different ZVS LIMITs.
(a) ZVS LIMIT : No load
(b) ZVS LIMIT : Full load
ZVS LIMIT may be chosen such that satisfactory performance (minimum overall losses)
is obtained throughout the load range. Alternatively, it may be chosen, to minimize the losses at
a particular load or load range, considered as nominal. Further discussions on ZVS LIMIT,
specific to the developed converter, is given in Chapter 4.
29
CHAPTER 4
DESIGN AND DEVELOPMENT
OF A 250 kHz / 560 W CONVERTER
The broad specifications and the overall block diagram of the developed SMPS are
given. Design of all the major components of the converter, like the power transformer, filter
components, drive and control circuits are explained in detail. Some of the practical aspects in
the physical design are discussed.
4. 1 SPECIFICATIONS
Nominal Output power
Output voltage
Max. Output current
Input
560 W
28 V DC
20 A
150 - 270 V AC, 50 Hz
Line regulation
Load regulation
Output ripple
Switching frequency
EMI
Protections
< 0.1 %
< 0.1%
< 0.5 % (pk. - pk.)
250 kHz
VDE - 0871 Class B
Output overload / short circuit
(Fold back with auto recovery)
Output overvoltage
Input overvoltage / under voltage
Isolation
2.5 kV AC for 1 minute
Table 4.1. Specifications of the Developed Converter
31
E
N
L
Vsense
18V
12V
Drive Circuit
PMC Control IC
HF Transformer
Fig. 4.1 Overall Block Diagram of the Converter
To
Mosfet
Gates
Phase Modulated Converter
Protection Circuit
Diode Bridge
Aux. Power Supply
EMI Filter
Protection Circuit
FW Rectifier
Feedback
Network
Output Filter
L
O
A
D
4. 2 CHOOSING THE ZVS LIMIT
The first step in design is to select the ZVS LIMIT, defined previously as the load down
to which ZVS is obtained. Loss curves such as the one shown in Fig. 4.2, help in deciding the
ZVS LIMIT. These curves give the total power lost in all the four Mosfets, at different loads,
for various chosen values of ZVS LIMITs. These losses comprise of the conduction losses and
the turn-on and turn-off losses, and are obtained from simulation. The exact procedure
followed to calculate these losses, is outlined in the section on Thermal Design.
60
Total Losses (W)
50
ZVS LIMIT= 0A
40
10A
30
15A
20
20A
10
0
2
4
6
8
10
12
14
16
18
20
Load Current (A)
Fig. 4.2. Loss Curves for Different ZVS LIMITs
From the loss curves it can be seen that, at heavy loads, where the conduction losses
dominate, higher ZVS LIMITs result in lower total losses. At light loads, where switching
losses is dominant, the lower ZVS LIMITs, result in lower overall losses. A ZVS LIMIT of
around 15A, gives satisfactory performance throughout the load range. However, it should be
noted that these curves are valid only for the specified frequency of 250 kHz and the chosen
Mosfet (IRFP460). For different switching frequencies or for different Mosfet characteristics,
the loss curves will be different and will have to be generated through simulation.
For the developed converter, ZVS LIMIT is chosen to be at 16 A (80% load). The
values of magnetizing inductance, leakage inductance and T Delay are then calculated using the
procedures outlined in Chapter 3. The values obtained are,
T Delay =
175 nsec
C DS
=
600 pF (intrinsic = 380 pF ; external = 220 pF)
Lm
L∗Lk
=
=
140 µH
7 µH
32
4. 3 DESIGN OF POWER TRANSFORMER AND PRIMARY INDUCTORS
For the chosen leakage inductance, the loss of
effective duty ratio due to overlap effect is determined
VAB
from simulation. Fig. 4.3 shows the primary voltage
IL
and the output inductor current, at full load and
minimum input voltage. As seen, the inductor current
On time lost
due to Overlap
begins to rise only after about 300 nsec, after the
primary voltage becomes positive. The turns ratio for
0
the power transformer, is calculated considering the
3 usec
Fig. 4.3 Loss of Effective Duty ratio
due to Over lap Effect.
reduced effective duty ratio available. The core is
made of high frequency ferrite materials and is operated at low flux densities (< 0.1T), to
reduce core losses. The windings are made of copper foils to reduce the losses due to skin
effect [18]. The transformer details are given in Table 4.2.
In order to study the performance of the converter at various ZVS LIMITs, the
magnetizing and leakage inductances are realised through separate external inductors with a
number of tappings. In the actual converter, it is possible to integrate both of them or atleast the
magnetizing inductance with the transformer, by using appropriate air gap.
Core - Ferrite(A-43
Webel)
Primary
No. of turns
Winding
Copper Foil
Secondary
Winding
Air gap
No. of turns
Copper Foil
mm
Power
Magnetizing Leakage Inductor
Transformer
Inductor
(Two in series)
EE 42 / 20
EE 42 / 20
EE 25
8
0-10-13-16
70µ
2
70µ × 3
-
70 µ
0.75
8
70µ × 2
0.5
Table 4.2. Details of Transformer and Primary side inductors
4. 4 DESIGN OF FILTER COMPONENTS
The design of filter inductor and capacitor is identical to that of the full bridge PWM
converter [11]. The inductor is designed to operate in continuous current mode [CCM] down to
5% load.
33
 Ts
 1−D

min  . 2 .Vo
Lo =
∆IL
where,
Dmin = minimum duty ratio occurring at min. load and max. input
Ts
= switching period
∆IL = inductor ripple current (pk - pk)
(4.1)
To design the filter capacitor, it is assumed that the entire output voltage ripple is
caused by the product of the ESR of the capacitor and the current through it. Hence the
maximum ESR allowable is
ESR Max. =
∆Vo
∆I L
(4.2)
The values obtained for the filter components are,
= 18 µH
= 2000 µF / 40 V (ESR ≈ 100 mΩ )
Filter inductance
Filter capacitance
High frequency core materials are not needed for the filter inductor since the high frequency
AC component of the inductor current is very small.
4. 5 SEMICONDUCTOR SELECTION AND THERMAL DESIGN
The peak, rms. and average current ratings required for the Mosfets and the rectifier
diodes are accurately determined from simulation. The left leg Mosfets which switch on / off
during the freewheeling to power transfer transition, operate under significantly different
conditions compared to the right leg Mosfets, which switch on / off during the power transfer
to freewheeling transitions. The ratings needed for the left leg and the right leg Mosfets are
slightly different. For the chosen ZVS LIMIT of 16 A, the ratings needed are as follows.
Parameters
Peak current
(A)
Max. rms. current through
Mosfet channel
(A)
Max. average current
through the body diode (A)
Peak voltage stress
(V)
Left leg Mosfets
6.47
4.2
Right leg Mosfets Secondary diodes
6.47
21
2.4
--
0.14
2.1
10
380
380
190
Table 4.3 Mosfet and Diode Ratings
34
Apart from the current and voltage stress, the other requirements for the Mosfets are
low R DS
ON
to reduce conduction loss and
low input capacitance (Ciss ) to achieve fast
transitions. A major advantage of PMC, is that the diodes across the Mosfets need not be ultra
fast. Hence, the intrinsic diodes of the Mosfets themselves can be used. The secondary side
rectifier diodes however, have to be of the ultra fast recovery type. The junction capacitance
of these secondary diodes needs to be low, since it resonates with the leakage inductance of the
transformer, resulting in high voltage overshoots. This problem is particularly severe in PMC,
since large leakage inductances are purposely introduced to achieve ZVS. A modified scheme,
which addresses this problem is suggested in Chapter 6.
In order to design the heatsinks for the Mosfets, the total losses, comprising of the
conduction losses and the switching losses, are to be determined accurately. The conduction
losses include losses both in the channel as well as in the body diodes. The channel losses are
calculated from a knowledge of the RDS ON and the rms. current through the channel. The diode
losses are obtained from the diode drop and the average current through the diode, obtained
from simulation. The turn-on losses at the maximum input voltage, is calculated from the
voltage across the Mosfet at the instant of turning on and the value of Mosfet capacitance
(intrinsic and external), as explained in Fig. 4.4a. For calculating the turn off losses, the Mosfet
current is assumed to fall linearly within a fall time of 50 nsec. The product of this falling
current and the voltage, gives a measure of the turn off losses, as explained in Fig. 4.4b.
VDS
ID
VD S
VDS
ON
t fall
VG S
2
Turn-On loss = C DS VDS
(each Mosfet)
PLoss
ON
Turn-Off loss = Av. PLoss
.f
(b)
(a)
Fig. 4.4 Calculation of Switching Losses a) Turn-on Losses
b) Turn-off Losses
The losses in the secondary rectifier diodes, are mainly on account of the conduction
losses given by the product of the forward voltage drop of the diode and the average current
through it. After estimating the Mosfet and diode losses, the heatsinks are chosen to obtain the
35
specified temperature rise of 30 o C. In the present case all the four Mosfets are mounted on the
same heat sink. If separate heat sinks are used, the different requirements of the right leg and
left leg Mosfets have to be considered in the design.
4. 6 CONTROL CIRCUIT
The Phase modulation controller IC, ML4818 [20] is used to obtain the control signals
for each of the four Mosfets. It features both current mode control as well as voltage mode
control with feed forward option. In the present converter, voltage mode control is used. The
dead time T Delay is programmable through an external resistor. Under voltage lock-out circuit
with 6V hysterisis, pulse by pulse current limit, an error amplifier with slew rate of 8.5
V/usec, and four 1.5 A peak current Totem-pole output drivers are some of the features of the
control IC. It can be used up to a clock frequency of 1.5 MHz, corresponding to converter
switching frequency of 750 kHz.
The power supply for the control IC, drive circuits and other monitoring and protection
circuits are derived from a separate flyback converter, mounted on the same PCB. Protections
include input over / undervoltage, output overvoltage, output overload and short circuit. In
addition, protection of the Mosfets against transformer saturation or shoot through faults, is
provided by directly sensing the switch currents.
The feedback and the compensation networks are discussed in the next section.
4. 7 DYNAMIC MODEL AND COMPENSATOR DESIGN
The small signal dynamic model of PMC is similar to the PWM full bridge topology,
since from a control point of view, phase shift control is analogous to pulse width control. The
large leakage inductance in the Phase modulated converter, does result in a slight deviation,
from the PWM model [25]. However, for practical compensator design, this difference may be
neglected, as it affects mainly the Q factor alone in the model. The model derived for the PWM
case is as follows [11].
∼
V
(1 + s C o R ESR )
Vo (s)
where, ω = 1
(4.3)
= DC
∼
2
d(s)
LC
s
s
1+
+
Qω ω 2
This model is verified for the case of PMC, through step response of the simulated
system as well as by frequency response measurements on the actual converter. The Frequency
response plots (for the converter alone), are shown in Fig. 4.5. For the designed values of L, C
36
and ESR, the zero due to the ESR is near the LC corner frequency of around 800 Hz. Due to
this zero and the high damping provided by the leakage inductance, the frequency response
plots look similar to that of a first order system.
0
10
0
db
-10
-60
-20
10k
-80
100
10
4.7nF
10nF
degrees
18k
-40
-30
Vo
-20
4.7k
100k
47k
+
Vref
-100
10000
1000
Frequency in Hz
Fig. 4.5 Frequency Response Plots of PMC
Fig. 4.6 Feedback and Compensator Networks
The compensator is designed such that the overall loop gain falls with a single slope
over the entire frequency range of interest [19]. The design involves placing two zeroes at the
LC corner frequency to cancel the complex poles, a pole at the origin for steady state accuracy
and another pole near the ESR zero. The crossover frequency is designed to meet the transient
response specifications. The feedback and compensator network are shown in Fig. 4.6. The
measured overall loop gain of the converter is shown in Fig. 4.7.
50
0
40
-50
-100
30
Magnitude
-150
20
db
-200
10
-250
Phase
-300
0
-10 1 0
degrees
-350
100
1000
Hz
10000
Fig. 4.7. Measured Overall Loop Gain (−Aβ) of the Converter
Phase Margin = (360 - 275) = 850
37
4. 8 DRIVE CIRCUIT
Since each of the Mosfets are switched at near 50% duty ratio always, a single drive
transformer with two secondaries can be used to drive the two Mosfets in the same arm. The
drive circuit, shown in Fig. 4.8, is designed to achieve fast turn-off (< 100 nsec) of the device.
The turn-on is made relatively slower, since it is a lossless transition. The transistor Q1,
discharges the input capacitance of the Mosfets quickly, thus ensuring fast turn-off times. The
buffer stage is made of complimentary P and N channel Mosfets with low input capacitances.
For low power applications, the IC can directly drive the main Mosfets without the external
buffer stage.
D
Rg
Ctl.
IC
Buffer
Rb
Rs
G
S
Q1
Cs
Fig. 4.8. Mosfet Gate Drive Circuit
38
CHAPTER 5
SIMULATION AND EXPERIMENTAL RESULTS
The important experimental results are presented. Relevant waveforms, explaining the
concept of phase modulation, zero voltage switching and the factors affecting it, loss of ZVS
for loads below the ZVS LIMIT etc. are shown. The performance of the converter under
different ZVS LIMITs are discussed. The experimental results are compared with those
obtained from simulation.
5. 1 REGULATION BY PHASE MODULATION
Output voltage regulation better than 0.1%, over the entire line and load ranges, is
obtained by Phase modulation. Figures 5.1 and 5.2, show how the phase difference between the
two legs (i.e., between VA and VB ) is controlled to regulate the transformer primary voltage
(VAB ), and hence the DC output, as the input varies from 150 V AC to 270 V AC.
(a)
(b)
Fig. 5.1. Phase difference at 150 V AC input
(a) VA and VB
(b) VAB
(Vert: ≈ 125 V/div Hori: ≈ 0.66 usec/div)
Fig. 5.2. Phase difference at 270 V AC input
(a) VA and VB
(b) VAB
(Vert: ≈ 125 V/div Hori: ≈ 0.66 usec/div)
39
5. 2 ZVS AND NON-ZVS TURN-ON TRANSITIONS
The transformer primary voltage gives information about the turn-on transitions of all
the four Mosfets. Figure 5.3 shows the simulated and experimental waveforms of the
transformer primary voltage ( VAB ) and primary current ( IAB ), corresponding to a load
current of 6A, which is well below the chosen ZVS LIMIT of 16A (80% load). As seen, the
turn-on in the freewheeling to power transfer mode (indicated by 2 and 3 in the figure), takes
place with about 180 V across the switch. This loss of ZVS is due to the insufficient energy
stored in the transformer inductances. The turn-on in the power transfer to freewheeling mode (
indicated by 1 and 4) is ZVS, as expected (as explained in Chapter 3, achieving ZVS for this
transition is relatively easier). Figure 5.4 shows the same waveforms for a load current of
18A, which is above the ZVS LIMIT. As seen, the increased reflected load current results in
ZVS turn-on for all the transitions.
500V
10A
Ipri
3
4
0
1
2
VAB
-500V
-10A 0
5uS
(a)
(b)
Fig. 5.3 Primary voltage and current at 6A load showing the turn-on transients. a)
Simulated results. (1, 2, 3 and 4 represent the instants when S1 , S2, S3 and S4 are turned on.)
500V
10A
3
Ipri
VAB
0
4
1
-500V
-10A 1.6509e-005
0
2
B
5uS5
Fig. 5.4 Primary voltage and current for a load current of 18 A. All the transitions are ZVS.
(VAB: ≈ 125 V/div IAB: ≈ 2.5 A/div ;
Hori: 0.5µ sec/div)
40
Zero voltage switching can be confirmed by observing simultaneously, the gate voltage
and the drain-source voltage (VDS ). ZVS means that VDS is brought to zero before the gate
voltage reaches the threshold level. Figures 5.5a and 5.5b show these waveforms for ZVS and
Non-ZVS (for loads less than the ZVS LIMIT) cases, respectively. As seen, in the ZVS case,
VDS reaches zero volts (by resonance) well before the gate voltage reaches the threshold. In
the Non-ZVS case, VDS is around 200V, when the gate exceeds the threshold level. VDS is
then brought to zero, dissipatively, by the switching action of the Mosfet.
Fig. 5.5 VDS
(a)
(b)
Vs. VGS during turn-on.
a) for ZVS transition
b) for Non-ZVS transition
(VDS : ≈ 60 V/div VGS : 5 V/div Hori: 50 nsec/div)
5. 3 ZVS LIMIT AND MOSFET LOSSES
The ZVS LIMIT chosen in the design is 16 A (80%). The values obtained from
simulation for the various parameters, to obtain the chosen ZVS LIMIT are,
T Delay =
175 nsec
C DS
=
600 pF (intrinsic = 380 pF ; external = 220 pF)
Lm
L∗Lk
=
140 µH
=
7 µH
With these values, ZVS is obtained in the actual converter, from full load down to 16.8 A. The
waveforms of the magnetizing current and the reflected load current corresponding to the
designed ZVS LIMIT of 16 A are shown in Fig. 5.6. It may be noted from Fig. 5.6a, that the
magnetizing current always maintains the correct polarity to aid in ZVS. Figure 5.6b, shows the
effect of the leakage inductance in slowing the rate of change of the reflected load current. It
may also be observed that during the freewheeling interval (when VAB is equal to 0), the peak
magnetizing current and the load current circulate through the primary switches, which
increases the conduction losses.
41
(a)
(b)
Fig. 5.6 Waveforms corresponding to ZVS LIMIT of 16 A (80% load).
a) Magnetizing current
Vs. VAB
b) Reflected Load Current Vs. VAB
In order to verify the loss curves (which are used in the design process) and other
results like peak current stress, Mosfet voltage at turn-on etc. obtained from simulation, the
performance of the experimental converter were studied under various ZVS LIMITs. The
different ZVS LIMITs were achieved by varying the magnetizing inductance (made of an
external inductor with many tappings). The experimental results were consistent with the
simulation results. For ZVS LIMIT of 80% load, the total Mosfet loss at min. load, as predicted
from simulation, was more than that at full load. The experimental results obtained for two
different ZVS LIMITs - 12A (60%) and 16A (80%) are listed in Table 5.1 and compared with
the simulation results.
ZVS LIMIT = 12A
PARAMETERS
Peak device voltage stress
Peak device current stress
VDS at Turn-ON
10% load
Left Leg Mosfets
Half load
Full load
ZVS LIMIT = 16A
Experimental Simulation Experimental Simulation
400 V
382 V
400 V
382 V
7.8 A
7A
6.9 A
6.4 A
215 V
80 V
0
188 V
74 V
0
285 V
153 V
0
276 V
146 V
0
120 V
0
0
100 V
0
0
195 V
0
0
190 V
0
0
Full load
Half load
10% load
27W
14W
13W
29.5 W
13.2 W
11.8 W
Full load efficiency (over all)
80.6%
-
22W
15.5W
27W
82%
23.1 W
14.2 W
28 .2W
-
10% load
Right Leg Mosfets Half load
Full load
Total power lost in
all the Mosfets
Table 5.1 Converter Performance at two different ZVS LIMITs
42
The efficiency is measured as the ratio of output DC power, to the input AC power
measured with an appropriate wattmeter. Hence, it considers all the losses like the front end
rectifier losses, EMI filter losses, drive and control circuit losses etc. apart from the major
losses which include the Mosfet losses, secondary rectifier losses and the losses in magnetics.
Table 5.2 below, gives a loss estimate, at full load and corresponding to ZVS LIMIT of 16 A.
Loss components
Estimated
Losses in W
Mosfet Losses
Switching
Conduction
Secondary rectifier Losses
Conduction
Switching
Snubber
Magnetics
Transformer
Magnetizing inductor
Leakage inductor
Output filter inductor
1.6
21.4
26
5.6
5
6
3
3
2
Front end rectifier including EMI filters, thermistors etc.
Control and drive circuits including loss in Auxiliary power
supply
Current sensing resistors
Output Bleeder resistor
Total Estimated Losses
Total Measured Losses
10
15
5
3
106.6
122
Table 5.2 Loss Estimate at full load and maximum input voltage.
From the table it is seen that the major portion of the losses is in the secondary rectifier
diodes. By choosing a device with higher current rating and better recovery characteristics, the
losses can be significantly brought down. Similarly, the magnetic losses can also be reduced
substantially, by using the latest high frequency core materials. There is scope also for reducing
the drive circuit losses, by selecting Mosfets with low input capacitance. With these
improvements, it is possible to achieve overall efficiencies in the range of 85% to 90%. The
input voltage range in the present converter is quite large - 182 V DC to 382 V DC. The PMC
is not well suited for such applications with wide input variations. If the input variations are
restricted to a smaller range, efficiencies well above 90% can be expected.
43
5. 4 CURRENTS THROUGH LEFT LEG AND RIGHT LEG MOSFETS
As explained earlier, the left leg Mosfets and the right leg Mosfets, operate under
significantly different conditions. In the left leg Mosfets, the Mosfet channel conducts for the
most part and the body diode conducts only during the turn-on transients. In the right leg
Mosfets, the diode conducts for almost as much time as the Mosfet channel (depending on the
duty cycle). The device current and voltages are shown in Figs. 5.7 and 5.8 for both the left leg
and the right leg Mosfets. As explained in Chapter 4, and verified experimentally (Refer Table
5.1), achieving ZVS for the right leg Mosfets is relatively easier. Considering these
differences, it may be beneficial to select different values of T Delay and CDS for the two legs.
IC's which support such features have already been introduced (ML 4828, UC 3875). A
modified scheme which reduces conduction losses by considering the different operating
conditions of the two legs, is proposed in the Chapter 6.
400V
10A
IAB
0A
0V
-10A 0
VDS
3uS
Fig. 5.7. VDS Vs. IAB for left leg Mosfets. IAB is equal to the device current when VDS is zero.
Note that the device voltage falls to zero, before its current becomes positive.
400V
10A
I AB
0A
VDS
0V
-10A
0
3uS
Fig. 5.8. VDS Vs. IAB for right leg Mosfets. The intrinsic diode conducts (negative current
with VDS zero) for the major part. [Scale: VDS : 60V/div IAB: 2.5A/div Hori : ≈ 0.5 µ sec /div ]
44
5. 5 TURN-OFF TRANSITION
The turn-off losses for a given load, depend on the capacitances across the Mosfets
(intrinsic and external) and the fall time. The drive circuit shown in Fig. 4.8 in Chapter 4,
ensures low fall times (< 50 nsec) for the Mosfets. Figure 5.9, shows the gate voltage and the
Drain to Source voltage of the left leg Mosfets during the turn-off transition, at full load. As
seen, by the time the gate voltage falls below the threshold of approximately 2V (representing
zero device current), the VDS rises only by about 25 V. Hence turn-off losses are small.
Vert:
VD S : 60V/div
VGS
Hori
:
5V/div
: 50nsec/div
Fig. 5.9. VDS Vs. VGS during Turn-off
5. 6 POWER DENSITY
Commercial Power Supplies with specifications similar to the one developed, but
operating at 50 kHz, have power densities typically around 2W / inch3 . The developed Phase
modulated converter operating at 250 kHz, has a power density of 4W / inch3. The major
volume, as expected in high frequency converters, is occupied by the heatsinks - for the
rectifier diodes and the primary Mosfets. About 20 % of the volume is used for the EMI
filters, to meet the stringent specifications. The size of the magnetic components reduce by a
factor of about 2.5, compared to the 50 kHz converters. With the latest high frequency core
material, further reductions are possible.
Power densities of above 50W / inch3 have been reported in research journals [26].
However they can not be readily compared with the commercial power supplies like the one
developed, since the specifications in the two cases are quite different. Wide input ranges,
stringent EMI specifications, many protection and monitoring requirements and the over rating
of the components to increase reliability are some of the reasons for the low power densities in
the commercial power supplies. However, by hybridization, use of planar transformer and with
better heat removal mechanisms, power densities in the order of 15 W / inch3 can be achieved
with the Phase Modulated topology, for the same specifications.
45
CHAPTER 6
LIMITATIONS OF PMC
AND SOME MODIFIED SCHEMES
Some of the main drawbacks of the basic Phase Modulated Converter are indicated. A
few modified schemes, which attempt to overcome these problems, at the expense of additional
components, are discussed briefly.
6. 1 LIMITATIONS OF PMC
The two main drawbacks of the Phase Modulated Converter are as follows.
ZVS characteristics are load dependent. If ZVS is desired over the entire load range,
higher conduction losses result.
The large leakage inductance, purposely introduced to aid ZVS, resonates with the
junction capacitance of the secondary side diodes, resulting in excessive ringing and
voltage overshoots across the diodes.
The loss of ZVS at light loads may not be a serious problem from the viewpoint of
Mosfet losses alone. This is so because, the conduction losses at light loads are low and hence
the total Mosfet losses will be within acceptable limits, even if the switching losses are high.
In fact much of the discussions in the earlier chapters were on arriving at a compromise
between the switching losses and the conduction losses, in the nominal load range. However,
the other problems associated with the high frequency Non-ZVS switching, especially the EMI
caused by the sudden, dissipative discharge of the Mosfet capacitances during turn-on, may
demand, in some applications, ZVS over the entire load range, even at the expense of a few
extra components. Section 6.2 indicates some such schemes, which increase the ZVS range.
Suppressing the excessive ringing and overshoot across the secondary side diodes, by
simple RC snubbers connected across the diodes, is not practical, since the energy associated
with the oscillations is large. Section 6.3 shows a scheme where clamp diodes are used in the
primary side to limit the ringing and overshoot.
46
6. 2 SCHEMES EXTENDING THE ZVS RANGE
The basic PMC relies on the energy stored in the leakage inductance (and any external
series inductor added) and the magnetizing inductance (and any external parallel inductor
added) of the power transformer, to achieve ZVS. Of these two, the energy stored in the
leakage inductance is load dependant and hence at light loads, not enough energy is stored to
completely discharge the capacitances across the Mosfet. On the other hand, the energy stored
in the magnetizing inductance is load independent. Hence it is possible to reduce the load
dependency of the ZVS characteristics, if the design relies more on the magnetizing energy to
achieve ZVS.
6. 2. 1 Effective Use of Magnetizing Energy
Ideally, it may be expected that the magnetizing current lags the primary voltage and the
load component of the primary current by 900, and hence the contribution of the magnetizing
current to the total average and rms. switch currents is not significant. However, in practice it
is not so, mainly because of the long freewheeling period, during which both the magnetizing as
well as the load component of the primary current, remain at their peak values.
The modified scheme shown in Fig. 6.1, exploits the following two characteristics of
the PMC, to make effective use of the magnetizing energy (in the extra inductor, LEx).
Achieving ZVS for the Left leg Mosfets alone is difficult.
Each of the switches, is operated at 50% duty ratio.
VDC
C3
C in
S3
C1
D3
D1
S1
LEX
C2
C in
C4
D2
S2
D4
S4
Fig. 6.1 PMC with External Inductor for the Left leg
47
For the Right leg Mosfets, the magnetizing energy is not usually needed, as the reflected
load current itself is enough to achieve ZVS, even at loads as low as 20%. Hence in the new
scheme, the magnetizing inductance of the transformer is made large and the magnetizing
current very small. This way the conduction loss through the Right leg Mosfets is made
minimum, corresponding to the PWM full bridge topology.
The new scheme results in significant reduction in the conduction losses of the Left leg
Mosfets too. For the same energy requirements during the freewheeling to power transfer
transitions, the current through the extra inductor, contributes much less to the average and rms.
switch currents compared to the magnetizing current of the transformer. This is so because, the
voltage across the inductor is a square wave and its current lags the reflected load current by
900. Figure 6.2 shows the inductor current and the reflected load current of the new scheme,
and compares them with the corresponding currents of the original scheme. From simulation it
is found that the conduction losses in the new scheme is less by about 40%, for a ZVS LIMIT
of 20% load.
VAB
VAB
I refl
Im
6
B
I refl
ILEX
6
Fig. 6.2 Comparison of the Original PMC scheme with the scheme shown in Fig. 6.1
(a) Reflected load current and Magnetizing current of the Original PMC scheme
(b) Reflected load current and External Inductor Current of the New scheme
An additional advantage of the new scheme is that the peak current through the
extra inductor is dependant on the input voltage, unlike the magnetizing current of the
transformer, which is constant for all input voltages. This is desirable, since the energy
required to discharge the Mosfet capacitances is also proportional to the input voltage.
6. 2. 2 Secondary Side Magamp Control [21]
As explained in Chapter 3, the reason for the Freewheeling to Power Transfer
Transition being critical, is that during this transition, the load reverses direction and hence
opposes the magnetizing current, in discharging the Mosfet capacitances. The scheme shown in
48
Fig. 6.3, uses magamps in the secondary side, to control the instant when the current reversal
begins.
V DC
C3
S3
MP
C1
D3
Dp
D1
Lo
S1
RL
Co
C2
S2
C4
D2
MN
D4
Dn
S4
Fig. 6.3. PMC with Secondary side Magamp Control
In Fig. 6.3, consider the freewheeling interval during which switches S1 and S3 conduct. In the
original PMC, as S3 is switched off the primary voltage becomes negative and the secondary
diode Dn begins to conduct. The reflected load current begins to fall sharply and reverses
direction. In the new scheme, the magamp switch MN is kept off till the discharge of C2 is
completed. This forces the diode Dp to continue to conduct the load current, and therefore the
reflected primary load current continues to flow in the same direction, aiding ZVS. Figure 6.4
shows the primary reflected load current during the freewheeling to power transfer transition,
for the new scheme. A detailed discussion on this scheme is given in [21]. .
Irefl
VAB
M 1 on
M 2 on
6
B
6
Fig. 6.4. Waveforms Corresponding to the Scheme shown in Fig. 6.3
49
6. 2. 3 Modified Rectifier Configuration [22]
In the scheme shown in Fig. 6.5a, the bridge rectifier is replaced by a modified
configuration, with two inductors. This circuit effectively modifies the apparent magnetizing
inductance of the transformer with the output filter inductors - L1 and L2. The reflected load
current is made to lag the primary voltage substantially, whereas with the conventional
rectifier circuits, the reflected load current is almost in phase with the voltage. Hence, in the
new scheme ZVS is achieved for a wider load range without the need for increasing the
magnetizing current of the transformer. Figure 6.5b, shows the waveforms corresponding to the
new scheme. A detailed explanation of the operation of this scheme and the practical
difficulties in implementing the same, are discussed in Reference 22.
VDC
C3
S3
Vo
C1
D3
D1
S1
R
Co
C2
S2
C4
D2
D4
S4
I L1
IL2
(a)
VAB
IL 2
I refl
IL1
(b)
Fig. 6.5 PMC with Modified Rectifier Configuration
(a) Schematic Diagram
(b) Corresponding Waveforms
50
6. 3 PMC WITH PRIMARY SIDE CLAMP DIODES [24]
As mentioned earlier, the large leakage inductance in the Phase Modulated Converter,
resonates with the junction capacitance of the secondary side diodes, resulting in excessive
ringing and voltage overshoots. Simple R-C snubber circuits connected across each diodes, are
not practical, since the energy associated with the oscillations is quite large [23].
A new scheme which clamps the peak ringing voltage non-dissipatively, is proposed in
Reference 24. In this scheme shown in Fig. 6.6, two clamp diodes are added in the primary
side. The transformer is designed to have minimum leakage inductance and the energy needed
for ZVS is derived mainly from the external inductor LR, connected in series. During the
transitions, the clamp diodes (DC) conduct, thus clamping the primary voltage to VDC. The
maximum diode voltage is therefore restricted to the reflected input voltage.
VDC
DC
Dp
Vo
L
T
LR
IL
Co
DC
Dn
Fig. 6.6 . PMC with Primary Side Clamp Diodes
51
CHAPTER 7
CONCLUSIONS
The scope of this work was,
To investigate the suitability of the Phase Modulated full-bridge Converter [PMC], for
high frequency SMPS applications.
To develop practical Design Methods for the above converter.
To experimentally verify the analytical results and the design methods developed.
The motivation for this study were the following promises of PMC.
1. Zero Voltage Switching (ZVS), without compromising much on the device stress or the
conduction loss.
2. Constant frequency operation with its attendant benefits.
3. Possibility of achieving ZVS, using the parasitic elements alone (without the need for
extra components like resonating L and C as in resonant converters).
The operation of the PMC was analysed by identifying the various distinct intervals in a
complete cycle and deriving the equivalent circuits and governing equations valid in each of
the intervals. These equations were used to numerically simulate the converter. From extensive
simulation, the steady-state and dynamic performance of the converter were obtained. In
particular, the various factors affecting the ZVS characteristics were studied in detail. Some of
the important findings are as follows.
Zero Voltage Switching can be achieved by proper design of the magnetizing and leakage
inductances of the transformer. Output control by Phase Modulation makes it possible to
operate at constant switching frequency.
The ZVS characteristics of PMC are load dependent - it is easy to achieve ZVS at higher
loads. If ZVS is desired at light loads also, then the magnetizing current and / or the
leakage inductance of the power transformer have to be increased, resulting in higher
conduction losses.
For satisfactory performance over the entire load range, compromise has to be made
between the switching losses at light loads and the conduction losses at higher loads.
ZVS LIMIT, defined as the load down to which ZVS is achieved, represents this
compromise. Optimum choice for the ZVS LIMIT depends on many factors like the
switching frequency, the range of line and load variations, Mosfet characteristics etc.
Loss curves obtained from simulation help in choosing satisfactory ZVS LIMIT, for a
given application.
More than the increase in magnitude of the instantaneous switch currents, the main
reason for the increase in conduction losses in PMC, compared to the PWM full bridge
52
converter, is the circulating currents in the primary switches during the freewheeling
interval. This increase is more pronounced in applications where the input variation, and
hence the variation in duty ratio, is wide.
In order to achieve satisfactory ZVS LIMITs, the core of the transformer needs to be
gapped to increase the magnetizing current and an external series inductor is usually
needed, to add to the leakage inductance of the transformer. Still, the ratio of Installed
VA to the Output power, in the case of PMC, is significantly lower than the resonant
converters of similar specifications.
The peak voltage stress of the devices is equal to the maximum DC link voltage, which is
the minimum possible with any topology. The peak current stress in PMC is slightly more
than the corresponding PWM topology, the exact difference depending on the chosen ZVS
LIMIT.
The constant frequency Phase Shift control of the PMC is similar to the duty ratio control
of the PWM topologies. Current mode control and Voltage feed-forward control are also
possible with the Phase Modulated Converter.
An interesting feature of the PMC is that, though it looks perfectly symmetrical, the left
leg Mosfets, which switch on / off during the freewheeling to power transfer transitions,
and the right leg Mosfets which switch on / off during the power transfer to
freewheeling transitions, operate under significantly different conditions. It is relatively
more difficult to achieve ZVS for the left leg Mosfets and hence the design of the
parameters affecting ZVS, has to be made considering the transitions from freewheeling
to power transfer mode.
The main design challenges in PMC are to choose the ZVS LIMIT and to obtain suitable
values for the parameters affecting the ZVS characteristics, namely the magnetizing and leakage
inductance of the transformer, capacitance across the Mosfets and the dead time allowed
between the turn-off of a Mosfet and the subsequent turn-on of the complimentary Mosfet in the
same arm [T Delay ] . Design equations to obtain suitable values for each of these parameters has
been derived and iterative use of simulation, with these values as the initial estimates, is
suggested, to obtain the most satisfactory design parameters. The design of output filters and
closed loop compensators is similar to that of PWM full bridge converter.
In order to verify the simulation results and to confirm the design methods, an Off-line
SMPS of 560 W rating (28V / 20A), based on the Phase modulation Controller IC - ML 4818,
was built. Though the aim was to study the performance of PMC in the 500 kHz to 1 MHz
range, non-availability of high frequency ferrite core material restricted the operation to 250
kHz. Even at this relatively low switching frequency, the advantages of PMC over the PWM
and the resonant converters were apparent. Some of the important experimental results are as
follows.
53
The design of the converter was made to obtain a ZVS LIMIT of 80% of full load
(obtained from simulation to get satisfactory performance over the entire load range). In
the actual converter ZVS was obtained from full load down to around 85% load,
confirming the validity of the design methods developed.
The total Mosfet losses at full load and maximum voltage was 3.9% of full load rating,
whereas the estimated losses for the PWM full bridge converter of similar specifications
was 7.2%.
The performance of the converter under various ZVS LIMITs were studied by varying the
magnetizing inductance (external inductor with many tappings). The results obtained
(mainly the Mosfet losses and current stress) matched closely with those predicted by
simulation.
Closed loop compensators designed on the same lines as that of the PWM full bridge
converter, was found to give the desired dynamic performance.
The overall efficiency obtained at full load was 82%. The losses in the secondary side
rectifiers alone accounted for more than 30% of the total losses. By using diodes with
lower forward drop, or better still, with synchronous rectifiers, and by using quality
high frequency core materials for the transformers and the primary inductor, efficiencies
above 90% is possible.
A main drawback of the PMC was the excessive ringing and voltage overshoot across
the secondary diodes, due to the resonance between the large leakage inductance and the
junction capacitance of the diodes. This problem was made more severe by the
inter-winding capacitance of the output filter inductor, which coupled this ringing to the
output, resulting in unacceptable noise in the output voltage. It is possible to use clamp
diodes in the primary side to limit the overshoot as suggested in Chapter 6.
No special efforts were made in the fabrication to achieve high power density. The
achieved power density of around 4W / in3, though significantly higher than the typical
power densities of the present commercial power supplies of similar specifications, falls
well short of what is possible with the Phase Modulated Topology at 250 kHz. With
hybridization, use of planar transformers and with more efficient heat removal
mechanisms, power densities in the range of 15 to 20W / in3 are possible.
Finally on the basis of simulation and experimental results, it may be concluded that at
power levels high enough to justify the use of four switches (approximately 500 W and above)
and at voltage levels high enough for the advantages of the ZVS to be significant, the Phase
Modulated full bridge Converter, with the proper choice of ZVS LIMIT, is potentially the most
suitable topology. Its advantages are more striking in applications where the range of input
variation is small. One such important application area is high power Off-line power supplies
with a front-end Power Factor Correction (PFC) scheme. Distributed Power Supply Systems
54
[26], where the raw input is regulated centrally to a standard voltage and then processed
further at the point of use, is another area where the PMC may be used most advantageously.
Considering the stringent demands on the input power factor of the Off-line power supplies and
with the increasing trend towards distributed power supply systems in many applications, it
may confidently be predicted that the PMC will be a standard topology of the future.
55
REFERENCES
1. A. I. Pressman, "Switching Mode Power Supply Design", McGraw Hill, 1992.
2. R. D. Middlebrook and S. Cuk, "Advances in Switched Mode Power Conversion
-Volumes 1 and 11" , Teslaco, 1983.
3. E. J. Miller, "Resonant Switching Power Conversion," IEEE Proc. Power Electronics
Specialist Conf. 1976 Record, pp 206-211.
4. R. L. Steigerwald, "A comparison of Half-Bridge Resonant Converter Topologies",
IEEE Trans. on Power Electronics, April 1988, pp 174-182.
5. K. Liu, R. Oruganti, F. C. Lee, "Resonant Switches - Topologies and Characteristics",
IEEE Trans. on Power Electronics, Jan 1987, pp 36-44.
6. S. Freeland, R. D. Middlebrook, "A Unified Analysis of Converters with Resonant
Switches", IEEE Proc. Power Electronics Specialist Conf. 1987 Record, pp 20-30.
7. G. Hua, C. leu, F. C. Lee, "Novel Zero Voltage Transition PWM converters", IEEE
Proc. Power Electronics Specialist Conf. 1992 Record, pp 55-61.
8. M .F. Schlecht, L. F. Casey, "Comparison of square wave and quasi-resonant
topologies", IEEE Trans. on Power Electronics, Jan 1988, pp 273-278.
9. A. Rajapandian, V. Ramanarayanan, "A Constant Frequency Resonant Transition
Converter", Journal of the Indian Institute of Science. (Submitted)
10. A. Rajapandian, V. Ramanarayanan, "A 250 kHz / 560W Phase Modulated Converter",
IEEE Proc. Power Electronics, Drives and Energy Systems (PEDES) Conf. 1996
Record.
(Selected for Presentation)
11. N. Mohan, Undeland and Robbins, "Power Electronics : Converters, Applications and
Design", John Wiley and sons, Newyork.
12. V. Vorperian and S. Cuk, " A Complete DC Analysis of the Series Resonant
Converter", IEEE Proc. Power Electronics Specialist Conf. 1982 Record, pp 85-100.
13. R. L. Steigerwald, "High frequency Resonant Transistor DC-DC Converters", IEEE
Trans. on Industrial Electronics, May 1984, pp 181-191.
14. V. Vorperian, S. Cuk, "Small signal Analysis of Resonant Converters", IEEE Proc.
Power Electronics Specialist Conf. 1987 Record, pp 424-430.
56
15. A. K. S. Bhat, S. B. Dewan, "Analysis and Design of a high frequency Resonant
Converter using LCC type commutation"' IEEE Proc. Industry Applications Society
Annual Meeting 1986 Record, pp 657-663.
16. K. H. Liu, F. C. Lee, "Zero Voltage Switching Techniques in DC-DC converters",
IEEE Proc. Power Electronics Specialist Conf. 1986 Record, pp 58-70.
17. W. A. Tabisz, F. C. Lee, "Zero-Voltage Switching Multi-Resonant Technique - A novel
approach to improve performanc
e of high frequency quasi-resonant converters",
IEEE Proc. Power Electronics Specialist Conf. 1988 Record, pp 9-17.
18. A. F. Goldberg, J. G. Kassakian, M. F. Schlecht, "Issues related to 1-10MHz
Transformer Design", IEEE Proc. Power Electronics Specialist Conf. 1987 Record.
19. V. Ramanarayanan, "Switched Mode Power Conversion", Class notes, Dept. of
Electrical Engg., Indian Institute of Science.
20. "Phase Modulated PWM topology with the ML 4818", Micro Linear Application
Note-19, June 1992.
21. R. Watson, F. C. Lee, "Analysis, Design and Experimental results of 1kW
ZVS-FB-PWM Converter employing Magamp Secondary side control", IEEE Proc.
Applied Power Electronics Conf. 1994 Record, pp 166-172.
22. W. A. Peterson et al, "A clamped transformer power supply producing zero voltage
resonant transitions over the full load range", IEEE Proc. Applied Power Electronics
Conf. 1994 Record, pp 287-292.
23. L. H. Mweene et al, "A 1 kW 500 kHz front end converter for a distributed power
supply systems", IEEE Proc. Applied Power Electronics Conf. 1989 Record,
pp 423-432
24. R. Redl et al, "Optimum ZVS FB dc-dc converter with PWM Phase Shift control Analysis, Design considerations and Experimental results", IEEE Proc. Applied Power
Electronics Conf. 1994 Record, pp 159-165.
25. J. Sabate et al, "Design considerations for high voltage, high power, full bridge ZVS
PWM converter", IEEE Applied Power Electronics Conf. 1990 Record, pp 275-284.
26. J. G. Kassakian, M. F. Schlecht, "High-frequency High-density converters for
distributed power supply systems", Proc. of IEEE, vol. 76, April 1988, pp 362-376.
57
APPENDIX 1
Expressions for Primary Current and Capacitor Voltage during the Overlap Interval
LLk
B
Figure A.1, shows the equivalent circuit
Lm
+ C3
of the Phase Modulated Converter, during the V
DC
overlap mode in the fourth inverter interval. It
A
Ipri
n2
Lo
Co
R
Irefl
+ C2
is the same as Fig. 2.8b, except that the
secondary leakage inductances have been
Fig. A.1. Eq. Circuit of PMC in Overlap Mode
referred to the primary here.
Imo
:
magnetizing current at the start of the interval
Irefl o
:
reflected load current at the start of the interval
C
Leq
:
:
total capacitance across the Mosfet
L
Lm Lk
2.n2
Lm
LLk
:
Magnetizing inductance
Leakage inductance referred to secondary
IPr i
:
Im + Irefl
From the equivalent circuit shown above, it can be written,
VDC =
Leq d IPr i + VC
dt
2
(A.1)
−IPr i
dV
=
2C
dt C 2
(A.2)
Differentiating Eq. (A.1),
2
0 = − Leq d IPr i + d
dt
dt2
VC
2
(A.3)
From Eq. (A.2) and Eq. (A.3)
I
2
0 = − Leq d IPr i − Pr i
2C
dt2
Laplace Transforming Eq. (A.4),
(A.4)
58
0 = − Leq (s 2 Ipri (s) − sIpri (0) − d Ipri (0)) −
dt
where,
Ipri (s)
2C
(A.5)
Ipri (0) = Imo + Irefl o
d I (0) = 0
dt pri
Ipri (s) =
s (Imo +Irefl o )
s2 +
(A.6)
1
2C Leq
Ipri (t) = (Imo + Irefl o ) . cos ωt
where,
ω =
(A.7)
1
2C. Leq
From the equivalent circuit,
VC (t) =
2
Vdc + Leq d Ipri
dt
(A.8)
From Eqs (A.7) and (A.8),
VC (t) =
2
Vdc − (Imo + Irefl o )
L eq
sin ωt
2C
59
(A.9)