Sinusoidal Pulse Width Modulation (SPWM) With Variable Carrier
Synchronization for Multilevel Inverter Controllers
M.S.Aspalli.
Email-maspalli@yahoo.co.in
Anil Wamanrao
Email-awpatil01@gmail.com
Dept. of Electrical & Electronics Engineering
Poojya Doddappa Appa College of Engineering,
Gulbarga – 585102
switches permits the addition of the capacitor voltages, which
reach high voltage at the output, while the power
semiconductors must withstand only reduced voltages. Fig.1
shows a schematic diagram of one phase leg of inverters with
different numbers of levels, for which the action of the power
semiconductors is represented by an ideal switch with several
positions.
Abstract
Voltage or current converters generate discrete output
waveforms, which require large inductances connected in
series with the respective load to generate the desired current
waveform. Mostly, neither the voltage nor the current
waveforms are as expected and also have distorted voltages
and currents waveforms produces harmonic contamination,
additional power losses, and high frequency noise. In this
paper a method of minimization of THD with near to reference
current generation is proposed based on multilevel inverter. A
sinusoidal pulse width modulation scheme is developed for the
multilevel inverter.
Vc +
Vc
Vc
a
+
Va
Keyword: Multilevel Inverter, THD, sinusoidal pulse width
modulation, PWM converter.
(a)
I. Introduction
+
a
Vc
+
a
+
Vc
Va
(b)
Vc
Va
+
(c)
Fig 1: One phase leg of an inverter with (a) two levels, (b)
three levels, (c) n levels
Power electronics devices contribute important part of
harmonics in all kind of applications, such as power rectifiers,
thyristor converters, and static var compensators (SVC). Even
updated PWM techniques used to control modern static
converters such as machine drives, power factor compensators
or active power filters, do not produce perfect sinusoidal
waveforms, which strongly depend on the semiconductors
switching frequency. Normally, with voltage or current
converters, as they generate discrete output waveforms,
forcing the use of machines with special isolation, and in some
applications large inductances connected in series with the
respective load are required. In other words, neither the
voltage nor the current waveforms are as expected. Also, it is
well known that distorted voltages and currents waveforms
produce harmonic contamination, additional power losses, and
high frequency noise that can affect not only the power load
but also the associated controllers. All these unwanted
operating characteristics associated with PWM converters can
be overcome with multi-level converters, with the addition that
higher voltage levels can be achieved [1-5]. Multi-level
inverters can operate not only with PWM techniques but also
with Space Vector Control (SVC), improving significantly the
quality of the output voltage waveform. With the use of
amplitude modulation, low frequency voltage harmonics are
perfectly eliminated, generating almost perfect sinusoidal
waveforms, with a THD lower than 5%. Another important
characteristic is that each converter operated at a low
switching frequency, reducing the semiconductor stresses, and
therefore reducing the switching losses [6, 7].
A two-level inverter generates an output voltage with two
values (levels) with respect to the negative terminal of the
capacitor, while the three-level inverter generates three
voltages, and so on. The term multilevel starts with the threelevel inverter. By increasing the number of levels in the
inverter, the output voltages have more steps generating a
staircase waveform, which has a reduced harmonic distortion.
However, a high number of levels increases the control
complexity and introduces voltage imbalance problems.
Three different topologies have been proposed for multilevel
inverters: diode-clamped (neutral-clamped), capacitor-clamped
(flying capacitors) and cascaded multi-cell with separate dc
sources. In addition, several modulation and control strategies
have been developed or adopted for multilevel inverters
including the following: multilevel sinusoidal pulse width
modulation (PWM), multilevel selective harmonic elimination,
and space-vector modulation (SVM).
II. Multilevel Inverter
The most attractive features of multilevel inverters are as
follows.
1. They can generate output voltages with extremely
low distortion and lower dv/dt.
2. They draw input current with very low distortion.
3. They generate smaller common-mode (CM) voltage,
thus reducing the stress in the motor bearings. In
addition, using sophisticated modulation methods,
CM voltages can be eliminated [12].
4. They can operate with a lower switching frequency.
Multilevel inverters include an array of power semiconductors
and capacitor voltage sources, the output of which generate
voltages with stepped waveforms. The commutation of the
III. Multilevel Inverter Controller Design
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Fourier series analysis, the amplitude of any odd ‘nth’
harmonic of the stepped waveform can be expressed as,
To control the flow of power in the converter, the switches
alternate between two states. This happens rapidly enough that
the inductors and capacitors at the input and output nodes of
the converter average or filter the switched signal. The
switched component is attenuated and the desired DC or low
frequency AC component is retained. This process is called
Pulse Width Modulation (PWM), since the desired average
value is controlled by modulating the width of the pulses.
hn =
whereas the amplitudes of all even harmonics are zero. Where
Vk is ‘kth’ the level of dc voltage, ‘n’ is an odd harmonic order,
‘m’ is the number of switching angles, and αk is the ‘kth’
switching angle. According α1 to αm Fig 2, to must satisfy α1 <
α2 ....< αm < π/2. To minimize harmonic distortion and to
achieve adjustable amplitude of the fundamental component,
up to ‘m - 1’harmonic contents can be removed from the
voltage waveform. In general, the most significant lowfrequency harmonics are chosen for elimination by properly
selecting angles among different level inverters, and highfrequency harmonic components can be readily removed by
using additional filter circuits. According to (4), to keep the
number of eliminated harmonics at a constant level, all
switching angles must be less than π/2. However, if the
switching angles do not satisfy the condition, this scheme no
longer exists. As a result, this modulation strategy basically
provides a narrow range of modulation index, which is its
main disadvantage.
Two requirements which all low pulse number PWM
candidates should observe are synchronism with the
fundamental frequency and quarter and half wave symmetry.
Synchronism with the fundamental frequency means ensuring
the switching frequency fc is an integer multiple of the
synthesized fundamental frequency f1. That is, the pulse
number N = fc / f1 must be an exact integer. The frequency
spectrum of the PWM waveform will then consist of discrete
frequencies at multiples of the fundamental frequency nf1,
where n is an integer.
Quarter and half wave symmetry ensures that no even
harmonics will exist in the output spectrum. This can be
achieved by choosing N odd. An important even harmonic
which is eliminated is the DC component.
No frequency components below the fundamental frequency
(commonly referred to as sub-harmonics) will exist. This is
important since an undesired harmonic component near zero
frequency, even if small in amplitude, can cause large currents
to flow in inductive loads.
V. Sinusoidal Pulse Width Modulation (SPWM) for
multilevel inverter.
SPWM for Multilevel Inverter is based on classic two level
SPWM with triangular carrier and sinusoidal reference
waveform.
The modulation methods used in multilevel inverters can be
classified according to switching frequency. Methods that
work with high switching frequencies have many
commutations for the power semiconductors in one period of
the fundamental output voltage. A very popular method in
industrial applications is the classic carrier-based sinusoidal
PWM (SPWM) that uses the phase-shifting technique to
reduce the harmonics in the load voltage. Another interesting
alternative is the SVM strategy, which has been used in threelevel inverters.
(a)
(b)
Fig 3 (a) Vertically shifted carriers
(b) Horizontally shifted carriers
Methods that work with low switching frequencies generally
perform one or two commutations of the power
semiconductors during one cycle of the output voltages,
generating a staircase waveform. Representatives of this
family are the multilevel selective harmonic elimination and
the space-vector control (SVC).
IV. Selective Harmonic Elimination
Only difference between two level SPWM and multilevel
SPWM is, numbers of carriers are used in multilevel SPWM.
For ‘m’ level inverter ‘m-1’ carrier are used. Interaction of
particular carrier and reference is used to generate gating
signal for particular complementary pair of switches in diodeclamped or capacitor-clamped inverter, or particular cell in
multi-cell inverter.
Vo
Vm
V2
V1
α 1 α 2 αm π
2
π
3π
2
4 m
∑[Vk cos(nαk )]
nπ k = 1
Carriers used in multilevel inverter may be vertically shifted or
horizontally shifted as shown in Fig 3(a),(b). Advantage of
horizontally shifted carriers scheme is that, each modules are
switched on and off with a constant number of times by
period, independently of magnitude of generated voltage. But
vertically shifted carrier scheme can be more easily
implemented on any digital controller.
2π
Fig 2 Generalized Stepped-Voltage waveform
Fig 2 shows a generalized quarter-wave symmetric stepped
voltage waveform synthesized by a (2 m + 1)-level inverter,
where ‘m’ is the number of switching angles. By applying
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In asymmetrical sampling, the reference signal is sampled at
positive as well as negative peak of carrier frequency and held
constant for half the carrier period. Here sampling frequency is
twice the carrier frequency. Asymmetrical sampling is the
preferred method, since each switching edge is the result of
new sample and give better performance as shown in Fig 6.
The phase shift is by π .
Vertically shifted scheme comes with three variant, as shown
in Fig 4 (a), (b) & (c)
1.
2.
3.
4.
All carriers are in phase (PH disposition)
All carries above the zero reference are in phase, but
in opposition with those below (PO disposition)
All carriers are alternatively in opposition (APO
disposition)
All carriers are shifted by 900.
2mf
vc
vm
Natural Sampling
Asymmetrical
Sampling
Fig. 4 (a) PH
(b) PO
(c) APO
Fig 6. Natural sampling ,asymmetrical sampling.
The PH technique produce less harmonics on a line-to-line
basis compared to other two techniques because it puts
harmonic energy directly into a common mode carrier
component which cancels across the line-to-line output.
Comparing natural SPWM and digital SPWM, digital SPWM
has following disadvantages,
1. Digital SPWM method sample the signal input at the
beginning of the switch cycle, before the actual switching
edge reflects this value later in the cycle.
2. This introduce a delay in out-put waveform. A delay of
π
π
and
is introduce in symmetrical and
mf
2 mf
asymmetrical sampling method respectively , where mf is
frequency modulation ratio
3. This delay in response is significant when the ratio of
switch frequency to reference frequency (the pulse
number) is small. It leads to a frequency response roll-off
which obeys a Bessel function, similar to the familiar sine
function roll-off for Pulse Amplitude Modulation (PAM).
4. Another unwanted effect of digital SPWM is odd
harmonic distortion of the synthesized waveform. The
severity of these effects is a function of the ratio of the
modulating and carrier frequencies, f1/fc. This ratio may
approach and pass unity in high power active filters (high
f1, low fc), by which point these effects have become
significant and limiting.
For five level inverter, four carriers (C1 – C4) divides whole
modulating voltage into four region r1 to r4 as shown in Fig 3
(a). Lower order harmonics can be shifted to higher order by
increasing carrier frequency. However, it is not possible to
improve the total harmonic distortion without using output
filter circuit. Switching frequency in SPWM is equal to carrier
frequency therefore switching losses are high.
VI. Implementation of SPWM Technique
Digital implementation SPWM technique is based on classical
SPWM technique with carriers and reference sine waveform.
Only difference between them is, in digital SPWM a sine table
consisting of values of sine waveform sampled at certain
frequency is used. As result reference wave form in digital
SPWM represents a sample and hold waveform of sine wave
forms.
This sampling of sine waveform comes in two variants; a)
Symmetrical sampling, b) Asymmetrical sampling.
In proposed model, magnitude of modulating signal at
crossover instant is calculated at interval of Ts/2 at each peak
of carrier frequency. kth sample give the value
In symmetrical sampling, reference sine waveform is sampled
at only positive peak of the carrier waveform and sample is
held constant for the complete carrier period. This introduces
the distortion in modulating signal and phase shift between
modulating signal and fundamental component of output
voltage. Here sampling frequency is equal to carrier frequency.
The phase shift is given by π , where
m
Reference
f
fc
mf =
fm
Ts
tk
tk+ Δ tk
fc = Carrier frequency .
fm = Reference Sine wave frequency.
vc
Mathematically Modulated
Reference
Carrier
tk+1
(tk+1)+ Δ (tk+1)
Fig 7 Scheme for proposed SPWM method.
vm
of the discrete time signal tk = kTs/2 where k is integer.
Extrapolation process is carried out to find the intersection of
modulating signal.
Natural Sampling
As shown in Fig 7 there is time delay Δtk between sampling
instant tk and actual crossing of natural sine waveform and
triangular carrier waveform tk+Δtk. Because of this time delay
there lies a phase delay in output waveform as shown in Fig 6.
If this time delay Δtk can be calculated then instead of using
Symmetrical
Sampling
Fig.5 Natural sampling, Symmetrical Sampling
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sampled value of sine waveform at time instant tk for
comparing with carrier, a sampled value of sine waveform at
tk+Δtk can be used. This will give exact crossing instant of
sampled and hold waveform of natural sine with carrier as
with natural sine waveform, as shown in Fig 7. So there will
be no phase delay in output waveform.
from region r = 0 are use to drive switch S2 and
complementary signal are use to drive S’2 , Signal from region
r = -1 are use to drive switch S3 and complementary signal are
use to drive S’3 , signal from region r = -2 are use to drive
switch S4 and complementary signal are use to drive S’4 .
Formula for finding time delay 'Δtk' for positive and negative
slop for different shifted carrier can be found by extending
case for two level inverter.
Procedure of calculating this time delay Δtk is as follows,
Consider reference signal as,
Vr (t ) = maVm sin(ωm t )
Transition from one region of operation to the other can be
decided on the basis of calculated vale of 'Δtk'. To decide the
transition from one region to other the criterion of transition
for positive slope carrier cross-over is
If Δtk > 1/2fc, then transition is form lower region to upper
region, so r new = r old + 1 (where r = region)
(2) If Δtk < 0, then transition is from upper region to lower
region, so r new = r old - 1
Similarly, to decide the transition from one region to other the
criterion for negative slope carrier cross-over is
If Δtk > 1/2fc,Then transition is form upper region to lower
region, so r new = r old – 1.
(2) If Δtk < 0 Then transition is from lower region to upper
region, so r new = r old + 1
Where
ma = modulation index .
Vm = Peak value of Reference signal .
ωm = 2 π f m .
fm = fundamental frequency of reference signal .
tk = Time instant at which sine wave form is sampled.
Carrier signal equation for positive slope and negative slope,
Vc
2
Vc
Vc ( N _ S ) = −2Vc fc t +
2
Vc ( P _ S ) = 2Vc fc t −
Vc = Peak value of carrier signal.
fc = Frequency of carrier signal .
VII. Results Observation
The value of 'Δtk' can be found simply by equating values of
reference signal and rising edge (positive slope) of carrier
signal at instant of intersection (i.e. tk+Δtk), and of reference
signal and falling edge (negative slope) of carrier signal at
instant of intersection (i.e. t(k+1)+Δt(k+1)).
Different modulation scheme for multilevel inverter are
explained under the heading Multilevel Inverter. Of these
different schemes a) Selective Harmonic elimination b)
SPWM method are simulated.
In SPWM method of modulation for multilevel inverter (m-1)
numbers of carriers are used. Arrangements of these carriers
come with different variants. Fig. 9 gives (a) carrier
arrangement, (b) output voltage and (c) FFT for PH disposition
(All carriers are in phase) SPWM method for 5-level inverter.
(fc = 1050 Hz, fm = 50 Hz).
With determination of value Δtk sampled signal is modified
with maVm sin ωm (tk + Δtk ) and held constant for a
period of Ts/2, which will give exact crossing of this modified
signal and carrier as that with natural sine signal thus
producing no phase delay in output wave form.
The allocation of proposed mathematical model can be
extended to multilevel inverter. The only difference in above
procedure and procedure for determination Δtk in case of
multilevel inverter is that, as numbers of carriers are used in
multilevel inverter, exact region of interaction of reference and
carrier is to be known. In other word region of operation and
transition from one region to other region should be
determined.
Ca
rri
er
an
d
sig
nal
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
Fig 8 shows the reference and carrier waveform arrangements
necessary to achieve PD SPWM for a five level inverter. Each
shifted carrier is consider as one region.
0
0.005
0.01
Time(sec)
0.015
0.02
(a)
200
150
Output Voltage (SPWM)
r=1
r=0
r = -1
100
50
0
-50
-100
-150
r = -2
-200
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
Time (sec)
(b)
Fig 8. Distribution of regions for proposed SPWM
For example for five level inverter region are r = 1, 0,-1, -2.
Signals from region r = 1 are use to drive switch S1 and
complementary signal are use to drive S’1, similarly signal
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2
1.5
1
Carrier
0.5
0
-0.5
-1
-1.5
-2
0.02
0.025
0.03
0.035
0.04
Time (sec)
(a)
(c)
Fig. 9 (a) carrier arrangement, (b) output voltage and (c) FFT
for PH disposition (All carriers are in phase)
200
150
100
Output Voltage
Fig. 10 gives (a) carrier arrangement, (b) output voltage and
(c) FFT for PO disposition (All carries above the zero
reference are in phase, but in opposition with those below )
SPWM method for 5-level inverter.(fc = 1050 Hz, fm = 50 Hz).
50
0
-50
-100
-150
-200
0.02
0.025
0.03
0.035
0.04
0.045
0.05
0.055
0.06
Time (sec)
2
(b)
1.5
1
C
a
rrie
r
0.5
0
-0.5
-1
-1.5
-2
0.02
0.025
0.03
0.035
0.04
Time (sec)
(a)
200
150
Output Voltage
100
50
(c)
0
-50
Fig. 11 (a) carrier arrangement, (b) output voltage and (c) FFT
for APO disposition (All carriers are alternatively in
opposition)
-100
-150
-200
0.02
0.025
0.03
0.035
0.04
0.045
0.05
0.055
0.06
(b)
Fig. 12 gives (a) carrier arrangement, (b) output voltage and
(c) FFT for SPWM method for 5-level inverter where carriers
are shifted by 90о with respective to each other. (fc = 1050 Hz,
fm = 50 Hz)
2
1.5
1
C
arriers
0.5
0
-0.5
-1
(c)
-1.5
-2
0.02
Fig. 10 (a) carrier arrangement, (b) output voltage and (c) FFT
for PO disposition (All carries above the zero reference are in
phase, but in opposition with those below )
0.025
0.03
0.035
0.04
Time (sec)
(a)
200
150
Fig. 11 gives (a) carrier arrangement, (b) output voltage and
(c) FFT for APO disposition (All carriers are alternatively in
opposition) SPWM method for 5-level inverter.(fc = 1050 Hz,
fm = 50 Hz)
Output Voltage
100
50
0
-50
-100
-150
-200
0.02
0.025
0.03
0.035
0.04
0.045
0.05
0.055
0.06
Time (sec)
(b)
5
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[4] Keith Corzine, and Yakov Familiant, “A New Cascaded
Multilevel H-Bridge Drive”, IEEE Transactions on Power
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(c)
Fig. 12 (a) carrier arrangement, (b) output voltage and (c) FFT
for SPWM method for 5-level inverter where carriers are
shifted by 90о
Table.1 Comparison different SPWM methods for Multilevel
Inverter.
Comparison of SPWM method for Multilevel inverter
Method
THD (%)
1
PH
21.96
2
PO
21.85
3
APO
21.89
4
Carrier shift (90о)
21.28
VIII. CONCLUSION
For controlling multilevel inverter different modulation
scheme are used. Of these different modulation schemes
SPWM method has gained more interest in industrial
application. The same can be implemented using hardware.
Mainly DSP or microcontroller based controller are preferred
over analog controller for implementing SPWM scheme for
multilevel inverter. But DSP based
scheme such as
symmetrical sampling, asymmetrical sampling or regular
sampling method either produce phase delay in generated
output waveform or required dedicated processor for
continuous sampling. In this work a mathematical model based
SPWM scheme is proposed which calculate exact instant of
crossing of reference sine waveform with carrier signal and
modify sampled value of reference signal based on this
information to achieve performance same as that with natural
SPWM. Results obtain from MATLAB simulations validate
the proposed scheme which give better performance of
proposed scheme over the other scheme on the basis of output
phase delay and output THD.
1993.
M.S.Aspalli received the B.E. degree in
electrical engineering and M.E. in Power Electronics in
the 1991 and 1997 respectively. He started his carrer as
lecturer in electrical department at P.D.A.College of
Engineering,Gulbarga,Karnataka and now working as
Asst Professor in the same college. He is the life member
of Indian Socity for Technical Education, the Instution of
electronics and Telecommunication Engineers and Indian
socity of lighting engineers.
IX. REFERENCES
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Breed Power Converter,” IEEE IAS Annual Meeting
Conf. Record, pp. 2348-2356, 1995
[2] Rodríguez, J., Lai J-S., Zheng Peng, F., “Multilevel
Inverters: A Survey of Topologies, Controls,and
Applications”, IEEE Transactions on Power Electronics,
Vol. 49, No.4, August 2002, pp.724-737.
[3] M. Manjrekar and G. Venkataramanan, “Advanced
topologies and modulation strategies for multilevel
inverters,” Conference Record of the IEEE-PESC, 1996,
pp. 1013-1018.
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