NEW ASYMMETRICAL HYBRID MULTILEVEL VOLTAGE INVERTER
Domingo Ruiz-Caballero *, Luis Martinez*, Reynaldo Ramos A.*, Samir A. Mussa**
*Pontificia Universidad Católica de Valparaíso - School of Electrical Engineering – EIE - Power Electronic Laboratory – LEP
Valparaíso, CHILE - Phone: +56-32-2273695 - e-mail: domingo.ruiz@ucv.cl
**Federal University of Santa Catarina - Power Electronics Institute – INEP - Florianópolis – SC – BRAZIL
Phone: +55-48-3721.9204- e-mail: samir@inep.ufsc.br
Abstract – This article presents the study and
implementation of a new asymmetric hybrid voltage
inverter, for high voltage applications. The proposed
inverter employs two types of modulation in low and high
frequency (sinusoidal PWM). Simulations and
experiment results are provided showing the validity of
the analyses. These were obtained using a low-voltage
single/three-phase prototype that demonstrated its
operation.
I. INTRODUCTION
The multilevel inverters have become popular in high
power and high voltage applications. The work shown in [1]
was the first to submit a topology known as asymmetric
hybrid multilevel inverters. The inverter belongs to the
family of hybrids [5] which means it is composed of switches
of different technologies (MOSFET and GTOS, for instance)
and strategies for several modulation (PWM Pulse single,
sinusoidal). The inverter is also known as asymmetric, since
it has power supplies of different values. In this study is a
circuit configuration with binary sources of voltages, is
described similar to the inverter studied in [1, 3, 4, 7], but
proposed as an alternative.
1
1
S1,S4
3E
S1
S3
2E
S2
S4
S1
S3
S2
S4
S2
S3
Is proposed in [5, 8] a new topology that derives from a
DC-DC three-level buck converter. The proposal differs from
this cell by the peculiarity of having a binary distribution of
the voltage sources. Fig. 1(a) shows the distribution
topological while Fig. 1(b) shows the possible voltage levels
that can be obtained at the voltage output of the cell. In
general the voltage produced by the inverter is governed by
equation (1) where `n` is the amount of sources in each of the
TC (three-level cells), with the value increasing
exponentially (E, 2E, 4E ,...).
2n
vab (t)
E
II. SINGLE–PHASE HYBRID ASYMMETRICAL
MULTILEVEL INVERTER
m
(a)
(1)
In Fig.2, a change in the circuit allows the reversal of the
voltage produced in TC. To obtain an alternating voltage is
connected between points ‘a’ and ‘b’ an inverter type Hbridge. Using a differentiation approach, a signal can be
obtained at the output of alternating between points ‘a’ and
‘b’.
t
0
(b)
Fig 1. (a) Five-level cell (TC), (b) waveform of the voltage
between a and b
The switches S1, S2, S3, and S4 produce a unipolar
waveform as shown in Fig. 1(a), while the switches SH1,
SH2, SH3 and SH4 generate an alternate output voltage for
each cycle of operation of switches S1 to S4. Fig. 2(b) shows
the output signal of the inverter, resulting in effectively seven
voltage levels. Fig. 2(c) shows the three-phase version of the
proposed circuit. The advantage is that the switches S1, S2,
S3, and S4 can operate at higher frequencies can be
MOSFETs or IGBTs and will withstand 2E, for S1, S2, and
E for S3, S4 voltage level, while SH1, SH2, SH3 and SH4
often operate at the main frequency, so the switches are slow
as the GTO or IGCTs must withstand whole DC-link voltage.
There are situations where the voltage levels in the load
are not reached. Equation (3) sets a minimum rate of
modulation which can be obtained in an inverter of seven
levels.
O
S1a
2E
DS1a
S7a
DS7a
S2a
DS2a
S5a
DS5a
S8a
DS8a S3a
DS3a S6a
DS6a
E
DS1b
S7b
DS7b
S2b
DS2b
S5b
DS5b
S8b
DS8b S3b
DS3b S6b
DS6b
S1c
2E
E
S4a
(a)
2E
S1b
DS1c
S7c
DS7c
S2c
DS2c
S5c
DS5c
S8c
DS8c S3c
DS3c S6c
DS6c
E
DS4a
S4b
DS4b
S4c
DS4c
Inverter leg
V
U
W
vA´B´ (t)
S1,S4
3E
S1
S3
2E
S2
S4
E
S1
S3
N
(a)
S2
S4
SH2
SH3
S2
S3
t
0
SH1
SH4
-E
-2E
-3E
S4
S2
S4
S2
S3
S1
S3
S1
S1,S4
Fig. 2. (a) Single-phase asymmetrical hybrid multilevel inverter, (b)
Output voltage waveform.
(b)
III. THREE-PHASE HYBRID ASYMMETRICAL
MULTILEVEL INVERTER
If three single-phase outputs are connected, so that they
feed a three-phase load in star connection, then the outcome
would be a three-phase symmetrical hybrid multilevel
inverter, as shown in Fig. 3.
The modulator is composed of three sinusoidal reference
signals shifted by 120º from each other, compared to three
carrier signals in phase disposition (PD). The common point
of the inverters is called ‘o’, whereas the common point of
the load star connection will be named ‘N’. The connection
points between each single-phase inverter and the load will
be called ‘U’, ‘V’ and ‘W’.
IV. MODULATION STRATEGY
In general the inverters are modulated by pulse width
modulation (PWM), or the pulses are generated comparison
of a signal modulator with the carrier. Often for converters
with “m” voltage levels and “m-1” carriers, the carriers are
defined with the same frequency (fc) and amplitude (Ac).
The amplitude of the modulator is denoted as (Am) and the
frequency (fm). The index of modulation, given by equation
(2), relates to initially the magnitude of the modulator with
respect to a carrier (mi) and finally respect to three carriers in
Phase Disposition (ma).
Am
Am
mi
, ma
(2)
1 Ac
m
AC
(c)
Fig. 3. (a) Three-phase asymmetrical hybrid multilevel inverter.(b)
Load- phase voltage and (c) line-to-line voltage waveforms in
steady state.
m 3
(3)
m 1
In this inverter a limit of modulation is given at 66.6%,
below you lose a voltage level. Another point is at 33.3%
which is lost the second voltage level, see Fig. 4. There is
another concept that is the index of frequency often given by
the equation (4) and which is defined as the ratio of the
frequency of the carrier with respect to the modulator. This
index is always greater than one.
fc
mf
(4)
fm
mamin
The modulations strategy for driving the switches is based
on the sinusoidal PWM modulation with phase disposition
(PD) [2] [6]. This technique requires (m-1) carriers to get (m)
voltages levels in the output of the cell. Each of these carriers
is in phase, but displaced vertically with a value equal to its
maximum. The circuit used in the generation of pulses of
commands of switches is shown in Fig. 5. In Fig. 4, shows
the different waveforms of the output voltage of three
different rates of modulation.
S1
S2
VP1
E3
VP2
E2
VP3
E1
S3
S4
(a)
VM
Fig. 5. Command circuit for the switches for modulation PWMS.
By the way as modulated is, without phase-shifting of the
carriers, the order of the harmonics generated by the
converter in the output voltage will depend, such as occur
with the two levels sinusoidal PWM, of the rate of frequency
(mf) , i.e., if mf is even number, it will generate even and
odd harmonics, and if mf is odd, will generate only odd
harmonics.
V. SPECTRAL ANALYSIS OF THE LOAD VOLTAGES
(b)
In order to analytically define the load voltages spectra
and their THD, this section shows the derivation of the
expressions for, both, single-phase and three-phase
converters. For the analysis was assumed that the carriers are
delayed 120 degrees with each other. However can be
observed that the mathematical outcomes obtained are a good
approximation of reality, simulation and experimental results
are provided showing the validity of the analyses.
A. Single-Phase Load Voltage Analysis
The load voltage for the single-phase multilevel converter
is given by,
vab (t )
E mi sin(
1
t)
n
2E
Jn
n
,n
mi
sin
sin
1
ti
1
(5)
n s ti
ti n s ti
Where JV(.) represents the Bessel function of v order.
Being this equation a good approximation for the output
voltage.
TABLE I
Amplitude of the load voltage harmonic components
Fig. 4. Signal of control and output voltage of the inverter for an
index of modulation of (a) 0.85, (b) 0.5 and (c) 0.3.
Harmonic
Fundamental A1
Amplitude
Components An,v
n= 2,4,6…
v=1,3,5
2E
Jn ,n
n
A1
Frequency
Emi
1
mi
v
1
n
s
When watching the equation (5) it is possible to see that
the harmonic components exist in side-bands ( 1) around
multiple of the switching frequency ( s). Fig. 6(a) is a plot
of the previous equation normalized with respect to ‘E’. The
peak amplitude of the harmonic components of the inverter
output voltage and their harmonic frequencies are exposed in
Table I and are graphically shown as a function of the
modulation index mi in Fig.6 (b). The harmonics components
are obtained from h=n.mf ± .
2
2
P
cos
v n
cos 2
v n
cos
v n
cos 2
v n
s en
v n
s en 2
v n
s en
v n
s en 2
v n
2
(7)
2
(8)
And,
2
2
N
Moreover;
tg
1
P
tg
1
N
s en
v n
2 cos
v n
s en 2
v n
cos 2
v n
s en 2
v n
cos 2
v n
(9)
And,
s en
v n
2 cos
v n
(10)
The maximum amplitude of the harmonic components of
the load-phase voltage and their frequencies are given in
table II and plotted in Fig. 7(b). Fig. 7(a) is a plot of the
previous equation normalized with respect to ‘E’.
TABLE II
Amplitude of the load-phase voltage harmonic
components
Harmonic
Fundamental A1
Harmonics Amplitude
Frequency
1
E mi
3
A1
Components An,v,
Bn,v,
n= 1,2,3…
v=1,3,5…
(a)
An,v/E
3.0
Amplitude
1
2E
J v n mi M P
3n
2E
J v n mi M N
3n
An, v
Bn , v
v
1
n
s
v
1
n
s
On the other hand, the expression that defines line-to-line
voltage is given by (11).
2.7
2.4
A1
2.1
vuv t
1.8
3 mi sen
t
1
6
n 1 v , impar
2
J v n mi
n
N P sen v
t n
1
N N sen v
n
1t
s
t
(11)
P
st
N
With:
1.5
NP
2 1 cos
v n
(12)
NN
2 1 cos
v n
(13)
1.2
0.9
A1,1
0.6
A1,2
A2,1
A1,3
0.3
P
0
0.6
1.8
1.2
Fig. 6.(a) Single-Phase Output voltage of the inverter for mf=32.
Graph obtained from eq. (5), taking account until n=30 and v=31,
i.e. h=991. (b) Harmonic components amplitude of the voltage Vab:
A1 = fundamental component, An,v = frequency harmonic (v.w1
n.ws); n = 2, 4, 6...; v = 1, 3, 5,...It can be seen that A1,1 represents
the harmonics h=31 and 33, being these the lower order.
B. Three-Phase Load Voltage Analysis
The equation that defines the load-phase output voltage is
given by (6).
(6)
n st P
1
2
P sen v 1t
mi sen
With:
t
1
n 1 v , impar
3n
cot
v n
2
N
tg
1
cot
v n
2
(14)
With
(b)
3
1
2.4
mi
vun t
tg
J v n mi
N
sen v 1t n
s
t
N
2
3
(15)
In Fig. 8(a) is a plot of the previous equation normalized
with respect to ‘E’. The peak amplitude of the harmonic
components of the line-to-line voltage and their frequencies
are tabulated in Table III and are displayed in function of the
modulation index ´mi´ in Fig. 8(b).
Also were obtained the expressions of the harmonic
distortion of voltages. The equation 16 shows the THDv of
line-to-line voltage and the equation 17 shown the THDv of
phase-load voltage, both are shown by Figure 9(a) and (b).
(b)
(a)
An,v/E
Bn,v/E
An,v/E
Bn,v/E
Harmonics Amplitude
2.7
2.4
A1
2.1
A1
1.8
1.5
1.2
0.9
A1,1
B1,3
0.6
B1,1
0.3
0
0.5
1.0
A1,1
B1,1
A2,3
1.5
2.0
B1,3
A2,1
A1,3
2.5
mi
Fig. 7. (a) Load-Phase Output voltage of the inverter for mf=32.
Graph obtained from eq. (6), taking account until n=100 and v=41,
i.e. h=3241. (b) Amplitude of the harmonic components of the
load-phase voltage of inverter: A1 = fundamental component, An,v =
v 1 n s , Bn,v = v 1 n s . It can be seen that A11 represents the
harmonic 33 and B13 the harmonic 29.
5,... A11 represents the harmonic 33 and B11 the harmonic 31.
TABLE III
Amplitude of the line-to-line voltage harmonic
components
Harmonic
Fundamental A1
Amplitude
A1
Components An,v,
Bn,v,
n= 1,2,3…
v=1,3,5…
An, v
Bn , v
2
THDvUV
n
100
n
v
THDvUN
3 E mi
2
3 n
100
Frequency
n
v
v
1
s
1
n
s
2
N P v, n
2
3 mi
2
N N v, n
2
M P v, n
2
M N v, n
2
(17)
2
THDv UV
THDv UN
n
2
J n v, n, , mi
1
mi
3
v
1
2E
J v n mi N P
n
2E
J v n mi N N
n
J n v, n, , mi
Fig.8. (a) Line-to-line voltage of the inverter for mf=32. Graph
obtained from eq. (11), taking account until n=100 and v=41, i.e.
h=3241. (b) Amplitude of the harmonic components line-to-line
voltage inverter: A1 = fundamental component, An,v = harmonics at
the frequency v 1 n s , Bn,v = v 1 n s ; n = 2, 4, 6...; v = 1, 3,
(16)
mi
(a)
mi
(b)
Fig.9. (a) THDv to load-phase voltage and at (b) THDv to Line-toline voltage of the inverter.
VI. SIMULATION RESULTS FOR SINGLE-PHASE
ASYMMETRICAL HYBRID INVERTER
In this section the results obtained by digital simulations
for the single phase and three-phase circuit with PD-PWM
modulation. Consider all the components ideals, with the
following designs specifications:
3E
Vl
1.5[ kV ]
PO
54[ kW ]
f red
1.275[ kV ]
RL
12[ )
LL
50[ Hz ]
18.51[mH ]
Cos ( )
f port
0.9
m a 0.85
4[ kHz ]
To check the operation of asymmetric hybrid multilevel
inverter is performed simulations with the proposed
modulation. In Fig. 10(a) it is possible to observe that the
single-phase voltage has seven levels, -1.5 kV, -1 kV, -0.5
kV, 0, 0.5 kV, 1 kV and 1.5 kV. The magnitude of
fundamental component is 1.27 kV with a distortion of a
19.46%. Regarding the harmonic spectrum can be observed
in Fig. 10(b) higher order of the components appear at 4 kHz
and only in side-bands on multiple frequencies of the carrier
frequency.
Also it presents simulation results from the three-phase 7level converter. The simulation specifications are the same as
given before except that the total output power is multiplied
by three and the carrier frequency was 1.6 kHz. In Fig. 11
shows the load voltages obtained in the simulation. The
phase voltage vRN at the load presents fifteen levels as seen
in Fig. 11(a), while the line voltage vRS presents eleven
levels. From the simulation were obtained that line-to-line
voltage has a THDv of 20.22% and load-phase voltage has a
THDv of 20.28% taking a maximum of 100 harmonics.
(a)
(b)
Fig. 10. (a) Output voltage of the single-phase inverter, (b)
harmonic spectrum of the output voltage.
(a)
(b)
Fig. 11. (a) Phase-load voltage, (b) and Line-to-Line voltage of the
three-phase inverter.
It is possible to appreciate that the voltage stress are
different among the switches. We can see that the fast
switches; S1 and S2 must withstand ´2E´ of reverse voltage,
S3 and S4 must withstand ´E´, while on the other hand, the
H-bridge switches (SH1, SH2, SH3 and SH4) must block a
higher voltage level of ‘3E’. However, these switches operate
only in one cycle of the output voltage. Thus, they operate at
low frequency commutating at zero voltage.
From the viewpoint of the current sharing; is that the RMS
current levels in the switches are based as a function of angle
of load. For resistive loads the sharing of current becomes
asymmetrical and the switches, S1 and S3, carry a large
percentage of the total current, this distribution tends to be
uniform for inductive loads. For the H-bridge, besides, the
distribution will be function of the angle of loading, but is
not as asymmetrical as in the case of fast switches. From the
viewpoint of the conduction loss it is clear that S1 will be
who will have a higher level of losses, since it must
withstand 2/3 of the DC-link voltage and moreover this leads
a large amount of current.
VII. EXPERIMENTAL RESULTS
To validate the operation of the inverter, an experimental
prototype of the single/three-phase multilevel inverter was
built with the following specifications: 2E =100V and E =
50V, 300 W of output power, operating at 1500 Hz
frequency switching and the fundamental frequency of 50
Hz. The switches used to cell TC were IRF840A MOSFET
and the bridge IRGP30B60KD-E. The modulation strategy is
based on the Phase Disposition (PD) PWM and was
implemented using the TMS320F2812 DSP. In Fig. 12(a)
shows the waveforms of the voltage and current output (top)
obtained a resistive load. Also at the bottom shows the
waveforms of the command pulse for the fast switches. In
Fig. 12(b) is shown output voltage and output current, to
single-phase inverter with inductive load. In Fig. 3 is shown
voltage and current to three-phase inverter with inductive
load.
(a)
Fig. 13. Three-phase system: (a) voltages waveforms VA0, VB0 and
VC0 and output current IA, (b) voltage waveforms VAN, VBN and VCN
and output current IA.
VIII. CONCLUSIONS
(b)
Fig. 12. (a) Top; output voltage and output current to resistive load
and bottom; command pulses for fast switches. b) Output voltage
and output current, to single-phase inverter with inductive load.
This paper presented the asymmetrical hybrid multilevel
inverter circuit based on the three-level cell (TC) and the
associated modulation technique. The circuits are
characterized by fast switches in the inverter cell and slow
switches in H-bridge. The switches that make up the cell
(TC) support different voltages, depending with which the
sources of voltages are connected and can be 2E or E. The
voltage blocked by the H-bridge switches equals the entire
DC-link voltage (3E).
The voltages produced in the output of the inverter are
seven levels with a low harmonic distortion. In the case of
PWM modulation that generates high-frequency components
in bands around the side of the index of multiple frequency,
which is convenient if the goal is to eliminate through a filter
output.
One should take into account that with the strategy of
modulation used, you should choose a frequency of carriers
that do not manage even components in the output signal of
the inverter to avoid asymmetry in the signal. Also was
realized the theoretical analysis to waveforms of, line-to-line
and phase-load, three-phase output voltages and obtained its
THD.
This topology has the advantage over the symmetric of a
greater amount of output levels for the same amount of
switches used. But has the disadvantage of having greater
efforts of voltage in a pair of high frequencies switches.
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