High Electron Mobility Transistors (HEMTs)
Source
Gate
Wg
Drain
VG = 2 V
1000
∆VG = 1 V
Active Region
S. I. Buffer
Open channel
Lg
Source
Gate
Wg
d
Drain
ID (mA/mm)
800
600
gm = 200 mS/mm
400
200
0
0
2
4
6
8
10 12 14 16
VDS (V)
Active Region
S. I. Buffer
Lg
Pinch off
Similar to normally-on MOSFETs but no substrate doping. For accurate formula, refer to Sze: Physics
of Semiconductor Devices
Output Power Calculation (AC, not DC)
A
I max
IDS
linear
Pout, max =
BIAS POINT
I SWING
Q
VSWING ISWING
8
Minimize Vknee
B
V
knee
VDS
Maximize Vbreakdown
Vbreakdown
Maximize Imax
Maximize nsµ or nsvs
VSWING
GaAs pHEMT
AlGaN/GaN HEMT
Vknee (V)
1
5 (~ Vpinchoff)
Vbreakdown (V)
20
100 (over 200 reported for
small Lgd)
Imax (A/mm)
0.6
1.2 (over 2 reported)
Pout, max (W/mm)
1.4
14 (32 highest reported)
Sample power calculations
• Let Vknee be 4 V, and Vbd be 120 V, and Iswing be 120 mA for a 100
micron gate width device. Calculate the maximum output power in
dBm and in W/mm
– Solution: Total maximum output power = 1/8 (120 – 4) 120 mW
= 1740 mW. So output power in dBm = 10 log1740 = 32.405
dBm. Output power density is 1740 mW/100 micron = 17400
mW/mm = 17.4 W/mm.
• If the gain is 15 dB, what is the input power?
– Solution: 10 log (Pout/Pin) = 15 ⇒ Pout = Pin x 101.5 = Pin x 31.62
⇒Pin = 17.4/31.62 = 0.5502 W/mm.
• If the dc input power is also given then the Power-Added
Efficiency (PAE) can be calculated as (Pout – Pin)/Pdc
Slide # 3
Performance criteria for microwave transistors
• Output Power: Total microwave power available (W/mm)
• Gain: G = Pout/Pin, log G = Log Pout – Log Pin (Gain usually
measured in dB, but Pin and Pout are in dBm)
• Ft : Maximum frequency of oscillation or the frequency at which
the short circuit current gain is 1
• Fmax: The frequency at which the power gain is 1 for a perfectly
matched load
• Power added efficiency (P.A.E): (Pout – Pin)/Pdc, Pin = input
microwave power, Pdc = total dc power in at the gate and drain
terminals.
• Linearity: The measure of gain against input signal level. High
linearity means lower harmonic content in the output signal
• Noise Figure: SNRin/SNRout (usually expressed in dBm by taking
the log)
• Stability: long term and short term operational stability
Slide # 4
AlGaN/GaN HEMT: wish list
•
High VBr
– Minimize
• Buffer leakage: GaN:Fe
• Gate leakage: Insulated-gate
– Other device structures to improve VBr
•
High power efficiency
When efficiency is low Power dissipation at semiconductor devices ↑
Ron ↑ efficiency ↓
•
How to maximize efficiency
– Eliminate surface traps (passivation/epitaxial solutions)
– Eliminate bulk traps (growth condition tuning)
– Decrease leakage (low dislocation density/insulators?)
Slide # 5
Growth Challenge I: heteroepitaxy
Tiny changes in growth conditions
have strong effect on GaN properties
(T,d, V/III)
+ very sensitive coalescence process
= process much less robust than
homo-epitaxy
Lattice mismatch
time
High dislocation density in epitaxial
layers and at the interface of the
heteroepitaxial layers.
Slide # 6
Growth Challenges II: alloy epitaxy
• GaN technology still less mature than GaAs and InP technology
• Crystal growth is dominantly heteroepitaxial
• Alloys:
today’s high efficiency devices
AlxGa1-xN
InxGa1-xN
AlN
InN
xAl < 0.4
xIn < 0.4
High Al (x=0.5 ~ 1) is currently under intense
research (UV LEDs and detectors etc.)
GaN
Alloys with high Al and/or In compositions
difficulties related to interplay of
• Material properties and
• Epitaxy process
Stacia Keller et al. UCSB
Slide # 7
AlGaN/GaN high electron mobility transistor: basics
• Unlike AlGaAs/GaAs HEMT
requiring intentional doping to
form charge, 2DEG in
AlGaN/GaN HEMT are
polarization-induced. No
intentionally doping is needed.
• Electrons come from surface
states.
Polarization charge
Gate
⊕⊕
_ ⊕_⊕_⊕ _⊕ ⊕_ ⊕_⊕_⊕ _⊕ ⊕_ ⊕_⊕_⊕ ⊕
_ ⊕_ ⊕_⊕ _⊕ ⊕
_ ⊕_⊕_⊕ _⊕ ⊕
_
Source
Donors
AlxGa1-xN
ĒP
Channel 2-DEG
Surface
states
+++++-
GaN
UID
AlGaN
Polarization
charge
AlGaAs/GaAs HEMT
Drain
_ +_ +_+ _+ _+ +_ +_+_+ _+ +
_ +_ +_+ _+ _+ +_ +_+_+ _+ +
_ +_ +_
2DEG
+ + -+
Donor-like surface
traps (empty)
+
+
+
+
+
+
+
---
2DEG
AlGaN/GaN HEMT
Slide # 8
AlGaN/GaN HEMTs: Formation of the 2DEG
Layer structure
20-30 nm Al0.3Ga0.7 N
Schematic band diagram
ΦB
AlGaN
2DEG
Ec
∆Ec
GaN buffer(1-2 µm)
Nucleation layer (~ 20 nm)
GaN
d
+ve
σcomp
EF
σB
Sapphire/SiC substrate
2 DEG
σsurf
+ σ B  εε 0 
ns =
−  2 [Φ B + E F (ns ) − ∆Ec ]
e
 de 
• The 2DEG is an explicit function of the surface barrier, AlGaN
thickness, and the bound positive charge at the interface
Slide # 9
Comparison with GaAs HEMT Physics
Schematic band diagram
ΦB
AlGaN
GaN
Ec
∆Ec
d
+ve
σcomp
AlGaAs/GaAs HEMT
EF
σB
AlGaAs
donor
layer
GaAs buffer
2 DEG
σsurf
AlGaAs spacer
• No doping is required for the 2DEG to be present at the interface.
• Higher sheet charge and higher conduction band discontinuity for
AlGaN/GaN heterostructure
Slide # 10
Heart of HEMT: 2DEG
for high power, high frequency HEMTs:
high xAl,
coherently strained,
trap free AlGaN/GaN heterojuction,
(abrupt + smooth on an atomic level)
carrier confinement,
high breakdown voltage,
high currents
AlGaN u.i.d.
AlGaN:Si ?
GaN S.I.
Al2O3/SiC
2DEG
(density and mobility)
Determined by
- xAl
- interface roughness
- alloy scattering
- dislocation, etc.
Ambacher et al, JAP 87(1) 2000
Slide # 11
Properties of the 2DEG
2DEG Mobility vs. density
Spacer layer
thickness vs.
2DEG density
and mobility
dspacer depends on
intended application
• For AlGaAs/GaAs heterostructures, the spacer layer
thickness is important for 2DEG mobility and density
• The 2DEG does not freeze out at very low temperature
unlike the 3D doping
• The 2DEG mobility does not decrease with decrease in
temperature unlike the 3D case
• The 2DEG mobility can increase with increase in 2DEG
density due to increased screening unlike the 3D doping
Slide # 12
2DEG… Influence of the Al-composition
xAl>0.2:
µ300K
~ 1/xAl
xAl :
1400
1300
1200
- interface problems
- strain induced defects
- higher impurity incorporation
- alloy ordering/clustering
1100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0
0.0
0.2
0.4
0.6
xAl
-2
13
[10 cm ]
1000
ns
µ300Κ
2
[cm / Vs]
MOCVD
1500
ns
~ xAl
- charge increases due to
spontaneous polarization and
piezoelectric effects
xAl<0.2:
µ300K
~ xAl
- better confinement of the 2DEG
at higher xAl
- low xAl = low ns: less efficient
screening of defects
relaxed
Slide # 13
Temperature dependence of v-F curve
3
GaN
2
Electron Velocity (107 cm/s)
Electron Velocity (107 cm/s)
3
300 K
500 K
700 K
1
0
GaAs
2
300 K
500 K
700 K
1
0
0
200
400
Electric Field (kV/cm)
600
0
4
8
12
16
Electric Field (kV/cm)
• Usually the regions are separated into regions of constant and zero
mobility
• A velocity overshoot is expected for GaN similar to GaAs case, but
usually not seen, possibly due to high background doping
• At higher temperature, the degradation of v-F curve for GaN is
much smaller than GaAs
Slide # 14
20
Temperature dependent mobility
Increasing alloy composition in barrier
Debdeep Jena Ph.D dissertation
Slide # 15
Electron transport
Phonon scattering:
---most important at room temperature
Alloy disorder scattering
---potential disorder from ternary alloy
---important at low and room
temperature
Surface roughness scattering
---important at low temperature
Ionized impurities scattering
Dislocation scattering
Dipole scattering
Mattheissen rule for total mobility:
1
µ net
=∑
i
1
µi
where i refers to the mobility corresponding to different sources
• Alloy disorder scattering is the limiting factor at low temperature.
• Alloy disorder scattering also plays an important role at room temperature when carrier
concentration is high.
• It is due to the ternary nature of AlGaN.
Debdeep Jena Ph.D dissertation
Slide # 16
Methods for reducing scattering
• Controllable scattering mechanisms
– Background impurity scattering: By growing the
material purer
– Alloy scattering: By putting a thin binary alloy
(AlN) at the interface
– Dislocation scattering: By growing on lattice and
thermally matched substrate
– Interface roughness scattering: By growing very
smooth interfacial layers
• Rest of the scattering processes are usually
physics limited
Slide # 17
2DEG… High-mobility AlN interlayers
30
2.5
AlGaN/GaN
AlGaN/AlN/GaN
2
2
4
-2
cm )
12
15
10
N
S.I. GaN
(10
1 nm AlN
20
S
AlGaN
Mobility µ (10 , cm /Vs)
AlGaN/GaN
AlGaN/AlN/GaN
25
5
T = 17 K
1.5
1
0.5
T = 17 K
sapphire
0
dAlN = 1 nm
0
0.1
0.2
0.3
0.4
Al mole fraction x
0.5
0
0
0.1
0.2
0.3
0.4
Alloy composition x
0.5
by MBE, I.P. Smorchkova et al., J. Appl. Phys. 90 (2001) 5196
Similar results obtained by MOCVD
no alloy scattering
Slide # 18
AlN as a barrier layer
6
0.08
-2
2DEG density (10 cm )
Al0.22Ga0.78N/GaN
AlN/GaN
Probability
13
0.06
AlGaN/GaN
interface
0.04
0.02
0.00
24
26
28
30
32
34
36
5
4
3
2
1
0
0
5
10
15
20
25
30
AlN barrier thickness (nm)
Distance (nm)
Simulations
• Alloy disorder scattering:
---Wavefunction penetration
---Ternary material: AlGaN
• Reduce alloy scattering:
---Increase Al composition
---Binary material: AlN
• Use AlN as barrier material
---No alloy disorder scattering:
higher mobility
---Higher polarization charge density:
higher carrier concentration
• However, after gate metal deposition, it was
found to be almost ohmic due to tunneling!
Slide # 19
AlGaN/AlN/GaN Heterostructure
25 nm Al0.3GaN
0.7-1 nm AlN
UID GaN
SiC Substrate
• Incorporation of a thin AlN (<1nm)
into a standard AlGaN/GaN HEMT
• The thickness of AlN interfacial
layer is below critical thickness for
formation of 2DEG. The main
purpose is to improve mobility.
• Thin AlN layer forms a larger
effective ∆Ec, which affects both
mobility and carrier concentration.
Slide # 20
Charge and mobility vs. AlN thickness
AlGaN/AlN/GaN HEMT
1400
-1
1.8
Mobility (cm V s )
-1
1.6
1200
2
13
2DEG Density (10 cm-2)
1600
Charge(Simulation)
Charge(Experiment)
Mobility(Experiment)
1.4
1000
1.2
1.0
800
optimum
thickness
0.0
0.5
1.0
1.5
2.0
2.5
3.0
600
Thickness of AlN (nm)
Theory predicts that ns increases with AlN thickness
In real growth, thick AlN suffers by the relaxation. Above
0.5nm, charge saturates and mobility drops
Slide # 21
Band Diagram
25 nm Al0.33Ga0.67N/ 1 nm AlN/GaN HEMT
3
Thin AlN
- +
- +
- +
+
1
2
Effective ∆EC
0
Energy (eV)
2
Energy (eV)
3
25 nm Al0.33Ga0.67N/GaN HEMT
AlGaN
GaN
1
0
∆ EC
-1
0
10
20
30
40
50
0
Thickness (nm)
σ AlGaN t AlGaN −
ns =
t AlGaN
∆E
'
c , eff
εε 0
φB +
= ∆EC , AlGaN +
q2
εε 0
20
30
40
50
Thickness (nm)
εε 0
q
q
+ t AlN + d 0
10
2
∆Ec' ,eff
σ AlGaN ⋅ t AlGaN −
ns =
εε 0
q
φB +
εε 0
q
2
∆EC, AlGaN
t AlGaN + d0
σ AlN t AlN
Slide # 22
Hall data and DC I-V
Hall Data:
Undoped AlGaN/AlN/GaN:
ns = 1.22 ×1013 cm-2
µ = 1520 cm2/V s
Si-doped AlGaN /AlN/GaN:
ns = 1.48 ×1013 cm-2
µ = 1500 cm2/V s
∆VG = 1 V
800
ID (mA/mm)
Conventional undoped AlGaN/GaN
ns = 1.1 ×1013 cm-2
µ = 1200 cm2/V s
VG = 2 V
1000
600
gm = 200 mS/mm
400
200
0
0
2
4
6
8
10 12 14 16
VDS (V)
Mobility was improved with a slight increase of 2DEG
Si doping increased 2DEG density while retaining high
mobility
Slide # 23
Power Performance
Undoped AlGaN
25
35
30
30
25
20
20
15
15
10
10
5
5
0
0
30
0
5
10
15
20
25
Pin (dBm)
40
8.47 W/mm
Pout
Gain
PAE
25
35
30
25
20
20
15
15
10
PAE (%)
Pout
Gain
PAE
30
35
Pout (dBm), Gain (dB)
8.1 W/mm
Si-doped AlGaN
40
PAE (%)
Pout (dBm), Gain (dB)
35
10
5
5
0
0
30
0
5
10
15
20
25
Pin (dBm)
• On SiC substrate. SiN passivated.
• 8.1W/mm with a peak PAE of 23% was obtained at 8GHz at VD=50V,
ID=130mA/mm from an undoped AlGaN barrier HEMT.
• 8.47W/mm with a PAE of 41% was obtained at 10GHz at 8GHz at VD=45V,
ID=160mA/mm from a Si-doped barrier HEMT.
Slide # 24
Nd/Polarization=0.8
Nd/Polarization=0.5
8
18
4
6
Energy (eV)
-3
Nd/Polarization=1.2
Electron, Hole Concentration (10 cm )
Effect of Si doping density
2
4
0
2
parallel conduction
-2
holes
0
-4
0
50 100 150 200 250 300 350
Thickness (nm)
ns = 1.7 × 1013 cm-2
npara = 0.3 × 1013 cm-2
0
50 100 150 200 250 300 350
Thickness (nm)
ns = 1.36 × 1013 cm-2
0
50 100 150 200 250 300 350
Thickness (nm)
ns = 1.04 × 1013 cm-2
ps = 0.18 × 1013 cm-2
• Too much Si doping results in free electrons in graded layer,
leading to parallel conduction
• Too little Si doping is not enough to remove holes
• ~80% compensation puts fermi level in the middle of bandgap
Slide # 25
Design rules for AlGaN/GaN HEMTs:
Materials perspective
• Thickness of the barrier layer: affects 2DEG
concentration and vertical gate field (which controls gate
leakage current, VD, breakdown, and can also affect device
degradation)
• Al composition of the barrier layer: affects 2DEG
concentration and ∆EC, which confines the 2DEG
• Nucleation and buffer layer: affects dislocation density,
and surface morphology (both affect mobility, one by
charged line scattering and other by interface roughness
scattering) and parasitic conduction.
• Substrate for epitaxial growth: affects the heat
conductivity and ultimate output power performance as
well as defect density, and parasitics.
Slide # 26
Transistor fabrication layout
Submicron Ni/Au
mushroom gate
3
defined by e-beam
Ti/Al/Ti/Au ohmic
contact annealed at 2
800˚C (0.3 to 0.6 Ω-mm)
SEM image of a submicron mushroom gate
Air-bridge to connect
4 isolated source pads
Cl2 based ECR
1
mesa isolation
SEM photo showing air-bridge
over the gate metal (T-layout)
Slide # 27
Design rules for AlGaN/GaN HEMTs:
Fabrication perspective
2 x 125 µm U-gate
2 x 75 µm T-gate
D
S
D
S
S
S
G
G
• The gate footprint and the cross-sectional area and width controls the frequency
response
– Lg lower means fT goes up
– Cross-section and gate width control gate resistance (this is why mushroom gates are
used)
• The gate drain spacing as well as gate footprint determines the breakdown voltage
– Lg lower means VBR down
– Gate-drain spacing up means VBR up
• The geometry of the device also plays a role
– The U-geometry device has 10 – 15 % lower gm, Idss due to self heating
Slide # 28
Large periphery devices
Parallel fingers or fishbone layout for 12 x 125 µm devices:
Parallel fingers
Fishbone
Air bridges
• Larger periphery devices used for higher actual output power NOT
power density (usually more than 1 mm gate finger width)
• The fabrication processes are complicated as this involves airbridging the source or the drain.
• Large periphery design issues: electrical and thermal
Slide # 29
Design issues for large periphery devices
Electrical issues:
• The voltage drop along the gate length causes lower PAE
• Phase difference at the gate fingers reduce overall PAE
• Finite Ron reduces PAE. This becomes severe in presence of
trapping as Ron increases
Thermal issues:
• Device heating is a problem at higher output power, since
power wasted is also larger
• The maximum possible output power depends on the
conductivity of the substrates. SiC substrates are commonly
used. Thinned sapphire substrates have also been used.
• The number of gate fingers as well as the gate finger pitch
determine the maximum temperature rise in a device.
Slide # 30
DC characteristics of AlGaN/GaN HEMTs
1×0.3×100 µm devices (~35% Al)
• The negative slope in the dc characteristics of sapphire is either
due to heating or trapping
• The dc characteristics are better for HEMTs fabricated on SiC
than on sapphire possibly because of reduced dislocation density
and increased thermal conductivity
• The difference becomes more severe with scaling
Slide # 31
RF performance
Small signal
Large signal
30
20
10
Pout
Gain
PAE
25
50
40
20
30
15
PAE (%)
h21, UPG (dB)
Pout (dBm), Gain (dB)
h21
UPG
30
60
3.4W/mm
20
10
10
5
0
1
10
100
f (GHz)
• ft of 22GHz and fmax of 40GHz were
obtained from a 0.7um-gate-length
HEMT at drain bias of 10V and drain
current of 240mA/mm.
0
5
10
15
20
0
25
Pin (dBm)
• On sapphire substrate.
• No SiN passivation.
• 3.4W/mm with peak PAE 32% was
obtained at 10GHz when VD=15V and
ID=230mA/mm.
Slide # 32
RF performance
Large signal
h21
UPG
40
h21, UPG (dB)
Pout (dBm), Gain (dB)
35
30
20
10
0
1
10
100
Frequency (GHz)
• ft of 21GHz and fmax of 39GHz were
obtained from a 0.7um-gate-length
HEMT at drain bias of 15V and drain
current of 280mA/mm.
12W/mm
Pout
Gain
PAE
30
50
40
25
44%
30
20
20
PAE (%)
Small signal
15
10
10
0
0
5
10
15
20
Pin (dBm)
• On SiC substrate
• 12W/mm with a peak PAE of 44% was
obtained at 4GHz at VD=50V,
ID=270mA/mm
Slide # 33