Fall Technical Meeting, San Antonio 10/28-31/2013
SLS-CS_13-20
High Data Rate (Gbps +) Coding Architecture
Part 3 (part 2 was presented at Spring 2013 meeting)
V. Sank, H. Garon - NASA/GSFC/MEI
W. Fong, W. Horne – NASA/GSFC
1
High Data Rate (Gbps) Coding Architecture
Purpose
• To avoid having a transmitter encoder built in a way that is incompatible
with the ground receiver decoder, a standard or recommendation should exist.
Introduction
• Inherent to any system is the problem of component rate limits. In addition
to the encoder and decoder, the circuits that compose the I and Q or higher order
modulation channels, hit a rate limit. If there was only one way to architect the
system, there would be little concern. The problem is that there are several ways
to build the system and the transmitter must have the same structure as the receiver.
• As we push to very high rate Gbps links, we believe that CCSDS should set
standards on how encoders and decoders should be multiplexed. Vendors are
ahead of CCSDS and several have already chosen an architecture.
• Our intent here, at a minimum, is to make the community aware that a
laissez-faire approach towards standards is a poor choice. Since there are multiple
structures possible, every user must clearly specify their intended structure and
must insure that the encoder and decoder are compatible.
2
High Data Rate (Gbps) Coding Architecture
Rb = data rate (from C&DH) (bits/sec)
Rs = coded data rate (code symbol rate, code symbols/sec)
N = number of encoders
k = codeword message size (bits, nibbles, bytes)
n = codeword size including parity (same unit as k)
m = modulation order (ie. m=3 => 8PSK)
Rm = modulation symbol rate
s = size of ASM (same units as k and n)
mPSK
Data
Source
Rb
Block Code
Encoder
Mapper
Rs
Code symbols to
Modulation
Symbols
Rs = (n+s)/k Rb
Rm
Modulation
symbol
rate = Rs/m
m order
Modulator
R/m
Transmitter
• Diagrams are shown from the point of view of the transmitter.
• The structure of the decoder must complement the transmitter, except as
noted.
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10-13-13
Recommended Architecture
Block Encoder Input, Block output (codeword in – codeword out)
b1, b2, b3, ...
Rb
b1, b2, b3, ...
Data Rb
Source
Rb
b1, b2, b3, ...
Rb
b1, b2, b3, ...
Rb
Block Code
R/N
Encoder
Block Code
R/N
Encoder
Block Code
R/N
Encoder
Block Code
R/N
Encoder
c1, c2, c3, ...
c1, c2, c3, ...
Rs
c1, c2, c3, ...
Rs = (n+s)/k Rb
Mapper
Code symbols to
Modulation
Symbols
mPSK
mth order
Modulator
Modulation
symbol
rate = Rs/m
c1, c2, c3, ...
• An encoder is loaded with the full message size, k, before data starts flowing into the
next encoder. (receivers from two vendors are configured this way. )
• Data on the physical channel appears the same as it would if there was a single
encoder that runs at the full rate.
• This architecture has the advantage that the number of encoders and decoders
need not be the same.
4
10-13-13
NOT Recommended Architecture
RS Type Frame applied to 7/8 LDPC
I=4
32 bit CSM
b1
b2
b3
b4
b5
b6
b7
b8
Bits are loaded horizontally and transmitted in the
same order. (Staggered IN, Staggered OUT)
Four separate codewords shown.
Codeword 1 contains bits b1, b5, … , 32637.
If a burs t of noise corrupts bits 5,6,7,8 on the
physical link, the decoder will see only one error in
each of the 4 codewords.
k = 7136
This configuration is used for Reed-Solomon
coding where the code word is only2040 bits long.
n = 8160
28545 28546 28547
n-k = 1024
This configuration is not generally required for the
7/8 LDPC code due to its larger size and better burst
error correcting ability.
When this configuration is used, the receiver must
be set up with the same number of decoders as
used in the encoder.
28548
CCSDS may decide to choose this as the
recommended Gbps coding structure, rather than
the structure shown on slides 5, 6, and 7.
32637 32638 32639 32640
If the encoder and decoder can handle the full data rate, it can be set to 1 and the result will
be the same structure on the physical channel as the recommended architecture. .
5
High Data Rate (Gbps) Coding Architecture
Conclusion:
• To avoid confusion, examples of architectures which are not
recommended are just as important as those which we do
recommend.
• Concepts that apply to RF also apply to Optical communications.
However, for optical communications, a different code block
structure (similar to the RS structure) may be desired.
• CCSDS should recommend standard before we have vendors
building Gbps systems that are incompatible with each other.
6
High Data Rate (Gbps) Coding Architecture
Back Up
7
Encoder, Simple Cases
Data
Source
Rb
Block Code
Encoder
BPSK
Rs
Mapper
Modulator
Single encoder
Limited rate
Simple
OQPSK
C1, C3, C5, ...
Data
Source
Rb
Block Code
Encoder
Single encoder
Limited rate
Recommended
Architecture
R/2
Rs
Mapper R/2
Modulator
C2, C4, C6, ...
Same decoder configuration as above
Recommended
Architecture
Simple
Staggered Encoder Input Independent Encoders on the I and Q channel
Block Code
Rb/2 Encoder
Rb/2 Block Code
b2, b4, b6, ...
Encoder
b1, b3, b5, ...
Data
Source
Rb
OQPSK
c1, c2, c3, ...
Rs/2
Rs/2
c1, c2, c3, ...
Modulator
Not
Recommended
Not so simple
Requires unique decoder configuration
When more than 1 encoder, input is shown as either b1 b2 b3 which means that a constant stream of bits
are input, or b1 b3 b5 and b2 b4 b6 which means that the bits are staggered from one encoder to the other.
8
Recommended Architecture
With OQPSK Modulation
Block Encoder Input, Block output
b1, b2, b3, ...
R
b1, b2, b3, ...
R
Data
Source
R
b1, b2, b3, ...
R
b1, b2, b3, ...
R
Block Code
R/N
Encoder
Block Code
R/N
Encoder
Block Code
R/N
Encoder
Block Code
R/N
Encoder
c1, c2, c3, ...
c1, c2, c3, ...
Data from a single encoder is
staggered onto the I and Q channels
OQPSK
c1, c3, c5, ...
R/2
R
Modulator
Mapper R/2
R
c1, c2, c3, ...
c1, c2, c3, ...
c2, c4, c6, ...
For 7/8 LDPC code
there will be 0 Modulation
symbols that cross a boundary.
• Data on Physical channel appears the same as if there was a single encoder that runs
at full rate, R.
• This architecture has the advantage that the number of encoders and decoders
need not be the same. Four encoders shown but the number depends on the rate
capability of the encoders and decoders.
9
Recommended Architecture
With 8PSK Modulation
Block Encoder Input, Block output
One encoder is
loaded before
switching to the
next.
R
Data
Source
b1, b2, b3, ...
R
b1, b2, b3, ...
R
b1, b2, b3, ...
R
Block Code
R/N
Encoder
Block Code
R/N
Encoder
Block Code
R/N
Encoder
c1, c2, c3, ...
c1, c2, c3, ...
R
Mapper
R
c1, c2, c3, ...
Currently,
Data Rates Greater than 1 Gbps Require 8PSK
Note that this Architecture does not use a
separate encoder for each of the 3 channels.
Data from a single encoder
forms a modulation symbol
Except at
Block
boundary
8 PSK
R/3
c1, c4, c7, ...
R/3 Modulator
c2, c5, c8, ...
R/3
c3, c6, c9, ...
For every 3 codewords
there will be 2 Modulation
symbols that cross a boundary.
• Data on Physical channel appears the same as if there was a single encoder that runs
at full rate, R.
• This architecture has the advantage that the number of encoders and decoders
need not be the same. Three encoders shown but the number depends on the rate
capability of the encoders and decoders.
10
NOT Recommended Architecture
With OQPSK Modulation
Staggered Encoder Input, and Output
Block Code
Rb/N Encoder
b1, b5, b9, ...
Block Code
Rb/N Encoder
b2, b6, b10, ...
Data Rb
Source
Block Code
Rb/N Encoder
b3, b7, b11, ...
Block Code
Rb/N Encoder
c1, c5, c9, ...
c2, c6, c10, ...
Rs/N
c3, c7, c11, ...
Possible OQPSK configuration
Similar to RS code block
NOT Recommended
OQPSK
c1, c3, c5, ...
Rs
R/2
Mapper R/2
Modulator
c2, c4, c6, ...
b4, b8, b12, ...
c4, c8, c12, ...
• This configuration has the same advantage as the RS code block, burst protection.
• M ≡ average number of codeword errors that can be corrected over all codewords.
• On average, this configuration will correct a burst of N*M bits because consecutive
bits on the physical channel are from different encoders.
• An implementation that is expecting a high burst noise background may prefer
such a custom design where bits are staggered into and out of the encoder.
(more detail on next slide)
11
Quad Encoder, 16PSK possible configuration
Block Encoder Input, Block output
Block Code
R/N Encoder
b1, b2, b3, ...
c1, c2, c3, ...
R/4
16PSK
Block Code c1, c2, c3, ...
s1, s2, s3, ...
R/N Encoder R/N
R
s1, s2, s3, ...
4th order
b1, b2, b3, ...
Mappers1, s2, s3, ...
Block Code
Modulator
R/N Encoder c1, c2, c3, ...
s1, s2, s3, ...
b1, b2, b3, ...
R
Data
Source
Possible 16PSK configuration
RECOMMENDED
Block Code
R/N Encoder
b1, b2, b3, ...
c1, c2, c3, ...
s1, s2, s3, …
are modulation symbols
Rchannel symbol = R/4
8192/4 = 2048
• This architecture has the advantage that the number of encoders and decoders
need not be the same.
• On average, this configuration will correct a burst of N bits, not N channel symbols
• A cover code can be used to synchronize the decoders and resolve ambiguity.
12
High Data Rate (Gbps) Coding Architecture
Background
• In days past, in a case with a convolutional code, and rate limited decoders,
several decoders were required. Not realizing that there was more than one way to
architect the system, the vendor chose what was thought to be the only or obvious
structure, and built the spacecraft. It was not until after CDR and after the spacecraft
was built, that we asked the vendor how he knew what the ground station design
was. It turned out that the spacecraft was built incorrectly and the transmitter
encoder needed to be disassembled and redesigned. The spacecraft vendors test
equipment also needed to be redesigned.
Scope
• the intend of this presentation is to have CCSDS consider a standard
• This presentation is not intended to be a design document or specification.
• The following diagrams do not consider the latencies, memory buffers and frame
synchronization that will be required in a formal specification or real system.
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