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TEST AND MEASUREMENT PRODUCTS
presence of these relays continues to reduce ultimate
system performance. Reliability, system size and cost are
all factors which could be improved with the removal of
some or all of the relays in this portion of a test system.
Introduction: Relays in Test Systems
Obtaining sub-nanosecond AC accuracy and nanoamp DC
precision in Automated Test Equipment (ATE) has
traditionally required relays to isolate the DC measurement
section from the AC measurement section. This has been
necessary to keep the leakage of the AC measurement
section from impacting the DC measurements as well as
keeping the parasitic capacitance of the DC section from
degrading the rise/fall times of the signals going to and
from the AC test section. It has also often been necessary
to protect the high speed pin driver electronics, which
operate at logic-level voltages, from the wider voltage range
put out by the PPMU for its measurements.
Getting Rid of the Relays
To reduce or eliminate the number of relays, it is necessary
to eliminate the reason for their presence. If the parasitic
capacitance of the PPMU can be kept from distorting the
fast rise/fall time signals passing between the pin driver
and the DUT, the two relays connecting the PPMU force
and sense pins can be eliminated. Reducing the leakage
current of the pin driver chip and designing it to withstand
the full range of PPMU voltages used allows the removal
of the relay connecting this part. Since the system PMU
uses the same force/sense connection approach as the
PPMU, connection of this subsystem can be done through
MOSFET switches inside the PPMU rather than through
external relays.
Figure 1 shows one version of relay-based tester-per-pin
architecture used in ATE systems. This architecture
typically requires five or more relays per pin.
In spite of the many advances in relay technology, the
SENSE
Per-Pin DC
Measurement Unit
FORCE
50
Driver
–
+
50Ω
DUT Pin
Transmission Line
Window Comparator
+
–
AC Pin Electronics
System PMU Force
System PMU Sense
Figure 1. Traditional Tester-Per-Pin Architecture with Relays
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SENSE
Per-Pin DC
Measurement Unit
FORCE
50
Driver
Inductor
Inductor
–
+
50Ω
DUT Pin
Transmission Line
Window Comparator
+
–
AC Pin Electronics
Figure 2. Tester Per Pin Architecture Using Inductors to Compensate for PPMU Capacitance
Ferrite-Based Relayless Test System
Inductor Compensation Approach to
Relayless Test System
An alternative approach uses a high-impedance ferrite to
block the effect of the PPMU capacitance from the fast
edges passing through the transmission line as shown in
Figure 3.
One established approach to a system using inductors
which combine all of these characteristics into a relayless
test system is shown in Figure 2.
For this approach to work, the impedance of the ferrite
must be relatively high at the Pin Driver operating
frequencies and low at the PPMU operating frequencies.
Surprisingly enough, currently-available chip ferrites fit into
this requirement very nicely. At the 100+ MHz frequencies
associated with DUT and Pin Driver edge rates, chip ferrite
impedances can easily reach hundreds of ohms, while at
the (<1 MHz) frequencies associated with a fast-settling
PPMU, the impedances are typically 1Ω or less (See Figure
4). So, a ferrite with this sort of characteristic will effectively
block the PPMU capacitance from degrading the high
speed time-measurement signals and still be essentially
transparent to the low speed PPMU signals.
The primary disadvantage of this approach is that even
small PPMU parasitic capacitances (<10 pf) slow down
the rise and fall times of the AC signals and reduce timing
accuracy and maximum operating frequency. The practical
upper limit for this sort of approach is 200-300 MHz.
Below this speed, however, this can be a good approach
to reducing relay count. For more details on this approach
see Semtech Application Note ATE-A1.
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SENSE
Per-Pin DC
Measurement Unit
5K - 50K
ferrite
>500Ω
FORCE
50
50Ω
DUT Pin
Transmission Line
Driver
–
+
Window Comparator
+
–
AC Pin Electronics
Figure 3. No-Relays Tester Per-Pin Architecture Using Ferrites and Resistors
1000
100
10
1
0.1
0.1
1
10
100
1000
Frequency (MHz)
Figure 4. Impedance Variation with Frequency for a Typical High-Impedance Ferrite
(Steward 600Ω 0603)
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Ferrite-Capacitance Effect on High Speed AC Signals
Since a ferrite is primarily resistive (dissipating energy) rather than reactive (storing and releasing energy) at high
frequencies (see Figure 5), this approach causes relatively little distortion of the rising and falling edges of the AC
signals going between the Pin Driver and the DUT. The only tradeoff is that the amplitude of the AC signal will be
reduced in much the same fashion as if an AC-coupled resistor were placed in parallel with the transmission line.
A ferrite impedance of 600Ω, for instance, will reduce the amplitude of the signal traveling a 50Ω transmission line
by as much as 8%. As shown in Figure 6, this effect is not dependent on the size of the load capacitance.
Figure 5. Resistive, Reactive and Total Impedances for a Typical High-Impedance Chip Ferrite
(Vishay ILB-1206-600). R is Resistive Component, X is Reacive Component, Z is Total Impedance
0.5
0.4
0.3
no ferrite or capacitance
10pf, 600 ohm 0603 ferrite
47pf, 600 ohm 0603 ferrite
150pf, 600 ohm 0603 ferrite
0.2
0.1
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Time (ns)
Figure 6. Effect of a 600Ω
Ω 0603 Ferrite in Series with Varying Capacitance on a 250 ps Rise Time Signal
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Chip ferrites come in a number of different package sizes, not all of which have the same effect. As shown in Figure
7, the larger packages distort the rise time of the signal more than the smaller packages. The reason for this can be
found by comparing the high frequency impedances of the different ferrites. As shown in Figure 8, the larger packages
generally have lower impedances than the smaller packages at the highest frequencies, which explains the results
shown previously in Figure 7. When the rise time of the signal is slowed down from 250 ns to 500 ns, the effect of the
ferrites is virtually unchanged (Figure 9) indicating that the system calibration will be good for a wide range of DUT slew
rates.
0.5
0.4
0.3
no ferrite or capacitance
47pf, 600 ohm 0402
47pf, 600 ohm 0603
47pf, 600 ohm 0805
47pf, 600 ohm 1206
0.2
0.1
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Time (ns)
Ω Ferrites (Steward) in Series with 47 pF
Figure 7. The Efect of Various Sized 600Ω
Capacitance on a 250 ps Rise Time Signal
1000
600 ohm 1206
800
600 ohm 0805
600
600 ohm 0603
600 ohm 0402
400
200
0
1
10
100
1000
Frequency (MHz)
Ω Ferrites in Different Package Sizes
Figure 8. Impedance Curves for Steward 600Ω
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0.5
0.4
0.3
0.2
No ferrite or capacitance
47pf+0402 ferrite
0.1
47pf+0603 ferrite
47pf+0805 ferrite
47pf+1206 ferrite
0
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Time (ns)
Figure 9. Effect of Various 600Ω
Ω Ferrites on 500 ps Rise Time Signal
Ferrite Effect on PPMU Measurements
The effect of the ferrite on PPMU performance is equally small. Since the impedance of a high-frequency, highimpedance ferrite is usually on the order of 1Ω or less at frequencies below 1 MHz, the effect of this part on the PPMU
settling and accuracy is negligible (Figure 10) as long as the sense line is connected on the DUT side of the ferrite.
0.06
0.05
2V step, no ferrites
2V step, with ferrites
0.04
10V step, no ferrites
10V step, with ferrites
0.03
0.02
0.01
0
1.E-05
2.E-05
2.E-05
3.E-05
3.E-05
4.E-05
4.E-05
5.E-05
5.E-05
6.E-05
6.E-05
Time (sec)
Figure 10. PPMU Settling Times with and without Ferrite Resistance in
Series with 100 pF DUT Capacitance
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Note that ferrites could also be connected in series with
the Sense input to the PPMU rather than the resistor shown
in Figure 3. But, since the Sense line does not carry any
current, the low impedance of the ferrite is not normally
needed. However, if the sense line has significant
capacitance and the PPMU response is very fast, then
the R-C time constant of the series resistor and the Sense
node capacitance may be large enough to increase the
settling time or introduce instabilities in the PPMU circuit.
In this case, using ferrites in place of the resistor is
recommended.
The reason for the ringing on this waveform can be found
by examining the ferrite impedance curve shown earlier in
Figure 5. At frequencies above 50 MHz. the resistive
impedance of the Ferrite dominates (R in Figure 5), but at
lower frequencies the reactive component (X in Figure 5),
which appears as an inductor to the circuit, becomes
dominant. So, if the voltage across the parasitic
capacitance has not stabilized by the time the ferrite
impedance becomes reactive, an L-C resonant circuit will
come into effect, causing the ringing shown in Figure 11.
Fortunately, there are solutions to this problem. The most
straightforward is to use PPMU’s which have the lowest
possible parasitic capacitance, and locate the part as
close to the transmission line as possible. If a PPMU with
a parasitic capacitance of 10 pf is used (such as the
E4707, E4287 or E4237), the amount of ringing using
the same ferrite as above is reduced, as shown in Figure
12. Note that the worst-case amplitude error, amount of
ringing and time duration of ringing all are reduced.
Effect of Ferrite Circuit on Long Pulse
Width AC Signals
The results shown so far indicate that the optimum ferrite
design would simply use one or more of 0402-sized
Ferrites in series with the PPMU. For systems which only
run at high frequencies (>50 MHz), this would be true.
But, in systems which require fast edges but also may
have long pulse widths, a ferrite circuit could distort the
long-term output voltage of the pulses, as shown in Figure
11.
0.6
0.5
0.4
0.3
no capacitance or ferrite
47pf,600R 0603 ferrite
0.2
0.1
0
-0.1
0
20
40
60
80
100
120
140
160
180
200
Time (ns)
Figure 11. Effect of a 600Ω
Ω 0603 Ferrite in Series with a 47 pF Capacitance on a Long Pulse
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0.6
0.5
0.4
no capacitance or ferrite
10pf, 600 ohm 0603 ferrite
0.3
0.2
0.1
0
-0.1
0
10
20
30
40
50
60
70
80
Time (ns)
Figure 12. Effect of a 600Ω
Ω 0603 Ferrite in Series with a 10 pF Capacitance on a Long Pulse
Another approach to reduce the ringing is to use larger-sized ferrites. The larger the size, the higher the resistance/
reactance ratio at lower frequencies. Thus larger ferrites have less ringing for a given capacitance (see Figure 13).
So, if system design requirements force the use of a PPMU which presents a larger capacitance (such as the E737 or
E4717), the larger ferrites will most likely need to be used in the circuit.
0.6
0.5
0.4
0.3
no ferrite or capacitance
47pf, 600 ohm 0402 ferrite
47pf, 600 ohm 0603 ferrite
47pf, 600 ohm 0805 ferrite
47pf, 600 ohm 1206 ferrite
0.2
0.1
0
-0.1
0
20
40
60
80
100
120
140
160
180
200
Time (ns)
Figure 13. Long-Term Signal Shape of Various 600Ω
Ω Ferrites in Series with 47 pF
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As the total parasitic capacitance to be shielded gets large (~150 pF), the amount of ringing increases dramatically,
even with larger-sized ferrites (Figure 14). At this point, off-the-shelf surface mount ferrites do not seem to be a useful
solution. Since peak dissipation frequencies of ferrites can be tailored by changing granule size and other parameters,
theoretically, custom devices can be made to solve this. However, since low-capacitance PPMU’s are readily available
from Semtech, this would not be a cost effective solution for most cases.
0.6
0.5
0.4
0.3
no ferrite or capacitance
150pf, 600 ohm 0402 ferrite
150pf, 600 ohm 0603 ferrite
150pf, 600 ohm 0805 ferrite
150pf, 600 ohm 1206 ferrite
0.2
0.1
0
-0.1
0
50
100
150
200
250
300
350
400
Time (ns)
Figure 14. Long-Term Signal Shape of Various 600Ω
Ω Ferrites in Series with 150 pF
Optimizing Ferrite Selection
Since the optimum high frequency characteristics occur in different sized ferrites than optimum mid-frequency
characteristics, it seems clear that most designs will likely need two or more ferrites in series to get good fast-edge
and long-pulse performance. Since even a single ferrite with good high frequency behavior is enough to keep the
distortion on fast edges to minimal amounts, it is the long-pulse behavior that usually requires more attention to get
optimized.
Figure 15 shows the long-pulse waveforms of a 10 pf PPMU capacitance with a Steward 600Ω 0402 ferrite only, or
with an 0402 ferrite in series with an 0805 or 1206 ferrite. While the worst-case voltage for the single 0402 ferrite
is not bad (5.2%), this is reduced to 3.2% worst-case for the 0402 in series with one of the larger ferrites. Since both
of the larger-sized ferrites have very close to the same effect, the smaller one will likely be preferable for most
designs.
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0.6
0.5
0.4
No ferrite or capacitance
0.3
10pf, 600ohm 0402 ferrite
10pf, 600ohm 0402+0805
0.2
10pf, 600ohm 0402+1206
0.1
0
-0.1
30.0
40.0
50.0
60.0
Time (ns)
70.0
80.0
90.0
Figure 15. Various Combinations of 600Ω
Ω Ferrites with 10 pF Capacitance
With a larger load capacitance, more ferrites need to be added in series in order to reduce the amplitude error to
acceptable levels. Figure 16 shows the effect of various ferrite combinations with a 47 pf load capacitance. For this
load capacitance, the worst-case voltage error is 12% with an 0402 ferrite alone, 7.3% for an 0402 ferrite in series
with an 0805 or 1206 ferrite, and 5.5% for an 0402 ferrite in series with two 0805 ferrites. Clearly, as the parasitic
capacitance gets larger, an increasing number of ferrites are needed to get good amplitude accuracy, though at a 47pf
load, the cost and board space required for ferrites is still relatively small.
0.6
0.5
12%
0.4
no capacitance or ferrite
47pf+0402 ferrite
47pf+0402+0805 600 ohm ferrites
47pf+0402+1206 600 ohm ferrites
47pf+0402+0805+0805 600 ohm ferrites
0.3
0.2
0.1
0
-0.1
22
42
62
82
102
122
142
162
182
202
222
Time (ns)
Figure 16. Long-Term Signal Amplitude Error with a 47 pF Parasitic
Capacitance and Varying Ferrite Combinations
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be reduced by the isolation effects of the first ferrite.
Ferrite Manufacturers
With board dielectric thicknesses becoming ever thinner
in order to maximize the number of 50Ω traces which can
be placed on a board, the amount of parasitic capacitance
presented by the solder pads for surface mount
components can be enough to distort very fast signals.
This can be reduced by removing the ground and power
planes directly underneath the isolation ferrites. It is
important, however, that the gap in the ground plane not
extend underneath the transmission line as this will change
the line impedance at this point, causing reflections.
The majority of the measurements presented were made
using Steward ferrites. However, similar parts are also
available from Panasonic (down to 0603 size) and Vishay
(down to 0402 size). Since ferrite resistive and reactive
characteristics change considerably with manufacturing
techniques, checking performance using different
manufacturers’ products is recommended to get the best
performance.
Board Layout
When laying out the printed circuit board, it is important
to place the ferrite (or the first ferrite if more than one is
used) as close to the transmission line as possible. This
minimizes the capacitance of the trace connecting the
ferrite to the transmission line as well as reducing the
“stub length” or the amount of time the signal travels
before being reflected by the ferrite’s impedance. It is
important that this time be much shorter than the fastest
rise/fall time of interest in order to minimize any signal
distortion.
Comparison to Other Approaches
For fast slew rate signals, ferrite isolation can actually give
better edge timing accuracy than other approaches. Figure
17 shows the change in a 250 ps rise time signal when a
Coto 9802 relay (rated at 6 GHz) is inserted to disconnect
the PPMU capacitance. Comparing this with Figure 18
shows that a circuit using two 600Ω ferrites in series,
instead of a relay to isolate the capacitance of a PPMU,
can have significantly less timing distortion than a good
quality relay.
When more than one ferrite is used in series, the one with
the largest high-frequency impedance should be placed
closest to the transmission line. After the first ferrite, the
placement of additional ferrites is not as critical since the
effect of small amounts of capacitance or line length will
The improvement can actually be larger than this since
this comparison was done with both the ferrites and relay
placed optimally close to the transmission line. In actuality,
the relatively large size of the relay makes it more difficult
to place close to the transmission line in an extremely
tightly-packed pin card.
0.5
0.4
Transmission line only
0.3
With Coto 9802 relay (open)
0.2
0.1
0.0
0.5
0.7
0.9
1.1
1.3
1.5
Time (nS)
Figure 17. Effect of an Open Coto 9802 Relay on a 250 ps Rise Time Signal
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0.5
0.4
0.3
no capacitance or ferrite
47pf+0402+0805 ferrites
0.2
47pf+0402 ferrite
0.1
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Time (ns)
Figure 18. Effect of One or Two Ferrites in Series with 47 pF on a 250 ps Rise Time Signal
rising edge and the voltage level of the high-speed signal
more than does ferrite isolation. One advantage, however,
is that the voltage level error only occurs for a very short
time, normally only a couple of nanoseconds or less. When
used in conjunction with the low-capacitance solid state
relays discussed above, this may be a viable alternative.
Recently-released solid state relays (SSR) such as the
International Rectifier PVY116 can have switch-off
capacitances as low as 3 pf, which presents much less
signal distortion than a PPMU load capacitance, but even
this low a capacitance must be shielded or compensated
for in order to get best performance. Putting these types
of switches in series with the pin driver also can lower
performance due to the bandwidth limitation going through
the switch. If a PPMU has excessively high capacitance,
then using a low-capacitance SSR in combination with
ferrite isolation (or inductor compensation) can still allow
good timing accuracy.
Conclusion
It is possible to design an ATE system without relays if the
PPMU and Pin Electronics are designed for this approach.
With careful system design this approach can have superior
AC performance at 500 MHz (or greater) operating speeds
even when using off-the-shelf components currently
available.
Inductor compensation of parasitic capacitance (discussed
in detail in Semtech app note ATE-A1) distorts both the
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