Transmission Line Basics Prof. Tzong-Lin Wu NTUEE 1 Outlines Transmission Lines in Planar structure. Key Parameters for Transmission Lines. Transmission Line Equations. Analysis Approach for Z0 and Td Intuitive concept to determine Z0 and Td Loss of Transmission Lines Example: Rambus and RIMM Module design 2 Transmission Lines in Planar structure Homogeneous Inhomogeneous Coaxial Cable Stripline Microstrip line Embedded Microstrip line 3 Key Parameters for Transmission Lines 1. Relation of V / I : Characteristic Impedance 2. Velocity of Signal: Effective dielectric constant 3. Attenuation: Conductor loss Dielectric loss Z0 e ac ad Lossless case Z0 Vp L C 1 VpC 1 LC c0 e Td C 1 Td 4 Transmission Line Equations Quasi-TEM assumption 5 Transmission Line Equations R0 resistance per unit length(Ohm / cm) G0 conductance per unit length (mOhm / cm) L0 inductance per unit length (H / cm) C0 capacitance per unit length (F / cm) KVL : KCL : dV ( R0 jwL0 ) I dz dI (G0 jwC0 )V dz Solve 2nd order D.E. for V and I 6 Transmission Line Equations Two wave components with amplitudes V+ and V- traveling in the direction of +z and -z V V e rz V e rz 1 I (V e rz V e rz ) I I Z0 Where propagation constant and characteristic impedance are r ( R0 jwL0 )(G0 jwC0 ) a j V V Z0 I I R0 jwL0 G0 jwC0 7 Transmission Line Equations a and can be expressed in terms of (R0 , L0 , G0 , C0 ) a 2 2 R0 G0 2 L0 C0 2a ( R0 C0 G0 L0 ) The actual voltage and current on transmission line: V ( z, t ) Re[(V e az e jz V e az e jz )e jwt ] 1 I ( z, t ) Re[ (V e az e jz V e az e jz )e jwt ] Z0 8 Analysis approach for Z0 and Td (Wires in air) C = ? (by Q=C V) L = ? (by Ψ=L I) 9 Analysis approach for Z0 and Td (Wires in air): Ampere’s Law for H field H(r)= I d I 2 r c 2) e BT d s S R2 r R1 0 I I R dr 0 ln( 1 ) (in Wb) 2 r 2 R2 10 Analysis approach for Z0 and Td (Wires in air): Ampere’s Law for H field 0 I R2 e ln( ) 2 R1 L e / I 11 The per-unit-length Parameters (E): Gauss’s Law 1) from gauss law D ET S ET d s Qtotal q 1m 0 ds S q 2 0 r 2) V= E T d r R2 C R1 q 2 0 ln q 2 0 r dr R2 R1 12 The per-unit-length Parameters (E) q R2 V ln( ) 2 0 R1 C Q /V 13 c. For example Determine the L.C.G.R of the two-wire line. (note:homogeneous medium) S Inductance: L= e e I I rw2 rw1 I where 0 I s-rw2 0 I s-rw1 e ln( )+ ln( ) 2 rw1 2 rw2 0 I (s-rw2 )(s-rw1 ) = ln( ) 2 rw1rw2 assume s e ( 0 , 0 ) rw1 , rw2 0 s2 L= ln( ) 2 rw1rw2 14 Capacitance: 1) e S c 0 0 + 2 0 C s2 ln ( ) rw1rw2 + rw1 - + + + q C/m V - rw2 - - -q C/m s-rw2 s-rw1 q 2) V= ln( )+ ln( ) 2 0 rw1 2 0 rw2 q (s-rw2 )(s-rw1 ) = ln( ) 2 0 rw1rw2 q s2 ln( ) 2 0 rw1rw2 q q C= V 2 0 s2 ln ( ) rw1rw2 if s rw1 , rw2 the same with 1) approach 15 The per-unit-length Parameters Homogeneous structure TEM wave structure is like the DC (static) field structure LG LC So, if you can derive how to get the L, G and C can be obtained by the above two relations. 16 The per-unit-length Parameters (Above GND ) 2C Why? L/2 17 d. How to determine L,C for microstrip-line. 0 , 0 1 , 1 1) This is inhomogeneous medium. 2) Nunerical method should be used to solve the C of this structure, such as Finite element, Finite Difference... 3) But e can be obtained by e C0 0 0 e 0 0 C0 where C0 is the capacitance when 1 medium is replaced by 0 medium. 18 Analysis approach for Z0 and Td (Strip line) Approximate electrostatic solution y 1. b x -a/2 2. a/2 The fields in TEM mode must satisfy Laplace equation t ( x , y ) 0 where is the electric potential The boundary conditions are ( x , y ) 0 at x a / 2 ( x , y ) 0 at y 0, b 2 19 Analysis approach for Z0 and Td 3. Since the center conductor will contain the surface charge, so n x n y A cos sinh n a a n 1 odd ( x, y ) B cos n x sinh n (b y ) n a a n 1 odd for 0 y b / 2 for b / 2 y b Why? 4. The unknowns An and Bn can be solved by two known conditions: R|The potential at y b / 2 must continuous S|The surface charge distribution for the strip: RS1 T0 T s for x W / 2 for x W / 2 20 Analysis approach for Z0 and Td 5. R|V E ( x 0, y)dy ( x, y) / y( x 0, y)dy z |S z ||Q z ( x)dx W (C / m) T b/2 b/2 y 0 w/ 2 0 s w/ 2 6. Q C V W 2a sin(nW / 2a ) sinh(nb / 2a ) (n ) 2 0 r cosh(nb / 2a ) n 1 odd r 1 Z0 v pC cC 7. Answers!! Td r / c 21 Analysis approach for Z0 and Td (Microstrip Line) y 1. PEC PEC d W x -a/2 2. a/2 The fields in Quasi - TEM mode must satisfy Laplace equation t ( x , y ) 0 where is the electric potential The boundary conditions are ( x , y ) 0 at x a / 2 ( x , y ) 0 at y 0, 2 22 Analysis approach for Z0 and Td (Microstrip Line) 3. Since the center conductor will contain the surface charge, so R| A cos nx sinh ny a a | ( x , y ) S || B cos nax e T n n 1 odd ny / a n for 0 y d for d y n 1 odd 4. The unknowns An and Bn can be solved by two known conditions and the orthogonality of cos function : R|The potential at y d must continuous S|The surface charge distribution for the strip: RS1 T0 T s for x W / 2 for x W / 2 23 Analysis approach for Z0 and Td (Microstrip Line) 5. R|V E ( x 0, y)dy ( x, y) / y( x 0, y)dy A sinh nd z a |S z ||Q z ( x)dx W (C / m) T b/2 b/2 y n 0 0 n 1 odd w/2 s w/ 2 6. C Q V W 4a sin(nW / 2a ) sinh(nd / 2a ) 2 n 1 ( n ) W 0 [sinh( nd / a ) r cosh( nd / a )] odd 24 Analysis approach for Z0 and Td (Microstrip Line) 7. To find the effective dielectric constant e , we consider two cases of capacitance 1. C = capacitance per unit length of the microstrip line with the dielectric substrate r 1 2. C 0 = capacitance per unit length of the microstrip line with the dielectric substrate r 1 e 8. C C0 e 1 Z0 v pC cC Td e / c 25 Tables for Z0 and Td (Microstrip Line) Z 0 ( ) 20 28 40 50 75 90 100 eff 3.8 3.68 3.51 3.39 3.21 3.13 3.09 L0 ( nH / mm) 0.119 0.183 0.246 0.320 0.468 0.538 0.591 C0 ( pF / mm) 0.299 0.233 0.154 0.128 0.083 0.067 0.059 6.54 6.41 6.25 6.17 5.99 5.92 5.88 T0 ( ps / mm) Fr4 : dielectric constant = 4.5 Frequency: 1GHz 26 Tables for Z0 and Td (Strip Line) Z 0 ( ) 20 28 40 50 75 90 100 eff 4.5 4.5 4.5 4.5 4.5 4.5 4.5 L0 ( nH / mm) 0.141 0.198 0.282 0.353 0.53 0.636 0.707 C0 ( pF / mm) 0.354 0.252 0.171 0.141 0.094 0.078 0.071 T0 ( ps / mm) 7.09 7.09 7.09 7.09 7.09 7.09 7.09 Fr4 : dielectric constant = 4.5 Frequency: 1GHz 27 Analysis approach for Z0 and Td (EDA/Simulation Tool) 1. HP Touch Stone (HP ADS) 2. Microwave Office 3. Software shop on Web: 4. APPCAD (http://softwareshop.edtn.com/netsim/si/termination/term_article.html) (http://www.agilent.com/view/rf or http://www.hp.woodshot.com ) 28 Concept Test for Planar Transmission Lines • Please compare their Z0 and Vp (a) (b) 29 (b) (a) (c) 30 (b) (a) (c) 31 32 Loss of Transmission Lines Typically, dielectric loss is quite small -> G0 = 0. Thus Z0 R0 jwL0 jwC0 L0 (1 jx ) 1/ 2 C0 r ( R0 jwL0 )( jwC0 ) a j where R x 0 wL0 • Lossless case : x = 0 • Near Lossless: x << 1 • Highly Lossy: x >> 1 w R0 L0 Highly Lossy Near Lossless w w 33 Loss of Transmission Lines •For Lossless case: • For Near Lossless case: a 0 a L0 C0 R0 2 L0 / C0 L xO L C M1 P N 8Q L F R I Z 1 j G J C H 2 wL K 2 Z0 L0 C0 Time delay T0 0 L0 C0 0 0 0 0 0 Time delay T0 0 L0 1 where C 2T0 / R0 C0 jwC L0 C0 34 Loss of Transmission Lines • For highly loss case: (RC transmission line) a wR0 C0 1 [1 ] 2 2x wR0 C0 1 [1 ] 2 2x Z0 R0 1 [1 ] 2 wC0 2x Nonlinear phase relationship with f introduces signal distortion That’s why telephone company terminate the lines with 600 ohm Example of RC transmission line: AWG 24 telephone line in home F R iwL IJ Z ( w) G H jwC K 0 1/ 2 648(1 j ) where R 0.0042 / in L 10nH / in C 1 pF / in w 10,000rad / s(1600 Hz ) : voice band 35 Loss of Transmission Lines ( Dielectric Loss) The loss of dielectric loss is described by the loss tangent G FR4 PCB tan D 0.035 tan D wC a D GZ 0 ( wC tan D Z 0 ) / 2 f tan D LC 2 36 Loss of Transmission Lines (Skin Effect) • Skin Effect DC resistance AC resistance 37 Loss of Transmission Lines (Skin Effect) s 1 a 2 w 1 length w R( w) area NOTE: In the near lossless region ( R / wL 1), the characteristic impedance Z 0 is not much affected by the skin effect R(w) w R( w) / wL (1 / w ) 1 38 Loss of Transmission Lines (Skin Effect) 100 200 400 800 1200 1600 2000 6.6um 4.7um 3.3um 2.4um 1.9um 1.7um 1.5um R s () 2.6m ohm 3.7m ohm 5.2m ohm 7.4m ohm 9.0m ohm 10.8m ohm 11.6m ohm Trace resistance 1.56 ohm 2.22 ohm 3.12 ohm 4.44 ohm 5.4 ohm 6.48 ohm 7.0 ohm f (MHz) s 1 f Skin depth resistance R s = 6mil Cu f () = 4 10 -7 H / m 17um (Cu) = 5.8 10 7 S / m Length of trace = 20cm 39 Loss Example: Gigabit differential transmission lines For comparison: (Set Conditions) 1. 2. 3. 4. Differential impedance = 100 Trace width fixed to 8mil Coupling coefficient = 5% Metal : 1 oz Copper Question: 1. 2. Which one has larger loss by skin effect? Which one has larger loss of dielectric? 40 Loss Example: Gigabit differential transmission lines Skin effect loss 41 Loss Example: Gigabit differential transmission lines Skin effect loss Why? 42 Loss Example: Gigabit differential transmission lines Look at the field distribution of the common-mode coupling Coplanar structure has more surface for current flowing 43 Loss Example: Gigabit differential transmission lines How about the dielectric loss ? Which one is larger? 44 Loss Example: Gigabit differential transmission lines The answer is dual stripline has larger loss. Why ? The field density in the dielectric between the trace and GND is higher for dual stripline. 45 Loss Example: Gigabit differential transmission lines Which one has higher ability of rejecting common-mode noise ? 46 Loss Example: Gigabit differential transmission lines The answer is coplanar stripline. Why ? 47 48 49 50 51 Intuitive concept to determine Z0 and Td •How physical dimensions affect impedance and delay Sensitivity is defined as percent change in impedance per percent change in line width, log-log plot shows sensitivity directly. Z 0 is mostly influenced by w / h, the sensitivity is about 100%. It means 10% change in w / h will cause 10% change of Z 0 The sensitivity of Z 0 to changes in r is about 40% 52 Intuitive concept to determine Z0 and Td •Striplines impedance Delay 53 Ground Perforation: BGA via and impedance 54 Ground Perforation: Cross-talk (near end) 55 Ground Perforation : Cross-talk (far end) 56 Example(II): Transmission line on non-ideal GND Reasons for splits or slits on GND planes 57 Example(II): Transmission line on non-ideal GND 58 Example(II): Transmission line on non-ideal GND 59 Example(II): Transmission line on non-ideal GND 60 Example(II): Transmission line on non-ideal GND 61 Example(II): Transmission line on non-ideal GND 62 Example(II): Transmission line on non-ideal GND 63 Input side 64 Output side 65 66 67 68 Example: Rambus RDRAM and RIMM Design RDRAM Signal Routing 69 Example: Rambus RDRAM and RIMM Design •Power: VDD = 2.5V, Vterm = 1.8V, Vref = 1.4V •Signal: 0.8V Swing: Logic 0 -> 1.8V, Logic 1 -> 1.0V 2x400MHz CLK: 1.25ns timing window, 200ps rise/fall time Timing Skew: only allow 150ps - 200ps •Rambus channel architecture: (30 controlled impedance and matched transmission lines) Two 9-bit data buses (DQA and DQB) A 3-bit ROW bus A 5-bit COL bus CTM and CFM differential clock buses 70 Example: Rambus RDRAM and RIMM Design RDRAM Channel is designed for 28 +/- 10% Impedance mismatch causes signal reflections Reflections reduce voltage and timing margins PCB process variation -> Z0 variation -> Channel error 71 Example: Rambus RDRAM and RIMM Design • Intel suggested coplanar structure Ground flood & Stitch • Intel suggested strip structure Ground flood & Stitch 72 Example: Rambus RDRAM and RIMM Design PCB Parameter sensitivity: • H tolerance is hardest to control • W & T have less impact on Z0 73 Example: Rambus RDRAM and RIMM Design • • How to design Rambus channel in RIMM Module with uniform Z0 = 28 ohm ?? How to design Rambus channel in RIMM Module with propagation delay variation in +/- 20ps ?? 74 Example: Rambus RDRAM and RIMM Design Impedance Control: (Why?) Loaded trace Unloaded trace Connector 75 Example: Rambus RDRAM and RIMM Design Multi-drop Buses Unloaded Z0 Stub Equivalent loaded ZL ZL L0 CT Electric pitch L L0 CL L 02 L Z0 Device input Capacitance Cd A Multidrop Bus 28 (for Rambus design) where C T is the per - unit - length equivalent capacitance at length L, including the loading capacitance and the unloaded trace capacitance C L is the loading capacitance including the device input capacitance C d , the stub trace capacitance, and the via effect. 76 Example: Rambus RDRAM and RIMM Design In typical RIMM module design stub via Device input capacitance If C L 0.2 pF + 0.1pF + 2.2pF, and If you design unloaded trace Z 0 56 the electric pitch L = 7.06mm to reach loaded Z L 28 L0 Z 0 56 6.77 psec / mm = 379 pH / mm = 9.5 pH / mil C L 2.5 pF 379 pH / mm CT L 02 0.475 pF / mm L Z0 7.06mm 56 2 ZL L0 28.3 CT 77 Example: Rambus RDRAM and RIMM Design • Modulation trace Device pitch = Device height + Device space Electrical pitch L is designed as L Z0 CL Z L 2 (Z0 Z L ) 2 2 If device pitch > electric pitch, modulation trace of 28ohm should be used. Modulation trace length = Device pitch – Electric pitch 78 Example: Rambus RDRAM and RIMM Design • Effect of PCB parameter variations on three key module electric characteristics 79 Example: Rambus RDRAM and RIMM Design • Controlling propagation delay: •Bend compensation •Via Compensation •Connector compensation Bend Compensation • • Rule of thumb: 0.3ps faster delay of every bend Solving strategies: 1. Using same numbers of bends for those critical traces(difficult) 2. Compensate each bend by a 0.3ps delay line. 80 Example: Rambus RDRAM and RIMM Design Via Compensation (delay) For a 8 layers PCB, a via with 50mil length can be modeled as (L, C) = (0.485nH, 0.385pF). Delay T0 LC 13.7 psec 1 Impedance Z 0 = 38 LC Inductive Rule of thumb: delay of a specific via depth can be calculated by scaling the inductance value which is proportional to via length. 30mil 10.6 p sec 50mil This delay difference can be compensated by adding a 1.566mm to the 30mil via has delay 13.7 unloaded trace (56) 81 Example: Rambus RDRAM and RIMM Design Via Compensation (impedance) 82 Example: Rambus RDRAM and RIMM Design Connector Compensation 83 Example: EMI resulting from a trace near a PCB edge Experiment setup and trace design 84 Example: EMI resulting from a trace near a PCB edge Measurement Setup 85 Example: EMI resulting from a trace near a PCB edge EMI caused by Common-mode current : magnetic coupling Measured by current probe 86 Example: EMI resulting from a trace near a PCB edge EMI measured by the monopole : E field Low effect at high frequency 87 Example: EMI resulting from a trace near a PCB edge Trace height effect on EMI 88 Reference 1. 2. 3. 4. 5. Howard W. Johnson, “High-speed digital design”, Prentice-Hall, 1993 Ron K. Poon, “Computer Circuits Electrical Design”, Prentice-Hall, 1995 David M. Pozar, “Microwave Engineering”, John Wiley & Sons, 1998 William J. Dally, “Digital System Engineering”, Cambridge, 1998 Rambus, “Direct Rambus RIMM Module Design Guide, V. 0.9”, 1999 89