Low Phase Noise
Normalized Phase Noise
in UltraCMOS® Devices
W
hat is Phase Noise?
Phase Noise is a measure of the spectral purity of a
signal in an oscillator system. It quantifies the short-term
random variation of the frequency of the signal, and is
a product of thermal noise and low frequency flicker
noise within the system. Most RF systems require an
overall integrated phase noise specification to be met,
as phase noise can corrupt both the up-converted and
down-converted signal paths. For digital systems, the
integrated phase noise can be converted and expressed
as phase jitter.
In the frequency domain, phase noise is typically
quantified at various frequency offsets from the carrier
frequency. Expressed as a ratio in units of dBc/Hz, the
noise power in a 1 Hz bandwidth is measured at each
offset frequency and divided into the carrier power.
If noise sidebands on either side of the carrier are
measured, the phase noise at each offset can be expressed
as a double-sideband value instead of a single-sideband
value.
Phase Noise in PLL Frequency
Synthesizers
A frequency synthesizer is used to generate multiple
output frequencies from a single reference frequency.
Used in a Phase-Locked Loop (PLL), a divided
down output can be compared to a scaled reference,
generating an error signal that drives the loop to achieve
both frequency and phase lock (Fig 1).
Phased-Locked Loop (PLL) phase noise is shaped by
several noise contributors including reference noise,
phase detector noise, and VCO noise. The loop
bandwidth defines the range over which the output
tracks the input. Within the loop bandwidth, the phase
detector drives the VCO to track the reference, and
the phase detector noise dominates the overall phase
noise. At very large-frequency offsets, outside the loop
bandwidth, the loop does not track the reference and the
VCO noise dominates the overall phase noise. Ideally,
the PLL loop bandwidth is designed so that the phase
detector noise floor equals the free-running VCO noise.
C rys tal
R eferenc e
R E F divider
÷R
fc
P has e
detec tor
M ain divider
÷N
L oop
F ilter
VCO
fV C O
Figure 1. Block Diagram of PLL Frequency Synthesizer
Normalized Phase Noise
Phase Detector Phase Noise (dBc/Hz) =
Normalized Phase Detector Noise Floor (dBc/
Hz) +10log (fc) + 20log (N)
where
-80
-90
Phase Noise (dBc/Hz)
Often datasheets, selection guides, or technical
collateral from PLL component vendors advertise
phase noise Figures of Merit (FOM). Peregrine
Semiconductor uses normalized phase noise in
benchmarking its PLL products. By normalizing the
phase detector noise floor to 1 Hz, the phase noise
within the loop bandwidth (dominated by the phase
detector) can be easily calculated for any comparison
frequency and VCO frequency. The mathematical
relationship is specified as follows:
Typical Phase Noise for PE97240
-70
-100
-110
-120
-130
-140
-150
-160
-170
100
1K
10K
100K
1M
10M
100M
Frequency Offset (Hz)
Figure 2. Typical Phase Noise for the PE33241.
VDD = 2.8 V, Temp = 25oC, fvco = 4 GHz, fc = 50 MHz,
Loop Bandwidth = 500 kHz
the phase noise is very close to the calculated value.
At this point in the loop, the 1/f noise has rolled off and
the phase detector noise is the dominant contributor.
fc = comparison frequency
fvco = VCO output frequency
N = fvco/fc
Take for example, the PE33241 5 GHz Integer-N
PLL synthesizer. Fabricated in UltraCMOS®
technology, the PE33241 enables low phase noise
frequency synthesizers for specialized applications.
The datasheet specifies a FOMFloor of -230 dBc/Hz, a
significant improvement over prior generations. The
EVK reference design can be used to calculate the
phase noise as follows:
With fvco = 4 GHz and fc = 50 MHz,
Phase Detector Phase Noise (dBc/Hz) = -230
dBc/Hz + 10log (50 MHz) + 20log(4 GHz/50
MHz) = -115 dBc/Hz
Figure 2 shows the measured phase noise for the
standard EVK reference design.
For a given normalized phase noise, the phase detector
phase noise can be reduced by 3 dB by doubling the
comparison frequency:
With fvco = 4 GHz and fc = 100 MHz, the phase
detector phase noise can be calculated as
Phase Detector Phase Noise (dBc/Hz) = -230 dBc/
Hz + 10log (100 MHz) + 20log (4 GHz/10 MHz)
= -118 dBc/Hz
In this fashion, the user can easily make tradeoffs to
determine if the PLL can meet the overall phase noise
requirements.
Reference:
Peregrine Semiconductor Application Note 16:
“Using Peregrine Phase-Locked Loop Integrated Circuits in Reference and
System Clock Applications."
http://www.psemi.com/pdf/app_notes/an16.pdf
Observing the plot at a frequency offset within loop
where the phase detector noise dominates (100 kHz),
PE33241 Integer-N PLL
ƒƒ Normalized phase noise floor figure of
merit: -230 dBc/Hz
ƒƒ Low power consumption of 80 µA @ 2.8 V
ƒƒ Dual modulus prescaler:
10/11 to 5 GHz and 5/6 to
4 GHz
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