Signal Integrity for Logic Devices
Keywords
Logic, Logic devices, Termination Resisters, Source Side terminations, Termination Schemes, Reflections,
Output Edge Rates, Rise Time, Fall Time, Transmission Lines, IBIS models, Propagation Delays.
Abstract
This document describes the basics of signal integrity, behavior of transmission lines and compares the
output edge rates of various logic devices. It also explains the causes of reflections on a transmission line
and suggests the effective termination schemes to avoid them. Finally, the paper includes examples of
logic devices with integrated source termination resisters from NXP’s portfolio, for better signal integrity in
system.
I. INTRODUCTION: WHAT IS SIGNAL INTEGRITY?
In electronic systems that have ICs communicating with each other at very high speeds, signal integrity is
an important part to ensure system reliability. The key factors that determine signal integrity are the timing
and quality of the signal. It is important that a digital signal, transmitted in the form of a “1” or “0”, is
received as a “1” or “0” at the required time, so it can be sampled and detected correctly. Reflection noise
is commonly the result of impedance mismatch, stubs, vias, or other interconnect discontinuities.
II. COMPARISON OF OUTPUT EDGE RATES
Important parameters that can affect signal integrity are the propagation delay, the rise and fall times, and
the input threshold voltages of the system’s digital logic devices and its analog switches. Figure 1 shows
the IBIS models of 74VHC08 devices from NXP, Fairchild, and Toshiba driving open-ended, unterminated
transmission lines.
Fig. 1 IBIS models of 74VHC08 driving unterminated transmission line
Output waveforms for rising and falling edges are shown in Figures 2 and 3 below. Tables 1 and 2 show the
rise and fall times with the respective slew rates.
Fig. 2 Output rising edge waveforms for circuit in Fig. 1
Fig. 3 Output falling edge waveforms for circuit in Fig. 1
Table 1. Output rise times and slew rates for circuit in Fig.1
Table 2. Output fall times and slew rates for circuit in Fig.1
Feature
NXP
Fairchild
Toshiba
Feature
NXP
Fairchild
Toshiba
Rise Time
3.25 ns
3.663 ns
3.461 ns
Fall Time
3.19 ns
3.49 ns
3.39 ns
0.923 V/ns
0.819 V/ns
0.867 V/ns
0.939 V/ns
0.856 V/ns
0.885 V/ns
Rise Slew Rate
Fall Slew Rate
It can be observed that the output edges of NXP’s VHC logic are faster than the edges of Fairchild’s and
Toshiba’s VHC logic. Typically, the rising output edges of NXP’s VHC logic lead the rising output edges of
Fairchild’s VHC logic by 0.41 ns and Toshiba’s VHC logic by 0.21 ns. And, typically the falling output edges
of NXP’s VHC logic lead the falling output edges of Fairchild’s VHC logic by 0.3 ns and Toshiba’s VHC logic
by 0.20 ns Therefore the VHC logic from these competitors can be replaced with NXP’s VHC logic in a
system, which has enough timing margins as mentioned above.
III. TRANSMISSION LINE AS A DISTRIBUTED LOAD
When a conductor must be considered as a distributed series of inductors and capacitors, it is known as
transmission line. All points on a transmission line do not react to the input stimuli at the same time. In
the digital realm, edge rate most of the time, determines the maximum frequency content, so rise and fall
times can be compared to the size of circuit. A trace on PCB can be treated as a transmission line, if its
length is greater than 1/10 of the signal wavelength. For example, the wavelength of 100 MHz radio wave is
about 3 meters since:
Wave length = D = v/f -------------------------------------  Eqn. 1
Where:
v = phase speed = speed of light = 3 x108 m/s
f = Signal Frequency
In terms of transition times, lower transition time ultimately translates to a higher frequency component
in a system and as a result transmission line theory must be applied for better signal integrity. As a rule of
thumb, if the length of a trace is greater than 1/6 times the ratio of signal rise time and propagation delay
per unit length of wire, trace can be considered as a transmission line i.e.
Wire Length > trise /6* tline -------------------------------- Eqn. 2
Where:
trise = Rise time of signal (ns)
tline = Propagation delay of the wire (ns/in)
IV. REFLECTIONS ON TRANSMISSION LINES
Figure 4 shows the model of NXP’s 74AHC245 transceiver as interface logic, driving three 74AHC245
transceivers, each connected via 28 AWG ribbon cable with characteristic impedance of 110 Ohms. Fig. 4
can be treated as a single cable with connectors spaced every 1.57 inches.
Fig. 4 Model of 74AHC245 transceiver interface logic
Assuming the frequency of output signal is 20 MHz, signal at A0 is shown in red and signal at D0, the last
receiver, is shown in purple in figure 5 below:
Fig. 5 Output signal waveforms for AHC245 transceiver interface logic
Note that the signal integrity for this circuit is acceptable and system will perform reliably as expected. Rise
time of signal at last receiver, shown in purple, is approx. 450 psec and fall time is approx. 454 psec.
Let’s assume that two additional 74AHC245 devices are connected to the interface logic circuit shown in
Fig.1 by using 28 AWG ribbon cables with characteristics impedance of
110 Ohms. New circuit is now shown in Fig. 6 below:
Fig. 6 Model of 74AHC245 transceiver interface logic extended by three more devices
Assuming the frequency of output signal is 20 MHz, signal at D0 is shown in red and signal at B1, the last
receiver, is shown in purple in figure 7 below:
Fig. 7 Output signal waveforms for 74AHC245 extended transceiver interface logic
Please note that the rise time of signal at B1 cell i.e. at the last receiver, has increased to approx. 509 ps
from 450 ps and fall time has increased to 505 ps from 454 ps as a result of additional loading. Since right
hand side of equation 2, is still much greater than the left hand side, there is no transmission line behavior
seen on cable. Overshoots and undershoots in signal at B1 are limited to 726 mV and 791 mV only, which
are not likely to cause any failure in system.
To explore the same phenomena even further, let’s assume that the 5V 74AHC245 logic shown in Fig. 6 is
replaced by the 3V 74LVC245 logic as shown in Fig. 8 below.
Fig.8 Model of 74LVC245A transceiver interface logic replacing 74AHC245 logic
Figure 9 shows that, the output signals at D0 and A1 cells have crossed the input high threshold (2 V at
Vcc = 3.3 V), so there will be a signal integrity issue that could cause system failure. The output signal rise
and fall times at cell B1, the last receiver, are now approximately 530 ps and 398 ps respectively. It can be
concluded that there are signal integrity issues in system as a result of huge reflections (instead of a steady
3.3 V signal level we see 6 V spikes and 1.4 V troughs). The faster transition time of LVC is the cause of
these reflections. If such a design is not done properly, by taking all transmission line effects into account,
system failure as a result of poor signal integrity is more likely.
In order to ensure good signal integrity in a high-speed system similar to the one shown in Figure 8,
one must explore how reflections are produced as a result of transmission line behavior and how these
reflections can be terminated effectively.
Fig.9 Output waveforms for 74LVC245A transceiver interface logic
As shown in Figure 9, the reflection of signals on a transmission line are the main cause of poor signal
integrity. Consider, then, an LVC245A device driving two LVC245A devices which are connected by two
cables, 50 cm or 19.65 inches each and with characteristic impedance of 110 ohms. Figure 10 gives the model of
such a circuit.
Fig. 10 Circuit Model of 74LVC245A for analysis of reflections
As shown in the resulting output waveforms, given in Figure 11, there would be multiple input transitions on the
receiving devices.
Fig. 11 Output waveforms for circuit shown in Fig 10
Figure 12 gives a closer look at the output waveforms
Fig. 12 Output waveforms for circuit shown in Fig. 11 : Zoomed in
The waveforms in Fig. 12 can be analyzed to understand the reflections travelling on the transmission line
as follows:
Let T be the total delay of the transmission line.
At time = 0, the output introduces a positive transition
to the line
After time = T/2, the positive transition reaches the midpoint of the line
After time = T, the positive transition reaches the end of the line where it is fully reflected.
After time = 3T/2, the reflected wave reaches the midpoint, green line increases.
After time = 2T, the reflected waveform is absorbed by the driver. This appears as a negative transition on
the line.
After 5T/2, this negative transition reaches the midpoint, green line descends.
After 3T, the negative transition reaches the end of the line where it is fully reflected.
As a result, a ringing of period 4T is seen on the line. The transmission line is not a lossless medium and as
a result, the reflections back and forth will be attenuated as shown more clearly in Fig. 13 below.
Fig. 13 Ringing of period 4T in output waveforms of circuit in Fig. 5
V. TERMINATION RESISTER SCHEMES TO AVOID REFLECTIONS
Now, in order to solve this issue, let’s look at the high frequency model of a transmission line as shown in
Fig. 14 below:
Fig. 14 High frequency model of a transmission line
Now, the characteristic impedance and time delay of transmission line can be defined as follows:
Zo = Lo/Co ---------------------------------------- Eqn. 3
TD = τ = √ LoCo
Where:
Zo = Characteristic Impedance of Transmission Line
TD = Time delay for a signal to propagate down a transmission line of length x
Lo = Total series inductance for unit length of transmission line
Co = Total shunt capacitance for unit length of transmission line
Reflection coefficient is another important parameter that determines the quality of signal travelling on a
transmission line. It is defined as the ratio of the reflected voltage to the incident voltage seen at a given
junction. A junction is impedance discontinuity, which could be a section of transmission line with different
characteristic impedance,
a terminating resister, or the input impedance of a buffer
on chip. Reflection coefficient can be calculated as:
Ρ = Reflection Coefficient =
Vreflected /Vincident = (Zt – Zo)/(Zt + Zo)
Where:
Zt = Impedance of discontinuity for Transmission Line
Zo = Characteristic Impedance of Transmission Line
The equation assumes that the signal is travelling on a transmission line with characteristic impedance of
Zo and encounters Zt, an impedance of discontinuity. Now, if Zt = Zo, the reflection coefficient is zero and
there will be no reflection, such a case is known as a transmission line with matched termination. However,
if there is impedance mismatch i.e Zt = Zo, there will be a portion of incident wave reflected back to the
source. The magnitude of this reflection VR is given by:
VR = Ρ x Vi where Vi is incident wave
The reflected component will then travel back to the source and possibly generate another reflection off
the source. This reflection and counter reflection continues until the line has reached a stable condition.
This phenomenon can be observed in figs. 9, 11 and 12 above. Fig. 15 below also shows the graphical
representation of this discussion. Z s is the source resistance and initial voltage Vi is governed by voltage
divider of source resistance and the line impedance.
Fig. 15 Incident signal reflected from unmatched load on a transmission line
Termination resisters are used in various different ways to match the impedance of transmission line with
the effective impedance of discontinuity. For example, the effective bus impedance of circuit shown in Fig.
8, can be calculated by using equation 3 where Lo is approx. 12.57 nH/inch and Co is replaced by Co + CL.
Equation 3 now becomes:
Zo (effective) = √Lo/(Co + CL ) ------------------------ Eqn. 4
The value of Co per bus model of the transmission line is approximately 1 pF/inch. CL is determined by
using a typical 3 pF input capacitance spaced every 4 cm or 1.57 inches, which gives approximately 1.91
pF/ inch for CL . From Equation 4, the value of the effective bus impedance can be calculated as 66 ohms.
Now, starting with the model shown in Figure 8, we use a 74LVC245A transceiver interface logic to replace
the 74AHC245 logic, and insert an end termination of 66 ohms before the last receiver. This is shown in
Figure 16.
Fig.16. Model of 74LVC245A transceiver interface logic replacing 74AHC245 logic with end termination
This form of termination results in the last receiver on the bus switching last as shown in Fig. 17. We see
that there is good signal integrity (the switching threshold point is clear of any oscillations).
Fig. 17 Output waveforms for circuit shown in Fig 16
Now a resistor equal to the bus impedance is inserted in series between the driver and bus. This type of
termination is called as source termination. The circuit is shown in Fig. 18 below:
Fig.18. Model of 74LVC245A transceiver interface logic replacing 74AHC245 logic with source termination
A single reflection is permitted, once this reflection reaches the driver, the combined impedance of the
source resistor and driver resistance acts to terminate the line.
The initial amplitude entering the line (after the resistor) is Vin = Voh/2 [resistor divider.] There is no end
termination so the reflection Vr = Vin. This results in a level at the end of the line of Voh, which propagates
back to the source. As a result, the last receiver on the bus is switched first; the first receiver is then
switched by the reflected waveform. Output waveforms for circuit of Fig. 18 using 66 Ohms source
termination are shown in Fig 19 below.
Fig. 19 Output waveforms for circuit shown in Fig. 18 with source termination of 66 Ohms
Source termination is recommended for point to point (single driver, single receiver) applications. However
in point to multi-point applications a lower source resistor can be used to ensure a voltage level above the
switching threshold point is seen by the first receiver. This results in a larger initial reflection and the failure
to completely suppress subsequent reflections. However from a signal integrity standpoint the reflections
do not cause the waveform to cross the switching threshold point. For example, Fig. 20 shows the output
waveforms if 66 Ohms source termination of circuit in Fig 18 is changed to 30 Ohms.
Fig. 20 Output waveforms for circuit shown in Fig. 18 with source termination of 30 Ohms
VI. NXP’S LOGIC DEVICES WITH INTEGRATED SOURCE TERMINATION RESISTERS
NXP offers the option of integrated source termination resisters for different logic functions in various
families like LVC, ALVC, LVT, ALVT, AVC and ABT. Table 3 shows some examples of logic functions and
families available with integrated source termination resisters. For complete list of products, please visit:
http://ics.nxp.com/logic/
Part Number
74LVC2245A
Description
Package
3.3 V Transceiver with Direction Pin; Non-Inverting with 30 Ω Termination resistors (3-State)
74LVC162244A
3.3 V 16-Bit Buffer/Line Driver; Non-Inverting with Bus Hold and 30 Ω Termination resistors (3-State)
20 pin SO, SSOP, TSSOP and DQFN
48 pin SSOP and TSSOP
74ALVC162834A
3.3 V 18-Bit Registered Driver with Inverted Register Enable with 30 Ω Termination resistors (3-State)
56 pin TSSOP
74ALVCH162245
3.3 V 16-Bit Transceiver with Direction Pin; Non-Inverting with Bus Hold and 30 Ω Termination resistors (3-State)
48 pin SSOP and TSSOP
3.3 V 16-bit buffer/driver; inverting with 30 Ω Termination resistors (3-state)
48 pin SSOP and TSSOP
3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω Termination resistors (3-state)
48 pin SSOP and TSSOP
74ALVT162821
3.3 V 20-bit D-type flip-flop; positive edge trigger with bus hold and 30 Ω Termination resistors (3-state)
56 pin SSOP and TSSOP
74ALVT162241
3.3 V 16-Bit Buffer/Line Driver; Non-Inverting with Bus Hold and 30 Ω Termination resistors (3-State)
48 pin SSOP and TSSOP
74AVCM162835
2.5 V 18-Bit Registered Driver with 15 Ohm Termination resistors and 3.6 V Tolerant I/Os (3-State
56 pin TSSOP
74ABT162245A
5 V 16-Bit Transceiver with Direction Pin; Non-Inverting with Bus Hold and 30 Ω Termination resistors (3-State)
48 pin SSOP and TSSOP
74LVT162240A
74LVT162374
VII. CONCLUSIONS
1.The most important characteristics of logic families in signal integrity are the output edge rate and the
input threshold voltage.
2.The faster the output transition the sooner an application requires transmission line termination to be applied.
3.A poorly terminated transmission line will oscillate with a period 4T (where T is the propagation delay of
the transmission line).
4.In multiple receiver applications the effective bus impedance differs from the characteristic impedance
of the transmission line.
5.Source termination is an optional feature of low voltage logic.
6.NXP’s VHC logic devices can replace VHC logic devices from Fairchild and Toshiba without signal
integrity issues in a system, which can accept a signal faster than the reference signal by 0.3 ns
(considering output of Fairchild’s VHC logic as reference) and by 0.15 ns (considering output of Toshiba’s
VHC logic as reference).
TABLE OF CONTENTS
I. Introduction: What is Signal Integrity?
II. Comparison of Output Edge Rates
III. Behavior of Transmission Lines
IV. Reflections on Transmission Lines
V. Termination Resister Schemes to avoid Refections
VI. NXP’s Logic Devices with Integrated Source Termination Resisters
VII.Conclusions
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© 2011 NXP Semiconductors N.V.
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Date of release: August 2011
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