Introduction to
CMOS VLSI
Design
Lecture 8:
Combinational Circuits
David Harris
Harvey Mudd College
Spring 2004
Outline
q
q
q
q
q
q
q
Bubble Pushing
Compound Gates
Logical Effort Example
Input Ordering
Asymmetric Gates
Skewed Gates
Best P/N ratio
8: Combinational Circuits
CMOS VLSI Design
Slide 2
Example 1
module mux(input s, d0, d1,
output y);
assign y = s ? d1 : d0;
endmodule
1) Sketch a design using AND, OR, and NOT gates.
8: Combinational Circuits
CMOS VLSI Design
Slide 3
Example 2
2) Sketch a design using NAND, NOR, and NOT gates.
Assume ~S is available.
8: Combinational Circuits
CMOS VLSI Design
Slide 5
Example 3
3) Sketch a design using one compound gate and one
NOT gate. Assume ~S is available.
8: Combinational Circuits
CMOS VLSI Design
Slide 8
Compound Gates
q Logical Effort of compound gates
unit inverter
AOI21
Y =A
Y = Ag B + C
Y = Ag B + C g D
A
B
C
A
B
C
D
A
Y
A
A
2
1
Y
AOI22
Y
4 B
C
A
2
B
2
4
4
C
Y
1
Complex AOI
Y
A
4 B
4
C
4 D
4
A
2 C
2
B
2 D
2
Y
Y = Ag( B + C ) + D g E
D
E
A
B
C
Y
B
6
C
6
A
3
D
6
E
6
E
2
A
2
D
2
2
C
gA = 3/3
gA = 6/3
gA =
gA =
p = 3/3
gB = 6/3
gB =
gB =
gC = 5/3
gC =
gC =
p = 7/3
gD =
gD =
p=
gE =
B
Y
2
p=
8: Combinational Circuits
CMOS VLSI Design
Slide 10
Example 4
q The multiplexer has a maximum input capacitance of
16 units on each input. It must drive a load of 160
units. Estimate the delay of the NAND and
compound gate designs.
8: Combinational Circuits
CMOS VLSI Design
Slide 12
NAND Solution
D0
S
Y
D1
S
8: Combinational Circuits
CMOS VLSI Design
Slide 14
Compound Solution
D0
S
D1
S
8: Combinational Circuits
CMOS VLSI Design
Y
Slide 16
Example 5
q Annotate your designs with transistor sizes that
achieve this delay.
Y
8: Combinational Circuits
CMOS VLSI Design
Y
Slide 18
Input Order
q Our parasitic delay model was too simple
– Calculate parasitic delay for Y falling
• If A arrives latest?
• If B arrives latest?
2
2
A
2
B
2x
8: Combinational Circuits
Y
6C
2C
CMOS VLSI Design
Slide 20
Inner & Outer Inputs
q Outer input is closest to rail (B)
q Inner input is closest to output (A)
2
A
B
q If input arrival time is known
– Connect latest input to inner terminal
8: Combinational Circuits
CMOS VLSI Design
2
Y
2
2
Slide 22
Asymmetric Gates
q Asymmetric gates favor one input over another
q Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
A
– Boost size of noncritical input
reset
– So total resistance is same
q gA =
2
Y
A
4/3
q gB =
reset
q gtotal = gA + gB =
q Asymmetric gate approaches g = 1 on critical input
q But total logical effort goes up
8: Combinational Circuits
CMOS VLSI Design
Y
Slide 23
Symmetric Gates
q Inputs can be made perfectly symmetric
2
2
A
1
1
B
1
1
8: Combinational Circuits
CMOS VLSI Design
Y
Slide 25
Skewed Gates
q Skewed gates favor one edge over another
q Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
HI-skew
inverter
unskewed inverter
(equal rise resistance)
2
A
unskewed inverter
(equal fall resistance)
2
Y
1/2
A
1
Y
A
1
Y
1/2
q Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
– gu =
– gd =
8: Combinational Circuits
CMOS VLSI Design
Slide 26
HI- and LO-Skew
q Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.
q Skewed gates reduce size of noncritical transistors
– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
q Logical effort is smaller for favored direction
q But larger for the other direction
8: Combinational Circuits
CMOS VLSI Design
Slide 28
Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
1
2
Y
2
A
NOR2
Y
gu = 1
gd = 1
gavg = 1
A
2
B
2
B
4
A
4
Y
1
gu = 4/3
gd = 4/3
gavg = 4/3
1
gu = 5/3
gd = 5/3
gavg = 5/3
B
HI-skew
Y
2
A
1/2
Y
gu = 5/6
gd = 5/3
gavg = 5/4
A
A
Y
B
gu =
gd =
gavg =
gu =
gd =
gavg =
B
LO-skew
Y
1
A
1
Y
gu = 4/3
gd = 2/3
gavg = 1
8: Combinational Circuits
A
A
B
Y
gu =
gd =
gavg =
CMOS VLSI Design
gu =
gd =
gavg =
Slide 29
Asymmetric Skew
q Combine asymmetric and skewed gates
– Downsize noncritical transistor on unimportant
input
– Reduces parasitic delay for critical input
A
reset
Y
1
A
reset
8: Combinational Circuits
2
Y
4/3
4
CMOS VLSI Design
Slide 32
Best P/N Ratio
q We have selected P/N ratio for unit rise and fall
resistance (µ = 2-3 for an inverter).
q Alternative: choose ratio for least average delay
q Ex: inverter
P
– Delay driving identical inverter
A
1
– tpdf =
– tpdr =
– tpd =
– Differentiate tpd w.r.t. P
– Least delay for P =
8: Combinational Circuits
CMOS VLSI Design
Slide 33
P/N Ratios
q In general, best P/N ratio is sqrt of equal delay ratio.
– Only improves average delay slightly for inverters
– But significantly decreases area and power
Inverter
NAND2
2
fastest
P/N ratio
A
1.414
Y
1
gu =
gd =
gavg =
8: Combinational Circuits
NOR2
2
Y
A
2
B
2
B
2
A
2
Y
gu =
gd =
gavg =
CMOS VLSI Design
1
1
gu =
gd =
gavg =
Slide 35
Observations
q For speed:
– NAND vs. NOR
– Many simple stages vs. fewer high fan-in stages
– Latest-arriving input
q For area and power:
– Many simple stages vs. fewer high fan-in stages
8: Combinational Circuits
CMOS VLSI Design
Slide 37