Combinational Logic Gates in CMOS
References:
Adapted from: Digital Integrated Circuits: A Design
Perspective, J. Rabaey, Prentice Hall © UCB
Principles of CMOS VLSI Design: A Systems Perspective,
N. H. E. Weste, K. Eshraghian, Addison Wesley
Adapted from: EE216A Lecture Notes by Prof. K. Bult ©
UCLA
Ratioed Logic
Reduce the number of devices over complementary logic
Ratioed Logic
• Use PDN to implement the function (which is the
negation of the network)
• Total number of devices: n for the input, 1 for the
static load
• Minimum load is 1 unit-gate load
• Functional sizing is required to optimize noise margin
Trade-offs to be Considered
• To reduce static power, ILoad should be low
• To obtain a reasonable NML, VOL = ILoadRPDN should
be low
• To reduce tpLH ≈ CLVDD/(2ILoad), ILoad should be high
• To reduce tpHL ≈ 0.69 RPDNCL, RPDN should be kept
small
Improving DC and AC Characteristics
• Bias circuit to force VOL below threshold
• Build better load to improve VOL and switching time
• Use differential logic to eliminate static current
Forcing the Voltage Output Low
Adaptive Load
Improved Loads
Differential Cascade Voltage Switch Logic (DCVSL)
Example
Pass Transistor Logic
Pass-Transistor Logic
A
Switch
Network
B
B
B
• Reduced number of transistors
• No static power consumption
Pass Transistor Logic
Control Signal
P
Pass
Signal
F = Product Term
V
⎧Z
F =⎨
⎩V
if P = 0
if P = 1
Basic Pass Transistor Logic Model
Control Signals
Pi
Pass
Signals
Vi
F = Sum of Products
F = P1 (V1 ) + P2 (V2 ) + " + Pn (Vn )
XNOR Gate
Truth Table
A
B
OUT
Pass Function
0
0
1
-A + -B
0
1
0
A + -B
1
0
0
-A + B
1
1
1
A+B
Modified Karnaugh Map
A
0
0
-A
-A
-B
B
1
1
A
B
A
-B
B
Boolean Function Unit
Operation
P1 P2 P3 P4
AND(A,B)
0
0
0
1
XOR(A,B)
0
1
1
0
OR(A,B)
0
1
1
1
NOR(A,B)
1
0
0
0
NAND(A,B)
1
1
1
0
NMOS-only switch
Problem: VB does not pull up to VDD, only to VDD - Vtn(body-effect)
Cannot completely turn off the PMOS transistor
Causes static power consumption
Solution 1: Transmission Gate
Transmission Gate Implementation
A
A
-A B
-A
B
-B
-B
P1
P2
F(A,B)
P3
F(A,B)
P4
B
P1
P2
P3
P4
-B
Transmission Gate XNOR
A
-B
OUT
-A
B
A
Transmission Gate (Inverting) Multiplexer
S
S
S
S
VDD
S
A
V DD
M2
F
S
M1
B
S
GND
In1
In2
Transmission Gate XOR
Resistance of Transmission Gate
B is discharged originally
For NMOS, VGS = VDS, saturated or cutoff
For PMOS, VGS = -VDD, VDS increases from
-VDD to 0, starts out in saturation, then
transitions into non-saturation
Vout < Vtp : NMOS saturated, PMOS saturated
Vtp < Vout < VDD − Vtn :
NMOS saturated, PMOS linear
VDD − Vtn < Vout :
NMOS cutoff, PMOS linear
Resistance of Transmission Gate
Vout
Approximations
• Assume both in linear region, ignore body effect
Geq =
=
1
Req
β n (VDD − VB − Vtn )(VA − VB )
(VA − VB )
+
β p (VDD + Vtp )(VA − VB )
(VA − VB )
≈ β n (VDD − Vtn ) + β p (VDD + Vtp )
• Assume both in saturated region
Geq =
=
In + I p
VDD
β n (VDD − Vtn ) 2 + β p (VDD + Vtp ) 2
2VDD
When Output Closely follows Input
pmost
Region A:
NMOS unsaturated, PMOS off
nmost
Ron
Region B:
NMOS unsaturated, PMOS unsaturated
Region C:
NMOS off, PMOS unsaturated
Transmission gate
Vin
Delay in Transmission Gate Networks
Distributed RC network
Elmore Delay
To solve for actual delay
dVi (t )
1
[Vi +1 (t ) + Vi −1 (t ) − 2Vi (t )]
=
dt
Req C
Estimate the dominant time constant:
assume all internal nodes are pre-charged to VDD,
and a step input is applied
n(n + 1)
τ N = ∑ C ∑ Req = ∑ Req ∑ C =
Req C
2
k =1
j =k
k =1
j =k
N
N
N
N
Delay Optimization by Buffer Insertion
n(n + 1)
Req C
• Delay of RC chain t p = 0.69τ N = 0.69
2
• Delay of buffered chain
⎤ ⎛n ⎞
⎡ n m(m + 1)
t p = 0.69⎢
Req C ⎥ + ⎜ − 1⎟t pbuf
2
⎦ ⎝m ⎠
⎣m
⎤ ⎛n ⎞
⎡ n(m + 1)
Req C ⎥ + ⎜ − 1⎟t pbuf
= 0.69⎢
⎦ ⎝m ⎠
⎣ 2
mopt = 1.7
t pbuf
Req C
Transmission Gate Full Adder
P
VDD
Ci
A
P
A
A
P
B
VDD
Ci
A
P
Ci
S Sum Generation
Ci
P
B
Setup
VDD
A
Co Carry Generation
P
Ci
A
VDD
P
Adder Truth Table
C
A
B
A.B(G)
A+B
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
1
1
A + B(P) SUM
SUM = A + B + C
CARRY = C if A + B = 1
CARRY = A (or B) if A + B = 0
CARRY
Solution 2:
Level Restoring Transistor for NMOS Only Logic
• Full Swing
• Disadvantage: More complex, larger capacitance
Level Restoring Transistor
3.0
without
without
3.0
with
VB
1.0
-1.00
with
5.0
VX
Vout (V)
5.0
2
t (nsec)
1.0
4
(a) Output node
6 -1.00
2
4
t (nsec)
(b) Intermediate node X
6
Proper Sizing of Level Restoring Transistor
• In transient, conducting path from Mr to M3 via Mn
when A is low, B switches from low to high, and X is
high
• Mr must not be too large, otherwise, X cannot be
brought below threshold voltage, VM, of inverter, Mr
cannot be turned off
Sizing of a Level Restorer
I = β 3 (VDD − Vtn )VA
=
βn
2
(VB − VA − Vtn ) 2
⎡
(VDD − VM ) 2 ⎤
= β r ⎢(VDD + Vtp )(VDD − VM ) −
⎥
2
⎣
⎦
Sizing of a Level Restorer
VDD = 5V
Vtn = −Vtp = 0.75V
VM = 2.5V
⎡
(VDD − VM ) 2 ⎤
I = β r ⎢(VDD + Vtp )(VDD − VM ) −
⎥ = 7 .5 β r
2
⎣
⎦
I = β 3 (VDD − Vtn )VA
βr
⇒ VA = 1.76
βn
if M 3 and M n are of equal size
VB ≤ VDD
⇒ VB = 3.87
βn
m=
> 1.55
βr
βr
β
+ 1.76 r + 0.75 ≤ 5V
βn
βn
Proper Sizes of Restorer
Making the NMOS pass-transistor and
PMOS restorer the same size is reasonable
Solution 3: Single Transistor Pass Gate with VT=0
VDD
VDD
0V
5V
VDD
0V
Out
5V
WATCH OUT FOR LEAKAGE CURRENTS
Complimentary Pass Transistor Logic
A
A
B
B
Pass-Transistor
Network
F
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
A
F=A⊕ΒÝ
(b)
A
A
B
B
F=A+B
B
OR/NOR
A
EXOR/NEXOR
F=A⊕ΒÝ
4 Input NAND in CPL
• Total number of transistors needed = 14 (including
the final buffer)
• But AND function is simultaneously present
• tpHL = 1.05ns, tpLH = 0.45ns
Dynamic Logic
Dynamic Logic
VDD
φ
VDD
φ
Mp
Me
Out
CL
In1
In2
In3
PDN
In1
In2
In3
PUN
Out
φ
Me
φ
φn network
2 phase operation:
Mp
φ p network
• Precharge
• Evaluation
CL
Example
•
•
•
•
•
•
N + 2 transistors
Ratioless
No static power consumption
Small Noise Margins (NML)
Requires Clock
Pull-down resistance increases
due to the evaluation transistor
Transient Response
6.0
φ
Vout (Volt)
4.0
Vout
EVALUATION
PRECHARGE
2.0
0.0
0.00e+00
2.00e-09
t (nsec)
4.00e-09
6.00e-09
Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4
φ
GND
Reliability Problems — Charge Leakage
VDD
φ
φ
Mp
Out
(1)
CL
t
A
(2)
φ
Vout
precharge
evaluate
Me
t
(a) Leakage sources
(b) Effect on waveforms
Dynamic
circuits
a minimal
clock rate
Minimum
Clockrequire
Frequency:
> 1 MHz
Charge Sharing (redistribution)
case 1) if ∆V out < VTn
VDD
φ
Mp
Out
CL
A
Ma
B=0
φ
Mb
Me
X
Ca
Cb
C L VDD = C L Vout ( t ) + Ca ( VDD – V Tn ( V X ) )
or
Ca
∆ V out = Vout ( t ) – V DD = – -------- ( V DD – V Tn ( V X ) )
CL
case 2) if ∆V out > VTn
C
a -⎞
⎛ --------------------∆Vout = –V DD ⎜
Ca + CL ⎟
⎝
⎠
Minimize Charge Sharing
• Keep the change in storage voltage below | Vtp |
– the output might be connected to a static inverter as in
Domino logic
Vtp
Ca
<
= 0.2
C L VDD − Vtn
• Ca is normally smaller than CL, but if there is series
connection of NMOS transistors, internal
capacitances can be strung together and that can
increase the voltage change
Charge Redistribution - Solutions
VDD
VDD
φ
Mp
φ
Mbl
Mp
Mbl
Out
Out
A
Ma
A
Ma
B
Mb
B
Mb
φ
Me
φ
Me
(a) Static bleeder
(b) Precharge of internal nodes
φ
Clock Feedthrough
VDD
φ
could potentially forward
bias the diode
Mp
Out
CL
A
B
φ
Ma
Mb
Me
5V
φ
X
Ca
Cb
overshoot
out
Clock Feedthrough and Charge Sharing
feedthrough
output without redistribution (Ma off)
6
out
4
V (Volt)
φ
internal node in PDN
2
0
0
1
2
t (nsec)
3
Cascading Dynamic Gates
VDD
φ
VDD
φ
Mp
Mp
Out2
Out1
V
φ
In
Out1
VTn
In
∆V
Out2
φ
φ
Me
(a)
Me
t
(b)
Only 0→1 Transitions allowed at inputs!
Domino Logic
VDD
VDD
VDD
φ
φ
Mp
Mp
Out1
Mr
Out2
In1
In2
PDN
PDN
In4
In3
φ
Me
φ
Me
Static Inverter
with Level Restorer
Domino Logic - Characteristics
• Only non-inverting logic
• Very fast - Only 1→0 transitions at input of inverter
affects the next Domino
• Static inverter increases noise immunity, increase the
size of PMOS to increase VM
• Proper sizing of inverter to drive the fan-out in optimal
way
• Add a level-restoring transistor to overcome charge
sharing and charge loss
np-CMOS (Zipper CMOS)
VDD
φ
In1
In2
In3
Mp
PDN
VDD
φ
Out1
Me
PUN
In4
Out2
φ
Me
φ
Mp
Only 1→0 transitions allowed at inputs of PUN
Reduced noise margins: NMH = | Vtp |, NML = | Vtn |
Full Adder Circuit
A
A
B
B
A
B
C
A
B
C
C
-carry
-sum
C
B
A
C
A
B
B
A
B
C
A
np CMOS Adder
VDD
φ
A1
VD D
VDD
φ
φ
B1
B1
A1
A1
φ
φ
B1
B0
φ
Ci0
Carry Path
B1
VDD
A0
φ
Ci1
A1
VDD
φ
B0
Ci1
S1
φ
VDD
A0
φ
φ
Ci2
VD D
φ
Ci1
A0
B0
φ
Ci0
φ
B0
A0
Ci0
S0
Manchester Carry Chain Adder
VDD
φ
0.5
P0
P1
M0
M1
3
Ci,0
φ
3.5
4
G0
3
2.5
G1
3.5
P2
M2
2.5
3
P3
M3
2
G2
2
1.5
G3
2.5
Total Area:
225 µm × 48.6 µm
P4
M4
1.5
2
1
G4
1
1.5
Co,4
Adder Truth Table
A + B(P) SUM
CARRY
C
A
B
A.B(G)
A+B
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
1
1
SUM = A + B + C = P + C
CARRY = C if P = 1
CARRY = AB if P = 0
CARRY = G + PC
CMOS Circuit Styles - Summary