U niversity of S outhern C alifornia
School Of Engineering
Department Of Electrical Engineering
EE 448:
Homework Assignment #01
( Assigned 08/27/01; Due 09/10/01)
Fall, 2001
Choma
Problem #01:
Wideband analog and high-speed digital integrated circuits necessarily use
minimal geometry transistors whose small breakdown voltages preclude their capability to sustain large collector-emitter (or drain-source) voltages over even relatively small time periods.
To protect these devices from transient voltage overstress, a second order LC filter of the form
shown in Fig. (P1) is often inserted between the ON/OFF power line switch and the power supply pad of the integrated circuit. In this circuit, Rl represents the steady state load to which
power is to be supplied and is nominally the ratio of the steady state load voltage -to- the steady
state load current. Thus, if the desired quiescent pad voltage of an integrated circuit is 3.3 volts
and if this circuit is to draw a quiescent current of 12 mA, Rl = 3.3/12 mA = 275 . The filter
itself consists of the inductance, Ls, which includes any parasitic inductance associated with the
power supply bus line routing on chip, and the capacitance, Cl, which includes parasitic power
supply pad capacitance. The resistance, Rs is generally small and includes the effects of power
bus losses and finite inductance quality factor (Q). By the way, the rubberized or plastic-coated
“bump” you see in the power line that connects your laptop computer to an energy source is the
inductance in Fig. (P1). The indicated voltage, Vp is the Thévenin energizing voltage for the
chip, while the switch, which is closed at time t = 0, allows the filter input voltage, vi(t), to
emulate the step function, Vpu(t). It is to be understood that the fundamental purpose of the filter
is to slow the rate of power delivery from the input port, where vi(t) is measured, -to- the output
port, where voltage vo(t) is established, so that vo(t) rises monotonically with time toward its
steady state value with little or no voltage overshoot.
Rs
Ls
vi(t)
vo(t)
t=
0

Rl
Cl
Vp

Fig. (P1)
(a). The filter in Fig. (P1) is clearly a second order circuit. In view of the discussion provided
above, should the circuit poles, whose frequencies might be labeled, p1 and p2, be real
numbers or complex conjugates? Briefly explain your rationale.
(b). Derive an expression for the transfer function, H(s) = Vo(s)/Vi(s) and in the process, show
EE 448
University of Southern California
J. Choma, Jr.
that the pole frequencies satisfy the relationships,
Ls
1
1


 R R C
s l
l
p1
p2
Rl  Rs


and
 R

l
 L C  H( 0 )L C .
 
s l

p1 p2
R  Rs  s l
 l

(c). Assume that the poles are real and that their frequencies relate as p2 = kp1, where k is
understood to be greater than or equal to one. For k > 1, show that the time domain
response, normalized to the steady state value of the response, is
vo ( t )
 k   p1 t
 1  k p1 t
von ( t ) 
 1  
 
,
e
e
H( 0 )V p
 k  1
 k  1
1
while for k = 1, confirm that
vo ( t )
von ( t ) 
 1 
H( 0 )V p
1  p t  e
1
 p1 t
.
(d). Plot the normalized responses determined in Part (c) -versus- the normalized time parameter, tn = p1t for k = 1, 1.5, 3, and 10. What value of k might be desired to ensure the realization of the slowest possible step response for any given real number value of p1?
(e). Let TR represent the rise time of the filter; that is, TR is the time required after the switch is
closed for the output response to achieve 90% of its steady state value. For the optimal
value of k (in the sense of a maximally slowed response) determined in Part (d), confirm
that p1TR  3.9.
(f). Assume now that Rl >> Rs and Ls >> RsRlCl. For the optimal operating condition stipulated in Part (e), show that a rise time of TR is achieved if
Ls 
T
R
 Rl  Rs 
1.95
and
C 
l
T
R
.
7.8Rl
(g). Assume that a certain integrated circuit is to be energized by a 3.3 volt battery that is
switched on at time t = 0. Assume further that the net effective Thévenin source resistance
(Rs) is 15  and that the effective steady state load resistance (Rl) is 1020 . The latter
resistance corresponds nominally to 3.3 volts delivered to a load drawing 3.23 mA. A 0 to- 90% rise time (TR) of at least 200 μSEC is desired to protect the active devices in the
given circuit. Design the protection filter and simulate it on SPICE to confirm the stipulated rise time objective.
Problem #02:
The two transistors in the simple amplifier of Fig. (P2) are minimum
geometry devices manufactured in a commercially available silicon-germanium heterostructure
Homework #01
2
Fall Semester, 2001
EE 448
University of Southern California
J. Choma, Jr.
process. This particular transistor delivers an optimal gain-bandwidth product (fT) of the order
of 55 GHz when it is biased at a collector current of 1.6 mA and a collector -to- emitter voltage
of 1.6 volts. At this operating point objective, VBE is about 822 mV, and hFE is approximately
107.
VCC
RCC
R1
Q1
Q2
RE
R2
Fig. (P2)
(a). Design the biasing circuit with VCC = 3.3 volts and RE = 150 . Allow the two transistors
to conduct nominally identical collector currents.
(b). Simulate the circuit on SPICE using the (realistic) SPICE parameters itemized below. If
necessary, adjust the biasing elements to ensure that transistor Q1 operates very near its
collector current and collector-emitter voltage optimum. At this quiescent operating point,
note and record the low frequency small signal parameters (base resistance rb, base-emitter
diffusion resistance r, Early resistance ro, current gain ac, internal emitter resistance re,
and internal collector resistance rc) of each transistor. Also, record for use in the subsequent problem the static current supplied to the circuit by the VCC power supply.
SPICE PARAMETERS - MINIMAL GEOMETRY NPN SiGe TRA NSISTOR
IS = 85.56746e-18 amps
VAF = 120 volts
BR = 0.1
ISC = 490e-21 amps
RE = 13.6 
MJE = .4
XCJC = 0.39
FC = 0.9
VTF = 1.8 volts
CN = 2.42
NC = 2.0
EG = 1.18 volts
IKF = 6.5 mA
NR = 0.993
RB = 204.402 
RC = 62.9 
CJC = 4.5 fF
CJS = 8.9 fF
TF = 1.78 pSEC
ITF = 30 mA
D = 0.87
BF = 135
ISE = 21.1923 fA
VAR = 800 volts
RBM = 13.2 
CJE = 25.4 fF
VJC = 0.78 volts
VJS = 0.80 volts
TR = 10.0 pSEC
XTB = 1.5
AF = 1.0
NF = 0.9979
NE = 2.34
IKR = 50 μA
IRB = 21.667 μA
VJE = 1.2 volts
MJC = 0.333
MJS = 0.50
XTF = 10
KF = 1.0e-12
XTI = 3.0
Problem #03:
The purpose of this problem is to examine the effectiveness of the filter
studied in Problem #01 on the biasing circuit examined in Problem #02.
Homework #01
3
Fall Semester, 2001
EE 448
University of Southern California
J. Choma, Jr.
(a). First, supplant the VCC battery by a zero -to- 3.3 volts pulse waveform whose pulse width is
perhaps a nanosecond and whose period is as long as 4 nSEC. To avoid SPICE convergence problems, let this pulse have 2 pSEC rise and fall times. Simulate the resultant circuit on SPICE and examine the voltage, vce(t) developed across the collector -to- emitter
terminals of transistor Q1. What problems do you see relative to precluding breakdown,
which occurs for this transistor at a collector-emitter voltage of approximately 2.3 volts?
Might you be able to rationalize, albeit qualitatively, the observed problems in terms of the
time domain voltage, vbe(t), developed across the base -to- emitter terminals of Q1?
(b). Now use the filter to generate the power line voltage, VCC = 3.3 volts in the steady state.
Design the filter for a rise time of 200 μSEC, and adjust the amplitude of voltage Vp so that
VCC is indeed nominally 3.3 volts in the steady state. Test your design on SPICE to ensure
that the optimum quiescent operating point is achieved under steady state operating circumstances. Examine the resultant waveform, vce(t), and compare the result with that observed in Part (a). Does the filter do its job in the sense of precluding voltage breakdown?
Problem #04:
A signal source, vs, whose Thévenin resistance is Rs, is applied through a
coupling capacitor, Cc, to the amplifier whose bias circuit has been designed in Problem #02.
The resultant output signal response is extracted as vo, as is depicted in Fig. (P4).
(a). What purpose is served by the coupling capacitor, Cc?
(b). Use the parametric results obtained in Problem #02b to derive an expression for the driving point input resistance, Rin. For simplicity, ignore all Early resistances.
(c). Select capacitance Cc so that it emulates an AC short circuit for signal frequencies above
50 MHz.
(d). Calculate the small signal voltage gain, vo/vs, for frequencies above 50 MHz but below
those signal frequencies for which the device capacitances become critically important.
Once again, ignore transistor Early resistances. Compare this computed result with appropriate small signal SPICE simulations.
VCC
RCC
R1
Rs
vo
Cc
Q1

Q2
vs

Rin
R2
RE
Fig. (P4)
Homework #01
4
Fall Semester, 2001
EE 448
University of Southern California
J. Choma, Jr.
U niversity of S outhern C alifornia
School Of Engineering
Department Of Electrical Engineering
EE 448:
Homework Assignment #01
(SOLUTIONS: Due 09/10/2001)
Fall, 2001
Choma
Problem #01:
Homework #01
5
Fall Semester, 2001