U niversity of S outhern C alifornia
School Of Engineering
Department Of Electrical Engineering
EE 348:
Midterm Examination #2
(Open Notes, Book, Homework)
March 22, 2001
11:00 –to–12:20
(35%)
Problem #1:
In the biasing circuit of Fig. (E1), all transistors are identical, except for possible differences in base-emitter junction areas. The base-emitter junction area of transistor Q2
is larger than that of Q1 by a factor of K, while the junction area ratio of Q3 -to- Q4 is two (2).
All four transistors have sufficiently large “DC” beta, hFE, to enable the tacit neglect of all
device base currents. The circuit is designed to ensure that all transistors conduct identical collector current densities.
+VCC
RL1
RL2
IC1
IC2
Q1
Q2
R1
Q3
Q4
R2
REE
 VEE
Figure (E1)
(a). Derive, in terms of power supply voltages, VBE, and appropriate circuit resistances, a
generalized expression for the current, IC2, conducted by transistor Q2.
(b). What is the relationship between resistance R2 and resistance REE?
(c). Give an expression for the maximum permissible value of resistance RL2 commensurate
with ensuring that transistor Q2 operates as a nominally linear device.
(d). What might be the engineering rationale for choosing Q3 twice larger, in the sense of baseemitter junction injection area, than Q4?
EE 348
University of Southern California
J. Choma, Jr.
(40%)
Problem #2:
The schematic diagram provided in Fig. (E2) is that of a modified voltage
buffer known as a Darlington configuration. Both transistors are identical and are biased at
identical collector currents; hence, both devices have identical small signal model parameters.
For simplicity, assume each transistor has an internal emitter resistance (re) of zero, an internal
collector resistance (rc) of zero, and an infinitely large forward Early resistance (ro).
 VCC
Rin
Q1
Rs

Q2
R
Rout
Vo
Vs

RL
 VEE
Figure (E2)
(a). Use the small signal model of the amplifier to show that the ratio of the small signal base
current, say Ib2s, flowing in transistor Q2 -to- the small signal current, Ib1s, conducted by
the base of transistor Q1 is given by
Ib2s
  ac  1 R

K.
Ib1s
rb  r  R
(b). In terms of the introduced parametric definition, K, and circuit and model resistances,
derive an expression for the small signal voltage gain, Vos/Vs.
(c). In terms of K, and circuit and model resistances, derive an expression for the small signal
input resistance, Rin, seen by the source circuit.
(d). Through careful examination of the voltage gain expression deduced in (b), deduce an
expression for the indicated small signal output resistance, Rout.
(e). For the case of large AC beta (ac), does the amplifier at hand behave as a reasonable
approximation of a voltage buffer? Explain why or why not.
(25%)
Problem #3:
Return to the circuit of Fig. (E2) and recall that both transistors are identical
and are biased at identical collector currents. Assume that under quiescent operating conditions,
the “DC” voltage developed at the base of transistor Q1 is zero volts and that the base emitter
biasing voltage of each transistor is VBEQ. Furthermore, assume that the static base currents conducted by both transistors are negligibly small.
Examination #2
2
Spring Semester, 2001
EE 348
University of Southern California
J. Choma, Jr.
(a). In terms of VBEQ and appropriate circuit resistances and power supply voltages, give an
expression for the quiescent collector current conducted by transistor Q2.
(b). How must resistor R be chosen to ensure that each transistor conducts the same quiescent
collector current?
(c). What is the “DC” output voltage, VOQ?
(d). What collector-emitter breakdown voltage must both transistors possess (remember–both
transistors are identical) if breakdown is to be precluded under quiescent operating conditions?
(e). What fundamental biasing purpose is served by resistor R?
(f). Assume that parasitic capacitances appear between ground and the base node of Q1, the
collector node of Q2, and the emitter node of Q3. Assuming a large source resistance, Rs,
which of these three capacitors most significantly limit the high frequency response of the
circuit? Briefly rationalize your choice.
Examination #2
3
Spring Semester, 2001
EE 348
University of Southern California
J. Choma, Jr.
U niversity of S outhern C alifornia
School Of Engineering
Department Of Electrical Engineering
EE 348:
Midterm Examination #2
(Solutions)
March 22, 2001
11:00 –to–12:20
Problem #1:
+VCC
RL1
RL2
IC1
IC2
Q1
Q2
R1
Q3
Q4
R2
REE
 VEE
Examination #2
4
Spring Semester, 2001