ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 5, 2010 Memory Overview 1 Penn ESE370 Fall2010 -- DeHon Today • Memory – Motivation – Organization – Basic components – Optimization concerns 2 Penn ESE370 Fall2010 -- DeHon Know how to store state 3 Penn ESE370 Fall2010 -- DeHon Register Storage • Could just put together a large number of registers 4 Penn ESE370 Fall2010 -- DeHon Concerns? • Large number of wires – Could determine area • Not able to update all on every cycle • Not able to use all on every cycle • May want to store for many cycles 5 Penn ESE370 Fall2010 -- DeHon Limited Data Use • What if can only use one on each cycle? – Use with shared data path • Need to select the one output – Can only update one • Need to control which one gets written 6 Penn ESE370 Fall2010 -- DeHon Limited Data Use • Add load enable to register • Logic to enable one on write • Mux to select output 7 Penn ESE370 Fall2010 -- DeHon Good Solution? • Could get away with just latch – Not full register with master/slave latch • Pay large amount for decode and mux – Proportional to memory bits Penn ESE370 Fall2010 -- DeHon 8 Memory Idea • Maximize storage density (bits/cm2) • By minimizing the size/complexity of the repeated element • Use shared periphery circuits to provide full functionality • Trades off bandwidth (concurrent access) to save area 9 Penn ESE370 Fall2010 -- DeHon Memory Bank 10 Penn ESE370 Fall2010 -- DeHon Share Address Decode • Words – group of bits read/written together – All have same control 11 Penn ESE370 Fall2010 -- DeHon Share Address Decode • Words • Mux select bits (words) from row read 12 Penn ESE370 Fall2010 -- DeHon Share Address Decode • Result: only spend N0.5 area (perimeter) on selecting rather than linear in bits 13 Penn ESE370 Fall2010 -- DeHon Memory Row • Use shared enable for wire economy – Word line 14 Penn ESE370 Fall2010 -- DeHon Memory Column • Use shared bus for area and wire economy – Row enable selects the cells to read/write from bus 15 Penn ESE370 Fall2010 -- DeHon Memory Cell • Hold data • Conditionally drive onto output bus • Conditionally overwritten with data from bus 16 Penn ESE370 Fall2010 -- DeHon SRAM Memory bit 17 Penn ESE534 Spring2010 -- DeHon SRAM Memory bit • Core is back-to-back inverters for storage – Like static latch 18 Penn ESE534 Spring2010 -- DeHon SRAM Memory bit • Core is back-to-back inverters for storage – Like static latch – Doesn’t include disable to minimize size 19 Penn ESE534 Spring2010 -- DeHon SRAM Memory bit • Pass gate mux for output to column – Bit-Line (BL) 20 Penn ESE534 Spring2010 -- DeHon SRAM Memory bit • How do we write into this cell? – No directionality to pass gate – If drive BL strong enough, can flip value in selected cell • Ratioed operation 21 Penn ESE534 Spring2010 -- DeHon Column Capacitance • What is capacitance of bit line (column)? – Waccess (M5,M6) – transistor width of column device – d rows g=Cdiff/Cgate 22 Penn ESE370 Fall2010 -- DeHon Time Driving Bit Line • In terms of Waccess, Wbuf (M1,M3), d • For Waccess=Wbuf=4, d=1024, g=0.5 23 Penn ESE370 Fall2010 -- DeHon Column Capacitance Consequence • Want Waccess, Wbuf small to keep memory cell small • Increasing Waccess, also increases Cbl – Don’t really win by sizing up • Driving bit line will be slow 24 Penn ESE370 Fall2010 -- DeHon Column Sensing • Speedup read time by sensing limited swing • Sense circuit detects small change in bit line voltage(s) – Precharge to intermediate voltage – BL and /BL swing opposite directions • Amplifies for output 25 Penn ESE370 Fall2010 -- DeHon Output Amps • Bottom of array includes Sense Amplifiers from bit lines to output 26 Penn ESE370 Fall2010 -- DeHon Column Write • Writes driven from outside array • Use large driver – Strong enough to flip memory bit – Strong so can charge column quickly • Disable when not write – Be careful on your project2 – Could overwrite wrong row 27 Penn ESE370 Fall2010 -- DeHon Complete Memory Bank 28 Penn ESE370 Fall2010 -- DeHon Admin • Project 2 out – Due November 17 • Note recommend milestones • Time change this weekend (Sunday 2am) – Extra hour to work on project? • Next week normal – Lectures MWF – Office hours 29 Penn ESE370 Fall2010 -- DeHon Idea • Memory for compact state storage • Share circuitry across many bits – Minimize area per bit maximize density • Aggressively use: – Pass transistors, Ratioing – Precharge, Amplifiers to keep area down 30 Penn ESE370 Fall2010 -- DeHon