# ESE370: Circuit-Level for Digital Systems Last week + today

```ESE370:
Circuit-Level
Last week + today
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Modeling, Design, and Optimization
for Digital Systems
Day 36: December 6, 2010
Transmission Lines
Penn ESE370 Fall2010 -- DeHon
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General wire formulation
Lossless Transmission Line
Reflections at ends of line
See in action in lab
Where arise?
Termination
Implications
Discuss Lossy
Penn ESE370 Fall2010 -- DeHon
Transmission Lines
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Transmission Lines
•  This is what wires/cables look like
•  Need to understand
–  Aren’t an ideal equipotential
–  Signals do take time to propagate
–  Shape and topology of wiring effects how
signals propagate
–  How to model  how to reason about
–  What can cause noise
–  How to engineer high performance
communication
•  …and the noise effects they see
Penn ESE370 Fall2010 -- DeHon
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Transmission Lines
Coaxial Cable
•  Inner core conductor: radius r
•  Insulator: out to radius R
•  Outer core shield (ground)
•  Cable: coaxial
•  PCB
–  Strip line
–  Microstrip line
⎛ &micro; ⎞ ⎛ R ⎞
L = ⎜ ⎟ ln⎜ ⎟
⎝ 2π ⎠ ⎝ r ⎠
•  Twisted Pair (Cat5)
Penn ESE370 Fall2010 -- DeHon
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Penn ESE370 Fall2010 -- DeHon
⎛ 1 ⎞⎛ &micro; ⎞ ⎛ R ⎞
Z 0 = ⎜ ⎟⎜
⎟ ln⎜ ⎟
⎝ 2π ⎠⎝ ε ⎠ ⎝ r ⎠
•  RG-58 Z0= 50Ω – networking, lab
•  (RG-59 Z0= 75Ω – video)
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Penn ESE370 Fall2010 -- DeHon
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Printed Circuit Board
Printed Circuit Board
•  Stripline
•  Microstrip line
–  Trace between planes
–  Trace over single supply plane
w
t
b
ε0
εr
εr
⎛ 1 ⎞⎛ &micro; ⎞ ⎛ 1+ W b ⎞
⎟
Z 0 = ⎜ ⎟⎜
⎟ ln⎜
⎝ 4 ⎠⎝ ε ⎠ ⎜⎝ t + W ⎟⎠
b
b
⎛ 1 ⎞⎛
Z 0 = ⎜ ⎟⎜⎜
⎝ 2π ⎠⎝
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Penn ESE370 Fall2010 -- DeHon
w
t
h
⎞ ⎛
⎞
&micro;
4h
⎟ ln⎜
⎟
⎟
(0.475ε r + 0.67)ε 0 ⎠ ⎝ 0.536W + 0.67t ⎠
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Penn ESE370 Fall2010 -- DeHon
€
€
Twisted Pair
Termination / Mismatch
•  Category 5 ethernet cable
•  Wires do look like these transmission lines
•  We are terminating them in some way
when we connect to gate
–  100Ω
–  V=0.64c0
–  Need to be deliberate about how terminate,
if we care about high performance
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Penn ESE370 Fall2010 -- DeHon
Where Mismatch?
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Vias
Wire corners?
Connectors
Board-to-cable
Cable-to-cable
Visualization
•  http://www.williamson-labs.com/xmission.htm
http://www.fpga4fun.com/Hands-on_Flashy.html
Penn ESE370 Fall2010 -- DeHon
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Penn ESE370 Fall2010 -- DeHon
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Penn ESE370 Fall2010 -- DeHon
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2
End of Line Reflection
Termination Cases
⎛ R − Z 0 ⎞
Vr = Vi ⎜
⎟
⎝ R + Z 0 ⎠
•  Parallel at Sink
–  Pix
•  Series at Source
€
⎛ 2R ⎞
Vt = Vi ⎜
⎟
⎝ R + Z 0 ⎠
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Penn ESE370 Fall2010 -- DeHon
–  pix
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Penn ESE370 Fall2010 -- DeHon
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Pipeline Bits
Limits to Bit Pipelining
•  For properly terminated transmission line
–  Do not need to wait for bits to arrive at sink
–  Can stick new bits onto wire
•  What limits?
–  Risetime/distortion
–  Clocking
•  Skew
•  Jitter
–  For bus
•  Wire length differences between lines
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Penn ESE370 Fall2010 -- DeHon
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Penn ESE370 Fall2010 -- DeHon
Eye Diagrams
•  Watch bits over line on scope
–  Look at distortion
–  “open” eye clean place to sample
•  Consistent timing of transitions
•  Well defined high/low voltage levels
http://en.wikipedia.org/wiki/File:On-off_keying_eye_diagram.svg
Penn ESE370 Fall2010 -- DeHon
http://focus.ti.com/analog/docs/gencontent.tsp?familyId=361&amp;genContentId=41762&amp;DCMP=ESD_Solutions&amp;HQS=Other+OT+esd
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http://archive.chipcenter.com/knowledge_centers/asic/todays_feature/showArticle.jhtml?articleID=12800254
Penn ESE370 Fall2010 -- DeHon
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3
Impedance Change
Z0=75, Z1=50
•  What happens if there is an impedance
change in the wire?
•  At junction:
–  Reflects
•  Vr=(50-75)/(50+75)Vi
–  Transmits
•  Vt=(100/(50+75))Vi
⎛ R − Z 0 ⎞
Vi ⎜
⎟ = Vr
⎝ R + Z 0 ⎠
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Penn ESE370 Fall2010 -- DeHon
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Penn ESE370 Fall2010 -- DeHon
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Impedance Change
Z0=75, Z1=50
€
What happens at branch?
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Penn ESE370 Fall2010 -- DeHon
⎛ 2R ⎞
Vi ⎜
⎟ = Vt
⎝ R + Z 0 ⎠
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Penn ESE370 Fall2010 -- DeHon
Branch
Z0=50, Z1=25
•  Transmission line sees two Z0 in parallel
•  At junction:
–  Looks like Z0/2
–  Reflects
•  Vr=(25-50)/(25+50)Vi
–  Transmits
•  Vt=(50/(25+50))Vi
⎛ R − Z 0 ⎞
Vi ⎜
⎟ = Vr
⎝ R + Z 0 ⎠
Penn ESE370 Fall2010 -- DeHon
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Penn ESE370 Fall2010 -- DeHon
€
⎛ 2R ⎞
Vi ⎜
⎟ = Vt
⎝ R + Z 0 ⎠
€
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End of Branch
Branch Simulation
•  What happens at end?
•  If ends in matched, parallel termination
–  No further reflections
Penn ESE370 Fall2010 -- DeHon
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Branch with Open Circuit?
Penn ESE370 Fall2010 -- DeHon
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Branch with Open Circuit
•  What happens if branch open circuit?
•  Reflects at end of open-circuit stub
•  Reflection returns to branch
–  …and encounters branch again
–  Send transmission pulse to both
•  Source and other branch
•  Sink sees original pulse as multiple
smaller pulses spread out over time
Penn ESE370 Fall2010 -- DeHon
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Open Branch Simulation
Penn ESE370 Fall2010 -- DeHon
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Open Branch Simulation
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Penn ESE370 Fall2010 -- DeHon
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Penn ESE370 Fall2010 -- DeHon
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Bus
Multi-drop Bus
•  Common to have many modules on a bus
–  E.g. PCI slots
–  DIM slots for memory
•  Ideal
•  High speed  bus lines are trans. lines
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Penn ESE370 Fall2010 -- DeHon
Multi-Drop Bus
Multi-Drop Bus
•  Capacitive load (stub) at drop?
•  Long wire stub?
–  If tight/regular enough, change Z of line
Z0 =
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Penn ESE370 Fall2010 -- DeHon
–  Looks like branch
•  may produce reflections
L
C
€
Penn ESE370 Fall2010 -- DeHon
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Lossy Transmission Line
Penn ESE370 Fall2010 -- DeHon
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Lossy Transmission Line
•  How do addition of R’s change?
•  R’s cause signal attenuation (loss)
–  Voltage, energy
–  Reduced signal swing at sink
–  Limits length of transmission line before
need to restore signal
Penn ESE370 Fall2010 -- DeHon
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Penn ESE370 Fall2010 -- DeHon
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6
Transmission Line Noise
•  Frequency limits
•  Imperfect termination
•  Mismatched segments/junctions/vias/
connectors
•  Loss due to resistance in line
•  Proj3b due Friday
–  Limits length
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Penn ESE370 Fall2010 -- DeHon
Penn ESE370 Fall2010 -- DeHon
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Idea
•  Transmission lines
–  high-speed
–  high throughput
–  long-distance signaling
•  Termination
•  Signal quality
Penn ESE370 Fall2010 -- DeHon
1
c0
=
LC
ε r &micro;r
L
Z0 =
C
w=
€
⎛ R − Z 0 ⎞
Vr = Vi ⎜
⎟
€ ⎝ R + Z 0 ⎠
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€
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