CISC 3360 Final Examination
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02 July 2015
Name_________________________________
What are the four major components of any general-purpose computer?
Explain Moore's law.
What is a CISC processor?
What is a RISC processor?
Describe the Basic Pipeline Scheduling process and give an example.
Describe Loop Unrolling and give an example.
Describe and explain the five steps in instruction execution.
Explain the four limitations on ILP for realizable processors.
Work the Pseudo-Assembly Language problem attached to this document.
Explain why our authors consider the following programming practices to be “pitfalls:”
a. Ignoring memory system behavior when writing pragmas or when generating code in a
compiler.
b. Forgetting to account for byte addressing or the cache block size in simulating a cache.
c. Having less set associativity for a shared cache than the number of cores or threads
sharing that cache.
d. Using average memory access time to evaluate the memory hierarchy of an out-oforder processor.
For a direct-mapped cache design with a 32-bit address, the following bits of the address
are used to access the cache.
Tag
31-10
Index
9-5
Offset
4-0
What is the cache block size (in words)?
How many entries does the cache have?
What is the ratio between total bits required for such a cache implementation over the data
storage bits?
Starting from power on, the following byte-addressed cache references are recorded.
0 4
16
132
232
160
Address
1024
30
140
3100
180
2180
How many blocks are required?
What is the hit ratio?
List the final state of the cache, with each valid entry represented as a record of <index, tag, data>.
12.
In this exercise, we will look at the different ways capacity affects overall performance. In
general, cache access time is proportional to capacity. Assume that main memory accesses
take 70 ns and that memory accesses are 36% of all instructions. The following table shows
data for L1 caches attached to each of two processors, P1 and P2.
P1
P2
L1
Size
2 KiB
4 KiB
L1 Miss
Rate
8.00%
6.00%
L1 Hit
Time
0.66 ns
0.90 ns
Assuming that L1 hit time determines the cycle times for P1 and P2, what are their respective
clock rates?
What is the Average Memory Access Time for P1 and P2?
Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 and P2?
Which processor is faster?
CISC 3360 Final Examination
02 July 2015
Name_________________________________
1=MOVE M(X), AC; 2=STORE AC, M(X); 3=ADD M(X), AC; 4=SUB M(X), AC.
FETCH
EXECUTE
Gen.MEMORY
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Inst.MEMORY
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Gen.MEMORY
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Gen.MEMORY
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Gen.MEMORY
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Gen.MEMORY
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Inst.MEMORY
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1750
3751
4752
2754
3753
2755
STEP 11
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CPU
REGISTERS
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CPU
REGISTERS
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Gen.MEMORY
PC
AC
IR
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CPU
REGISTERS
000A
0003
0009
0008
Gen.MEMORY
PC
AC
IR
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CPU
REGISTERS
000A
0003
0009
0008
Gen.MEMORY
PC
AC
IR
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0003
0009
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CPU
REGISTERS
PC
AC
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CPU
REGISTERS
PC
AC
IR
CPU
REGISTERS
1750
3751
4752
2754
3753
2755
STEP 10
Inst.MEMORY
500
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PC
AC
IR
1750
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4752
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STEP 8
Inst.MEMORY
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CPU
REGISTERS
1750
3751
4752
2754
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STEP 6
Inst.MEMORY
500
501
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PC
AC
IR
1750
3751
4752
2754
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STEP 4
Inst.MEMORY
500
501
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CPU
REGISTERS
1750
3751
4752
2754
3753
2755
STEP 2
Inst.MEMORY
Gen.MEMORY
PC
AC
IR
1750
3751
4752
2754
3753
2755
STEP 9
000A
0003
0009
0008
Inst.MEMORY
Gen.MEMORY
PC
AC
IR
1750
3751
4752
2754
3753
2755
STEP 7
Inst.MEMORY
750
751
752
753
754
755
CPU
REGISTERS
1750
3751
4752
2754
3753
2755
STEP 5
Inst.MEMORY
Gen.MEMORY
PC
AC
IR
1750
3751
4752
2754
3753
2755
STEP 3
Inst.MEMORY
Gen.MEMORY
750
751
752
753
754
755
1750
3751
4752
2754
3753
2755
STEP 1
Inst.MEMORY
500
501
502
503
504
505
CPU
REGISTERS
1750
3751
4752
2754
3753
2755
STEP 12
PC
AC
IR
CPU
REGISTERS
PC
AC
IR