ELEC 5200
CPU DESIGN PROJECT REPORT
FALL 2012
Timothy McCall
Seth Beech
Kentereian Thomas
What did you learn from this project?
Designing and implementing a CPU has been a great learning experience in this course, before starting
project we had basic knowledge of the VHDL language, but the project helped us to learn the language
a little better. We worked on the tools like ModelSim, Quartus and used Altera FPGA Boards starting
from part 3 of the project although the FPGA board was used only for implementing our CPU design in
part 5. We now understand the different steps involved in designing a multi-cycle datapath. In the final
step of the project, we learned how to simulate our processor on the Altera FPGA board provided in the
lab.
What would you do differently next time?
We would start trying to implement the design earlier than we did. By starting earlier we could have
been able to fix problems we had when trying to put the design on the board. We were not able to get
our design on the board for demonstration.
What is your advice to someone who is going to work on a similar project?
We would encourage you to start implementing the design as soon as possible. We ran out of time
trying to get our design on the board and ended up not being able to demo our design.
Over the course of this semester we were asked to design and implement in VHDL a RISC CPU. The
project forced us to face the many challenges that go along with designing a cpu, forcing us to solve
issues such as synchronization and workflow between the many components of the datapath as well as
many other issues.
In part five of our project we were asked to program a FPGA in order to see our CPU working on
hardware. This proved to be more problematic that we had originally expected and leaving our group
unable to complete this last stage of our project. We were unable to simulate our design and couldn't
verify it's proper function. We attempted to follow the guide posted online (Altera Quartus II and DE2
Manual) that details the steps needed to create and simulate a VHDL model using Quartus 2 however
we were not successful in doing so. Below are several screenshots that show some of the options that
we chose when making our project.
Project Device Settings
Simulation Tools
After creating our project we added our VHDL model files and were able to successfully complile our
source.
Quartus Compilation Results
The full results of this compilation can be seen at the end of this report.
After compiling this model we attempted to simulate using ModelSim but were unable to do so because
of an error that would occur as we attempted to simulate our model. This error was caused because
Quartus was unable to find the executable that ran ModelSim. We attempted to resolve this error but
were unable to do so and as a result were unable to simulate the model.
Quartus Error
We were asked to answer a few questions about this project the first of which being: “What did
you learn from this project?” As was mentioned earlier, this project forced us to face the many aspects
of CPU design. One of the most interesting thing that we learned was how many of the CPU's
instructions were implemented in hardware. For instance, how the Control Unit and ALU work together
in order to take the binary machine language and perform complicated R-Type instructions.
The second question we were asked in regard to our project was “What would you do
differently next time?” In response to that question, I would say devote more time to the final stage of
the project. We were rather optimistic in our time budget for the final stage for this project, and as a
result we were not able to complete the final assignment. If given another chance I would have spent
more time on attempting to implement our design on hardware. Because of the fact that we didn't
devote adequate time to our implementation when we were faced with the issues that arose when trying
to program the hardware we were unable to complete the project.
As to the final question “What is your advice to someone who is going to work on a similar
project” I would reiterate on the changes I would make if I did it again. As was previously discussed
unforeseen problems caused us to not have adequate time to complete our project, and if I were to give
advice to someone who was going to work on a similar project I would say that they should expect
issues to arise and plain to budget your time accordingly. If our group had done that small issues such
as working with Quartus wouldn't have left us dead in the water and we would have been able to work
past such adversity.
Compilation Results:
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
Info: Processing started: Sun Nov 25 23:33:26 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off datapath -c datapath
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Found 2 design units, including 1 entities, in source file cu.vhd
Info: Found design unit 1: CU-CONTROL
Info: Found entity 1: CU
Info: Found design unit 1: CU-CONTROL
Info: Found entity 1: CU
Info: Found 2 design units, including 1 entities, in source file reg.vhd
Info: Found design unit 1: reg-reg1
Info: Found entity 1: reg
Info: Found design unit 1: reg-reg1
Info: Found entity 1: reg
Info: Found 2 design units, including 1 entities, in source file 3x1mux.vhd
Info: Found design unit 1: mux1-multiplexer
Info: Found entity 1: mux1
Info: Found design unit 1: mux1-multiplexer
Info: Found entity 1: mux1
Warning: Entity "mux" obtained from "2x1MUX4.vhd" instead of from Quartus II megafunction library
Info: Found 2 design units, including 1 entities, in source file 2x1mux4.vhd
Info: Found design unit 1: mux-multiplexer
Info: Found entity 1: mux
Info: Found design unit 1: mux-multiplexer
Info: Found entity 1: mux
Info: Found 2 design units, including 1 entities, in source file mux3.vhd
Info: Found design unit 1: mux3-multiplexer
Info: Found entity 1: mux3
Info: Found design unit 1: mux3-multiplexer
Info: Found entity 1: mux3
Info: Found 2 design units, including 1 entities, in source file regfile.vhd
Info: Found design unit 1: regfile-rtl
Info: Found entity 1: regfile
Info: Found design unit 1: regfile-rtl
Info: Found entity 1: regfile
Info: Found 2 design units, including 1 entities, in source file datapath.vhd
Info: Found design unit 1: datapath-datpat
Info: Found entity 1: datapath
Info: Found design unit 1: datapath-datpat
Info: Found entity 1: datapath
Info: Found 2 design units, including 1 entities, in source file pc.vhd
Info: Found design unit 1: pc-reg
Info: Found entity 1: pc
Info: Found design unit 1: pc-reg
Info: Found entity 1: pc
Info: Found 2 design units, including 1 entities, in source file alu.vhd
Info: Found design unit 1: alu-ALU
Info: Found entity 1: alu
Info: Found design unit 1: alu-ALU
Info: Found entity 1: alu
Info: Found 2 design units, including 1 entities, in source file sr.vhd
Info: Found design unit 1: shift-shifter
Info: Found entity 1: shift
Info: Found design unit 1: shift-shifter
Info: Found entity 1: shift
Info: Found 2 design units, including 1 entities, in source file 2x1mux.vhd
Info: Found design unit 1: mux2-multiplexer
Info: Found entity 1: mux2
Info: Found design unit 1: mux2-multiplexer
Info: Found entity 1: mux2
Info: Found 2 design units, including 1 entities, in source file mem.vhd
Info: Found design unit 1: mem-SYN
Info: Found entity 1: mem
Info: Found design unit 1: mem-SYN
Info: Found entity 1: mem
Info: Found 2 design units, including 1 entities, in source file mux4.vhd
Info: Found design unit 1: mux4-multiplexer
Info: Found entity 1: mux4
Info: Found design unit 1: mux4-multiplexer
Info: Found entity 1: mux4
Info: Elaborating entity "datapath" for the top level hierarchy
Info: Elaborating entity "CU" for hierarchy "CU:Control"
Warning (10492): VHDL Process Statement warning at cu.vhd(61): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(63): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(65): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(103): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(105): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(107): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(109): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(111): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(113): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(115): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(138): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(140): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(153): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(156): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(172): signal "ALUflag" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(226): signal "opcode" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at cu.vhd(227): signal "ALUflag" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "PCclr", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "PCen", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "IRclr", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "IRen", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "MDclr", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "RegWren", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "Aclr", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "Bclr", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "ALUoutclr", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "ALUop", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "memWriteEn", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "regfileDataSelect", which
holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "regfileRegSelectSelect",
which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "AinSelect", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "BinSelect", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "PCinSelect", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at cu.vhd(30): inferring latch(es) for signal or variable "memaddrSelect", which holds
its previous value in one or more paths through the process
Info (10041): Inferred latch for "memaddrSelect" at cu.vhd(30)
Info (10041): Inferred latch for "PCinSelect[0]" at cu.vhd(30)
Info (10041): Inferred latch for "PCinSelect[1]" at cu.vhd(30)
Info (10041): Inferred latch for "BinSelect" at cu.vhd(30)
Info (10041): Inferred latch for "AinSelect" at cu.vhd(30)
Info (10041): Inferred latch for "regfileRegSelectSelect[0]" at cu.vhd(30)
Info (10041): Inferred latch for "regfileRegSelectSelect[1]" at cu.vhd(30)
Info (10041): Inferred latch for "regfileDataSelect[0]" at cu.vhd(30)
Info (10041): Inferred latch for "regfileDataSelect[1]" at cu.vhd(30)
Info (10041): Inferred latch for "regfileDataSelect[2]" at cu.vhd(30)
Info (10041): Inferred latch for "memWriteEn" at cu.vhd(30)
Info (10041): Inferred latch for "ALUop[0]" at cu.vhd(30)
Info (10041): Inferred latch for "ALUop[1]" at cu.vhd(30)
Info (10041): Inferred latch for "ALUop[2]" at cu.vhd(30)
Info (10041): Inferred latch for "ALUop[3]" at cu.vhd(30)
Info (10041): Inferred latch for "ALUoutclr" at cu.vhd(30)
Info (10041): Inferred latch for "Bclr" at cu.vhd(30)
Info (10041): Inferred latch for "Aclr" at cu.vhd(30)
Info (10041): Inferred latch for "RegWren" at cu.vhd(30)
Info (10041): Inferred latch for "MDclr" at cu.vhd(30)
Info (10041): Inferred latch for "IRen" at cu.vhd(30)
Info (10041): Inferred latch for "IRclr" at cu.vhd(30)
Info (10041): Inferred latch for "PCen" at cu.vhd(30)
Info (10041): Inferred latch for "PCclr" at cu.vhd(30)
Info: Elaborating entity "pc" for hierarchy "pc:PCount"
Warning (10492): VHDL Process Statement warning at PC.vhd(16): signal "b" is read inside the Process Statement but isn't in the Process
Statement's sensitivity list
Info: Elaborating entity "reg" for hierarchy "reg:MemData"
Info: Elaborating entity "regfile" for hierarchy "regfile:registerFile"
Info: Elaborating entity "alu" for hierarchy "alu:ALUnit"
Warning (10631): VHDL Process Statement warning at ALU.vhd(16): inferring latch(es) for signal or variable "ALUout", which holds its
previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at ALU.vhd(16): inferring latch(es) for signal or variable "z", which holds its previous
value in one or more paths through the process
Info (10041): Inferred latch for "z" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[0]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[1]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[2]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[3]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[4]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[5]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[6]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[7]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[8]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[9]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[10]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[11]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[12]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[13]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[14]" at ALU.vhd(16)
Info (10041): Inferred latch for "ALUout[15]" at ALU.vhd(16)
Info: Elaborating entity "mux2" for hierarchy "mux2:memaddrMUX"
Info: Elaborating entity "mux3" for hierarchy "mux3:regfileDataMUX"
Warning (10492): VHDL Process Statement warning at mux3.vhd(25): signal "d" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at mux3.vhd(27): signal "e" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at mux3.vhd(16): inferring latch(es) for signal or variable "o", which holds its
previous value in one or more paths through the process
Info (10041): Inferred latch for "o[0]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[1]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[2]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[3]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[4]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[5]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[6]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[7]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[8]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[9]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[10]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[11]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[12]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[13]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[14]" at mux3.vhd(16)
Info (10041): Inferred latch for "o[15]" at mux3.vhd(16)
Info: Elaborating entity "mux4" for hierarchy "mux4:regfileRegSelectMUX"
Warning (10492): VHDL Process Statement warning at mux4.vhd(21): signal "c" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at mux4.vhd(14): inferring latch(es) for signal or variable "o", which holds its
previous value in one or more paths through the process
Info (10041): Inferred latch for "o[0]" at mux4.vhd(14)
Info (10041): Inferred latch for "o[1]" at mux4.vhd(14)
Info (10041): Inferred latch for "o[2]" at mux4.vhd(14)
Info (10041): Inferred latch for "o[3]" at mux4.vhd(14)
Info: Elaborating entity "mux1" for hierarchy "mux1:PCinMUX"
Warning (10492): VHDL Process Statement warning at 3x1MUX.vhd(25): signal "d" is read inside the Process Statement but isn't in the
Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at 3x1MUX.vhd(16): inferring latch(es) for signal or variable "o", which holds its
previous value in one or more paths through the process
Info (10041): Inferred latch for "o[0]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[1]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[2]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[3]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[4]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[5]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[6]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[7]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[8]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[9]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[10]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[11]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[12]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[13]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[14]" at 3x1MUX.vhd(16)
Info (10041): Inferred latch for "o[15]" at 3x1MUX.vhd(16)
Info: Elaborating entity "shift" for hierarchy "shift:shifter"
Warning: LATCH primitive "mux1:PCinMUX|o[0]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[1]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[2]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[3]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[4]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[5]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[6]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[7]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[8]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[9]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[10]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[11]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[12]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[13]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[14]" is permanently enabled
Warning: LATCH primitive "mux1:PCinMUX|o[15]" is permanently enabled
Warning: Latch CU:Control|memaddrSelect has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch mux4:regfileRegSelectMUX|o[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileRegSelectSelect[1]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileRegSelectSelect[1]
Warning: Latch mux4:regfileRegSelectMUX|o[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileRegSelectSelect[1]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileRegSelectSelect[1]
Warning: Latch mux4:regfileRegSelectMUX|o[3] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileRegSelectSelect[1]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileRegSelectSelect[1]
Warning: Latch mux4:regfileRegSelectMUX|o[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileRegSelectSelect[1]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileRegSelectSelect[1]
Warning: Latch alu:ALUnit|ALUout[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch CU:Control|PCinSelect[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch CU:Control|PCinSelect[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and PRE on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and PRE on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch CU:Control|PCen has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and PRE on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and PRE on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch alu:ALUnit|ALUout[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[3] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[4] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[5] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[6] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[7] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[8] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[9] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[10] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[11] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[12] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[13] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[14] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch alu:ALUnit|ALUout[15] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[2]
Warning: Latch mux3:regfileDataMUX|o[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch CU:Control|RegWren has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and PRE on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and PRE on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch mux3:regfileDataMUX|o[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[3] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[4] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[5] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[6] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[7] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[8] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[9] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[10] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[11] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[12] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[13] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[14] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch mux3:regfileDataMUX|o[15] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|regfileDataSelect[2]
Warning: Latch CU:Control|ALUop[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch CU:Control|ALUop[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal pc:InstReg|b[12]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal pc:InstReg|b[12]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch CU:Control|ALUop[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal pc:InstReg|b[12]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal pc:InstReg|b[12]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch alu:ALUnit|z has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[0]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|ALUop[0]
Warning: Latch CU:Control|regfileDataSelect[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch CU:Control|regfileDataSelect[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Latch CU:Control|regfileDataSelect[0] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports D and ENA on the latch are fed by the same signal CU:Control|state[3]
Warning: Ports ENA and CLR on the latch are fed by the same signal CU:Control|state[3]
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "writeEn" is stuck at GND
Warning (13410): Pin "writeEn" is stuck at GND
Info: Generating hard_block partition "hard_block:auto_generated_inst"
Info: Implemented 1221 device resources after synthesis - the final resource count might be different
Info: Implemented 17 input pins
Info: Implemented 33 output pins
Info: Implemented 1171 logic cells
Info: Implemented 17 input pins
Info: Implemented 33 output pins
Info: Implemented 1171 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 169 warnings
Info: Peak virtual memory: 305 megabytes
Info: Processing ended: Sun Nov 25 23:33:42 2012
Info: Elapsed time: 00:00:16
Info: Total CPU time (on all processors): 00:00:07
Info: Peak virtual memory: 305 megabytes
Info: Processing ended: Sun Nov 25 23:33:42 2012
Info: Elapsed time: 00:00:16
Info: Total CPU time (on all processors): 00:00:07
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
Info: Processing started: Sun Nov 25 23:33:43 2012
Info: Version 11.0 Build 157 04/27/2011 SJ Full Version
Info: Processing started: Sun Nov 25 23:33:43 2012
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off datapath -c datapath
Info: Parallel compilation is enabled and will use 4 of the 4 processors detected
Info: Selected device EP2C35F672C6 for design "datapath"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Sorce Code:
2x1 Mux
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity mux2 is
port( a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
s:
in std_logic;
o: out std_logic_vector(15 downto 0));
end mux2;
architecture multiplexer of mux2 is
begin
process(a, b, S)
begin
if(S = '1') then
o <= a;
else
o <= b;
end if;
end process;
end architecture multiplexer;
2x1 mux 4
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity mux is
port( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
s:
in std_logic;
o: out std_logic_vector(3 downto 0));
end mux;
architecture multiplexer of mux is
begin
process(a, b, S)
begin
if(S = '1') then
o <= a;
else
o <= b;
end if;
end process;
end architecture multiplexer;
3x1mux.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity mux1 is
port( a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
c: in std_logic_vector(15 downto 0);
d: in std_logic_vector(15 downto 0);
s: in std_logic_vector(1 downto 0);
o: out std_logic_vector(15 downto 0));
end mux1;
architecture multiplexer of mux1 is
begin
process(a, b, c, S)
begin
if(S = "00") then
o <= a;
elsif(S = "01") then
o <= b;
elsif(S = "10") then
o <= c;
elsif(S = "11") then
o <= d;
end if;
end process;
end architecture multiplexer;
ALU.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity alu is
port(
a :in std_logic_vector(15 downto 0);
b
:in std_logic_vector(15 downto 0);
s
:in std_logic_vector(3 downto 0);
z : out std_logic;
ALUout
:out std_logic_vector(15 downto 0));
end alu;
architecture ALU of alu is
begin
process(a, b, s)
begin
case s is
when "0000" =>
ALUout <= a+b;
when "0001" =>
ALUout <= a-b;
when "0010" =>
ALUout <= a and b;
when "0011" =>
ALUout <= a or b;
when "0100" =>
if (a=b) then
z <= '1';
else
z <= '0';
end if;
when "0101" =>
if (a < b) then
z <= '1';
else
z <= '0';
end if;
when "0110" =>
if (a > b) then
z <= '1';
else
z <= '0';
end if;
when others =>
ALUout <= "0000000000000000";
end case;
end process;
end architecture ALU;
cu.vhd
library ieee;
use ieee.std_logic_1164.all;
entity CU is
port(PCclr: out std_logic;
PCen: out std_logic;
IRclr: out std_logic;
IRen: out std_logic;
MDclr: out std_logic;
RegWren: out std_logic;
Aclr: out std_logic;
Bclr: out std_logic;
ALUoutclr: out std_logic;
ALUop: out std_logic_vector(3 downto 0);
ALUflag: in std_logic;
memaddrSelect: out std_logic;
memWriteEn: out std_logic;
regfileDataSelect: out std_logic_vector(2 downto 0);
regfileRegSelectSelect: out std_logic_vector(1 downto 0);
AinSelect: out std_logic;
BinSelect: out std_logic;
PCinSelect: out std_logic_vector(1 downto 0);
clk: in std_logic;
opcode: in std_logic_vector(3 downto 0));
end entity CU;
architecture CONTROL of CU is
signal state: integer := 0;
begin
process(state)
begin
if (state'event) then
if (state = 1) then
--instruction fetch
PCclr <= '1';
PCen <= '0';
IRclr <= '1';
IRen <= '1';
MDclr <= '1';
RegWren <= '0';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
ALUop <= "0000";
--memaddrSelect <= '0';
memWriteEn <= '0';
regfileDataSelect <= "000";
regfileRegSelectSelect <= "00";
AinSelect <= '0';
BinSelect <= '0';
PCinSelect <= "00";
elsif (state = 2) then
--instruction decode, etc
PCclr <= '1';
PCen <= '1';
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
RegWren <= '0';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
if (opcode = "0011") then --greater than
ALUop <= "0110";
elsif (opcode = "0100") then --less than
ALUop <= "0101";
elsif (opcode = "0010") then --equal
ALUop <= "0100";
end if;
memaddrSelect <= '0';
memWriteEn <= '0';
regfileDataSelect <= "000";
regfileRegSelectSelect <= "00";
AinSelect <= '1';
BinSelect <= '1';
PCinSelect <= "01";
--try 00 if no work
elsif (state = 3) then
-PCclr <= '1';
PCen <= '0';
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
RegWren <= '0';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
ALUop <= "0000";
memaddrSelect <= '0';
memWriteEn <= '0';
regfileDataSelect <= "000";
--not sure
regfileRegSelectSelect <= "00"; --not sure
AinSelect <= '0';
BinSelect <= '0';
PCinSelect <= "00";
elsif (state = 4) then
--ALU operation
PCclr <= '1';
PCen <= '0';
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
RegWren <= '0';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
if (opcode = "0000") then
ALUop <= "0000";
elsif (opcode = "0001") then
ALUop <= "0001";
elsif (opcode = "1010") then
ALUop <= "0010";
elsif (opcode = "1011") then
ALUop <= "0011";
elsif (opcode = "0011") then
ALUop <= "0110";
elsif
elsif
elsif
elsif
elsif
elsif (opcode = "0100") then
ALUop <= "0101";
elsif (opcode = "0101") then
ALUop <= "0100";
end if;
memaddrSelect <= '0';
memWriteEn <= '0';
regfileDataSelect <= "000";
regfileRegSelectSelect <= "00";
AinSelect <= '1';
BinSelect <= '1';
PCinSelect <= "00";
(state = 5) then
--load immediate
PCclr <= '1';
PCen <= '0';
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
RegWren <= '1';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
ALUop <= "0000";
memaddrSelect <= '0';
memWriteEn <= '0';
if (opcode = "1100") then
regfileDataSelect <= "010";
elsif (opcode = "1101") then
regfileDataSelect <= "011";
end if;
regfileRegSelectSelect <= "00";
AinSelect <= '0';
BinSelect <= '0';
PCinSelect <= "00";
(state = 6) then
--write jump address to PC
PCclr <= '1';
PCen <= '1';
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
if (opcode = "0110") then
RegWren <= '1';
PCinSelect <= "10";
elsif (opcode = "0111") then
RegWren <= '0';
PCinSelect <= "11";
end if;
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
ALUop <= "0000";
memaddrSelect <= '0';
memWriteEn <= '0';
regfileDataSelect <= "100";
regfileRegSelectSelect <= "10";
AinSelect <= '0';
BinSelect <= '0';
(state = 7) then
PCclr <= '1';
PCen <= ALUflag;
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
RegWren <= '0';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
ALUop <= "0000";
memaddrSelect <= '0';
memWriteEn <= '0';
regfileDataSelect <= "000";
regfileRegSelectSelect <= "00";
AinSelect <= '0';
BinSelect <= '0';
PCinSelect <= "10";
(state = 8) then
--read memory data
PCclr <= '1';
PCen <= '0';
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
RegWren <= '0';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
ALUop <= "0000";
memaddrSelect <= '1';
memWriteEn <= '0';
regfileDataSelect <= "000";
regfileRegSelectSelect <= "00";
AinSelect <= '0';
BinSelect <= '0';
PCinSelect <= "00";
(state = 9) then
PCclr <= '1';
PCen <= '0';
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
--what do
--not sure
--what do
RegWren <= '0';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
ALUop <= "0000";
memaddrSelect <= '1';
memWriteEn <= '0';
regfileDataSelect <= "000";
regfileRegSelectSelect <= "00";
AinSelect <= '0';
BinSelect <= '0';
PCinSelect <= "00";
elsif (state = 10) then
--write register
PCclr <= '1';
if (opcode = "0011" or opcode = "0100" or opcode = "0101") then
PCen <= ALUFlag;
RegWren <= '0';
else
PCen <= '0';
RegWren <= '1';
end if;
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
RegWren <= '1';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
ALUop <= "0000";
memaddrSelect <= '0';
memWriteEn <= '0';
regfileDataSelect <= "001";
regfileRegSelectSelect <= "01";
AinSelect <= '0';
BinSelect <= '0';
PCinSelect <= "11";
elsif (state = 11) then
PCclr <= '1';
PCen <= '1';
IRclr <= '1';
IRen <= '0';
MDclr <= '1';
RegWren <= '0';
Aclr <= '1';
Bclr <= '1';
ALUOutclr <= '1';
ALUop <= "0000";
memaddrSelect <= '0';
memWriteEn <= '0';
regfileDataSelect <= "000";
regfileRegSelectSelect <= "00";
AinSelect <= '0';
BinSelect <= '0';
PCinSelect <= "00";
end if;
end if;
end process;
process(clk)
begin
if (clk'event and clk = '1') then
if (state = 0) then
state <= 1;
elsif (state = 1) then
state <= 2;
elsif (state = 3 and opcode = "1000") then
state <= 8;
elsif (state = 3 and opcode = "1001") then
state <= 9;
elsif (state = 4) then
state <= 10;
elsif (state = 6 or state = 7 or state = 9 or state = 10 or state = 5 or state = 11) then
state <= 1;
elsif (state = 8) then
state <= 11;
elsif (state = 2 and (opcode = "1000" or opcode = "1001")) then
state <= 3;
elsif (state = 2 and (opcode = "0011" or opcode = "0100" or opcode = "0101")) then
state <= 4;
elsif (state = 2 and (opcode = "0110" or opcode = "0111")) then
state <= 6;
elsif (state = 2 and (opcode = "1100" or opcode = "1101")) then
state <= 5;
elsif (state = 2 and (opcode = "0000" or opcode = "0001" or opcode = "1010" or opcode = "1011" or opcode =
"1110" or opcode = "1111")) then
state <= 4;
elsif (state = 2 and opcode = "0010") then
state <= 9999;
end if;
end if;
--end if;
end process;
end architecture CONTROL;
datapath.vhd
library ieee;
use ieee.std_logic_1164.all;
entity datapath is
port( clk: in std_logic;
memaddr: out std_logic_vector(15 downto 0);
dataout: out std_logic_vector(15 downto 0);
datain: in std_logic_vector(15 downto 0);
writeEn: out std_logic);
end entity datapath;
architecture datpat of datapath is
signal PCout: std_logic_vector(15 downto 0);
signal IRout: std_logic_vector(15 downto 0);
signal MDout: std_logic_vector(15 downto 0);
signal Ain: std_logic_vector(15 downto 0);
signal Bin: std_logic_vector(15 downto 0);
signal RegfileDin: std_logic_vector(15 downto 0);
signal RegfileRegSelect: std_logic_vector(3 downto 0);
signal Aout: std_logic_vector(15 downto 0);
signal Bout: std_logic_vector(15 downto 0);
signal ALUinA: std_logic_vector(15 downto 0);
signal ALUinB: std_logic_vector(15 downto 0);
signal ALUout: std_logic_vector(15 downto 0);
signal ALUoutRegOut: std_logic_vector(15 downto 0);
signal PCin: std_logic_vector(15 downto 0);
signal Sl2out: std_logic_vector(11 downto 0);
signal concSig: std_logic_vector(15 downto 0);
signal RFDSig1: std_logic_vector(15 downto 0);
signal RFDSig2: std_logic_vector(15 downto 0);
signal PCclr: std_logic;
signal PCen: std_logic;
signal IRclr: std_logic;
signal IRen: std_logic;
signal MDclr: std_logic;
signal RegWren: std_logic;
signal Aclr: std_logic;
signal Bclr: std_logic;
signal ALUoutclr: std_logic;
signal ALUop: std_logic_vector(3 downto 0);
signal ALUflag: std_logic;
signal memaddrSelect: std_logic;
signal regfileDataSelect: std_logic_vector(2 downto 0);
signal regfileRegSelectSelect: std_logic_vector(1 downto 0);
signal AinSelect: std_logic;
signal BinSelect: std_logic;
signal PCinSelect: std_logic_vector(1 downto 0);
signal regfifteen: std_logic_vector(15 downto 0);
component reg is
port(clk, clr: in std_logic;
a: in std_logic_vector (15 downto 0);
o: out std_logic_vector (15 downto 0));
end component reg;
component mux is
port( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
s:
in std_logic;
o: out std_logic_vector(3 downto 0));
end component mux;
component alu is
port(
a
:in std_logic_vector(15 downto 0);
b
:in std_logic_vector(15 downto 0);
s
:in std_logic_vector(3 downto 0);
z : out std_logic;
ALUout
:out std_logic_vector(15 downto 0));
end component alu;
component mux1 is
port( a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
c: in std_logic_vector(15 downto 0);
d: in std_logic_vector(15 downto 0);
s: in std_logic_vector(1 downto 0);
o: out std_logic_vector(15 downto 0));
end component mux1;
component mux3 is
port( a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
c: in std_logic_vector(15 downto 0);
d: in std_logic_vector(15 downto 0);
e: in std_logic_vector(15 downto 0);
s: in std_logic_vector(2 downto 0);
o: out std_logic_vector(15 downto 0));
end component mux3;
component pc is
port(
clk, clr,en: in std_logic;
a: in std_logic_vector (15 downto 0);
b: out std_logic_vector (15 downto 0));
end component pc;
component mux2 is
port( a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
s:
in std_logic;
o: out std_logic_vector(15 downto 0));
end component mux2;
component regfile is
port(
clock
: in std_logic;
regwr
: in std_logic;
-reset
: in std_logic;
wrreg
: in std_logic_vector(3 downto 0);
rr1
: in std_logic_vector(3 downto 0);
--selects rd1
rr2
: in std_logic_vector(3 downto 0);
--selects rd2
wrdata
: in std_logic_vector(15 downto 0);
rd1
: out std_logic_vector(15 downto 0); --hardwired to A
rd2
: out std_logic_vector(15 downto 0); --hardwired to B
regfifteen: out std_logic_vector(15 downto 0);
inr: in std_logic_vector(3 downto 0);
--selects outvalue
outvalue: out std_logic_vector(15 downto 0)
--hardwired to Mem port
);
end component regfile;
component shift is
port( shiftIn: in std_logic_vector(9 downto 0);
shiftOut: out std_logic_vector(11 downto 0));
end component shift;
component mux4 is
port( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
c: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
o: out std_logic_vector(3 downto 0));
end component mux4;
component CU is
port(PCclr: out std_logic;
PCen: out std_logic;
IRclr: out std_logic;
IRen: out std_logic;
MDclr: out std_logic;
RegWren: out std_logic;
Aclr: out std_logic;
Bclr: out std_logic;
ALUoutclr: out std_logic;
ALUop: out std_logic_vector(3 downto 0);
ALUflag: in std_logic;
memaddrSelect: out std_logic;
memWriteEn: out std_logic;
regfileDataSelect: out std_logic_vector(2 downto 0);
regfileRegSelectSelect: out std_logic_vector(1 downto 0);
AinSelect: out std_logic;
BinSelect: out std_logic;
PCinSelect: out std_logic_vector(1 downto 0);
clk: in std_logic;
opcode: in std_logic_vector(3 downto 0));
end component CU;
begin
concSig <= PCout(15 downto 12) & Sl2out;
RFDSig1 <= IRout(7 downto 0) & "--------";
RFDSig2 <= "--------" & IRout(7 downto 0);
Control: CU
port map(PCclr,
PCen,
IRclr,
IRen,
MDclr,
RegWren,
Aclr,
Bclr,
ALUoutclr,
ALUop,
ALUflag,
memaddrSelect,
writeEn,
regfileDataSelect,
regfileRegSelectSelect,
AinSelect,
BinSelect,
PCinSelect,
clk,
IRout(15 downto 12));
PCount: pc
port map(clk,PCclr,PCen,
PCin, PCout);
InstReg: pc
port map(clk, IRclr,IRen,
datain, IRout);
MemData: reg
port map(clk, MDclr,
datain, MDout);
registerFile: regfile
port map(
clk,
RegWren,
RegfileRegSelect,
IRout(7 downto 4),
IRout(3 downto 0),
RegfileDin,
Ain,
Bin,
regfifteen,
RegfileRegSelect,
dataout);
Areg: reg
port map(clk, Aclr,
Ain, Aout);
Breg: reg
port map(clk, Bclr,
Bin, Bout);
ALUoutReg: reg
port map(clk, ALUoutclr,
ALUout, ALUoutRegOut);
ALUnit: alu
port map( ALUinA,
ALUinB,
ALUop,
ALUflag,
ALUout);
memaddrMUX: mux2
port map( PCout,
ALUoutRegOut,
memaddrSelect,
memaddr);
regfileDataMUX: mux3
port map( MDout,
ALUoutRegOut,
RFDSig1,
RFDSig2,
PCout,
regfileDataSelect,
RegfileDin);
regfileRegSelectMUX: mux4
port map( IRout(3 downto 0),
IRout(11 downto 8),
"1111",
regfileRegSelectSelect,
RegfileRegSelect);
AinMUX: mux2
port map(Aout,
PCout,
AinSelect,
ALUinA);
BinMUX: mux2
port map(Bout,
"0000000000000100",
BinSelect,
ALUinB);
PCinMUX: mux1
port map(ALUout,
ALUoutRegOut,
concSig,
regfifteen,
PCinSelect,
PCin);
shifter: shift
port map(IRout(9 downto 0),
Sl2out);
end architecture datpat;
mem.vhd
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: mem.vhd
-- Megafunction Name(s):
--
altsyncram
--- Simulation Library Files(s):
--
altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--- 12.0 Build 178 05/31/2012 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2012 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors.
Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY mem IS
PORT
(
address
: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock
: IN STD_LOGIC
data
: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren
: IN STD_LOGIC ;
q
: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
:= '1';
);
END mem;
ARCHITECTURE SYN OF mem IS
SIGNAL sub_wire0
: STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a
: STRING;
clock_enable_output_a
init_file
: STRING;
: STRING;
intended_device_family
lpm_hint
: STRING;
lpm_type
: STRING;
: STRING;
numwords_a
: NATURAL;
operation_mode
: STRING;
outdata_aclr_a
: STRING;
outdata_reg_a
: STRING;
power_up_uninitialized
: STRING;
widthad_a
: NATURAL;
width_a
: NATURAL;
width_byteena_a
: NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock0
: IN STD_LOGIC ;
data_a
: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a
: IN STD_LOGIC ;
q_a
: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q
<= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "../RAM_init.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1234",
lpm_type => "altsyncram",
numwords_a => 8192,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
widthad_a => 13,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "1234"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "../RAM_init.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "../RAM_init.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1234"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL mem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
mux3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity mux3 is
port( a: in std_logic_vector(15 downto 0);
b: in std_logic_vector(15 downto 0);
c: in std_logic_vector(15 downto 0);
d: in std_logic_vector(15 downto 0);
e: in std_logic_vector(15 downto 0);
s: in std_logic_vector(2 downto 0);
o: out std_logic_vector(15 downto 0));
end mux3;
architecture multiplexer of mux3 is
begin
process(a, b, c, S)
begin
if(S = "000") then
o <= a;
elsif(S = "001") then
o <= b;
elsif(S = "010") then
o <= c;
elsif(S = "011") then
o <= d;
elsif(S = "100") then
o <= e;
end if;
end process;
end architecture multiplexer;
mux4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity mux4 is
port( a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
c: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
o: out std_logic_vector(3 downto 0));
end mux4;
architecture multiplexer of mux4 is
begin
process(a, b, S)
begin
if(S = "00") then
o <= a;
elsif(S = "01") then
o <= b;
elsif(S = "10") then
o <= c;
end if;
end process;
end architecture multiplexer;
pc.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pc is
port(
clk, clr,en: in std_logic;
a: in std_logic_vector (15 downto 0);
b: buffer std_logic_vector (15 downto 0));
end entity pc;
architecture reg of pc is
begin
process (clk,clr,en)
begin
if (b = "UUUUUUUUUUUUUUUU") then
b <= "0000000000000000";
end if;
if clr = '0' then
b <= "0000000000000000";
elsif (clk'event and clk='1') then
if (en ='1') then
b <= a;
end
end
end
end
if;
if;
process;
architecture reg;
reg.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity reg is
port(clk, clr: in std_logic;
a: in std_logic_vector (15 downto 0);
o: out std_logic_vector (15 downto 0)
);
end entity reg;
architecture reg1 of reg is
signal ou: std_logic_vector (15 downto 0);
begin
process (clk,clr,a)
begin
if (clr = '0') then
ou <= (others =>'0');
elsif (clk'event and clk='1')
ou <= a;
end if;
end process;
o <= ou;
end architecture reg1;
then
regfile.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity regfile is
port(
clock
: in std_logic;
regwr
: in std_logic;
-reset
: in std_logic;
wrreg
: in std_logic_vector(3 downto 0);
rr1
: in std_logic_vector(3 downto 0);
rr2
: in std_logic_vector(3 downto 0);
wrdata
: in std_logic_vector(15 downto 0);
rd1
: out std_logic_vector(15 downto 0);
rd2
: out std_logic_vector(15 downto 0);
regfifteen: out std_logic_vector(15 downto 0);
inr: in std_logic_vector(3 downto 0);
outvalue: out std_logic_vector(15 downto 0)
);
end regfile;
--selects rd1
--selects rd2
--hardwired to A
--hardwired to B
--selects outvalue
--hardwired to Mem port
architecture rtl of regfile is
type regs is array(0 to 15) of std_logic_vector(15 downto 0);
signal reg : regs;
begin
process(clock,wrdata,regwr)
begin
-- if initialisation of register file on 'reset' is required then uncomment the following lines and reset signal in the entity
-- if (reset = '0') then
------------------
reg(0)<= "0000000000000000";
reg(1)<= "0000000000000000";
reg(2)<= "0000000000000000";
reg(3)<= "0000000000000000";
reg(4)<= "0000000000000000";
reg(5)<= "0000000000000000";
reg(6)<= "0000000000000000";
reg(7)<= "0000000000000000";
reg(8)<= "0000000000000000";
reg(9)<= "0000000000000000";
reg(10)<= "0000000000000000";
reg(11)<= "0000000000000000";
reg(12)<= "0000000000000000";
reg(13)<= "0000000000000000";
reg(14)<= "0000000000000000";
reg(15)<= "0000000000000000";
elsif
if (clock'event and clock = '1') then
reg(0) <= "0000000000000000";
if regwr = '1' then
if (wrreg = "0000") then
reg(conv_integer('0' & wrreg)) <= "0000000000000000"; -- Register 0 hardwired to zero.
else
for I in 0 to 15 loop
if (wrdata(I) = '-')
then
else
reg(conv_integer('0' & wrreg))(I) <= wrdata(I);
end if;
end loop;
end if;
end if;
end if;
end process;
rd1 <= reg(conv_integer('0' & rr1));
rd2 <= reg(conv_integer('0' & rr2));
regfifteen <= reg(15);
process (inr,reg)
begin
case inr is
when "0000" => outvalue<=reg(0);-- used to display the contents of the registers on FPGA in the final part.
when "0001" =>
outvalue<=reg(1);
when "0010" =>
outvalue<=reg(2);
when "0011" =>
outvalue<=reg(3);
when "0100" =>
outvalue<=reg(4);
when "0101" =>
outvalue<=reg(5);
when "0110" =>
outvalue<=reg(6);
when "0111" =>
outvalue<=reg(7);
when "1000" =>
outvalue<=reg(8);
when "1001" =>
outvalue<=reg(9);
when "1010" =>
outvalue<=reg(10);
when "1011" =>
outvalue<=reg(11);
when "1100" =>
outvalue<=reg(12);
when "1101" =>
outvalue<=reg(13);
when "1110" =>
outvalue<=reg(14);
when "1111" =>
outvalue<=reg(15);
when others => outvalue<="0000000000000000";
end case;
end process;
end rtl;
sr.vhd
library ieee;
use ieee.std_logic_1164.all;
entity shift is
port( shiftIn: in std_logic_vector(9 downto 0);
shiftOut: out std_logic_vector(11 downto 0));
end entity shift;
architecture shifter of shift is
begin
shiftOut <= shiftIn & "00";
end architecture shifter;