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The Devices Jan M. Rabaey Digital Integrated Circuits Devices © Prentice Hall 1995 Goal of this chapter • Present intuitive understanding of device operation • Introduction of basic device equations • Introduction of models for manual analysis • Introduction of models for SPICE simulation • Analysis of secondary and deep-sub-micron effects • Future trends Digital Integrated Circuits Devices © Prentice Hall 1995 The MOS Transistor Gate Oxyde Gate Source Polysilicon n+ Drain n+ p-substrate Field-Oxyde (SiO2) p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Digital Integrated Circuits Devices © Prentice Hall 1995 Cross-Section of CMOS Technology Digital Integrated Circuits Devices © Prentice Hall 1995 MOS transistors Types and Symbols D D G G S S NMOS Enhancement NMOS Depletion D D G G S S PMOS Enhancement Digital Integrated Circuits B Devices NMOS with Bulk Contact © Prentice Hall 1995 Threshold Voltage: Concept + S VGS - D G n+ n+ n-channel Depletion Region p-substrate B Digital Integrated Circuits Devices © Prentice Hall 1995 The Threshold Voltage Digital Integrated Circuits Devices © Prentice Hall 1995 Current-Voltage Relations VGS VDS S G n+ – V(x) ID D n+ + L x p-substrate B MOS transistor and its bias conditions Digital Integrated Circuits Devices © Prentice Hall 1995 Current-Voltage Relations Digital Integrated Circuits Devices © Prentice Hall 1995 Transistor in Saturation VGS VDS > VGS - VT G D S n+ Digital Integrated Circuits - VGS - VT Devices + n+ © Prentice Hall 1995 I-V Relation VDS = VGS-VT Saturation ID (mA) VGS = 4V 1 VGS = 3V VGS = 2V VGS = 1V 0.0 1.0 2.0 3.0 4.0 5.0 VDS (V) 0.020 ÷ID Triode Square Dependence 2 VGS = 5V 0.010 Subthreshold Current 0.0 2.0 VT1.0 VGS (V) 3.0 (b) ID as a function of VGS (for VDS = 5V). (a) ID as a function of VD S NMOS Enhancement Transistor: W = 100 m, L = 20 m Digital Integrated Circuits Devices © Prentice Hall 1995 A model for manual analysis Digital Integrated Circuits Devices © Prentice Hall 1995 Dynamic Behavior of MOS Transistor G CGS CGD D S CGB CSB CDB B Digital Integrated Circuits Devices © Prentice Hall 1995 The Gate Capacitance Digital Integrated Circuits Devices © Prentice Hall 1995 Average Gate Capacitance Different distributions of gate capacitance for varying operating conditions Most important regions in digital design: saturation and cut-off Digital Integrated Circuits Devices © Prentice Hall 1995 Diffusion Capacitance Digital Integrated Circuits Devices © Prentice Hall 1995 Junction Capacitance Digital Integrated Circuits Devices © Prentice Hall 1995 Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest Digital Integrated Circuits Devices © Prentice Hall 1995 The Sub-Micron MOS Transistor • Threshold Variations • Parasitic Resistances • Velocity Sauturation and Mobility Degradation • Subthreshold Conduction • Latchup Digital Integrated Circuits Devices © Prentice Hall 1995 Threshold Variations VT Long-channel threshold Low VDS threshold L Threshold as a function of the length (for low VDS) Digital Integrated Circuits Drain-induced barrier lowering (for low L) Devices © Prentice Hall 1995 Parasitic Resistances Polysilicon gate LD G Drain contact W VGS,eff D S RS RD Drain Digital Integrated Circuits Devices © Prentice Hall 1995 Velocity Saturation (1) 2 n (cm /Vs) n (cm/sec) sat = 10 7 constant velocity Constant mobility (slope = ) Esat E V/m) 700 250 0 EtV/m) (b) Mobility degradation (a) Velocity saturation Digital Integrated Circuits n0 Devices © Prentice Hall 1995 Velocity Saturation (2) 1.5 0.5 VGS = 3 0.5 VGS = 2 VGS = 1 0.0 1.0 2.0 VDS 3.0 (V) 4.0 5.0 (a) I D as a function of VDS ID (mA) VGS = 4 I D (mA) 1.0 Linea r Dependence VGS = 5 0 0.0 1.0 2.0 VGS (V) 3.0 (b) ID as a function of VGS (for VDS = 5 V). Linear Dependence on VGS Digital Integrated Circuits Devices © Prentice Hall 1995 Sub-Threshold Conduction 102 ln(ID) (A) 104 Linear region 106 108 1010 10120.0 Digital Integrated Circuits Subthreshold exponential region VT 1.0 2.0 3.0 VGS (V) Devices © Prentice Hall 1995 Latchup VD D VDD + p + n n+ + p + n+ p n-well p-source Rnwell Rpsubs n-source p-substrate (a) Origin of latchup Digital Integrated Circuits Rnwell Devices Rpsubs (b) Equivalent circuit © Prentice Hall 1995 SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular Digital Integrated Circuits Devices © Prentice Hall 1995 MAIN MOS SPICE PARAMETERS Digital Integrated Circuits Devices © Prentice Hall 1995 SPICE Parameters for Parasitics Digital Integrated Circuits Devices © Prentice Hall 1995 SPICE Transistors Parameters Digital Integrated Circuits Devices © Prentice Hall 1995 Fitting level-1 model for manual analysis Region of matching ID Short-channel I-V curve VGS = 5 V Long-channel approximation VDS = 5 V VDS Select k’ and such that best matching is obtained @ Vgs= Vds = VDD Digital Integrated Circuits Devices © Prentice Hall 1995 Technology Evolution Digital Integrated Circuits Devices © Prentice Hall 1995
