J. Parsons, LAr Electronics, LHCC, July 1/2003 2


Full functionality was demonstrated by Module 0 electronics (~6k channels), used in testbeam measurements of CAL modules for past several years
 Due to schedule constraints, was not required to be radiation tolerant

First rad-tol prototypes of the various boards are now available

A system test (1/2 crate) is last step before launching full production
 System test to be completed before end of 2003, with production to be launched beginning of 2004 (installation in ATLAS pit starts 11/2004)
J. Parsons, LAr Electronics, LHCC, July 1/2003 3


Moving to rad-tol version of FE electronics required development and qualification of a total of 15 custom rad-tol ASICS (in various technologies):


10 in DMILL
4 in DSM (using rad-tol standard cell library)
 1 in AMS BiCMOS
 All custom ASICs are available, or are in production

A limited number of COTs are needed (ADC, op-amps, GLink, line driver)



Extensive radiation qualification procedures performed
Procurement plans targeted single lot, or limited number of lots
All production COTs have been purchased and qualified, except for ADC for which common ATLAS/CMS/LHCb order is to be signed very soon

LAr FE (and particularly FEB) has extensive needs for Vregs (both + and -)



ST contracted by CERN to develop rad-tol Vregs for general LHC use
Positive Vregs (L4913) successfully developed, and production quantities avail.
Negative Vreg (L7913) design continues to have technical problems, and is significantly impacting our FE electronics development
J. Parsons, LAr Electronics, LHCC, July 1/2003 4


LAr has 3 different DMILL wafer sets:
1. SCA production (200 wafers)
 robotic testing should be finished TODAY!
(> 85k SCA chips tested)
 we have enough good SCA chips
2. Analog wafers (12 wafers of BiMUX, opamp)


 wafers received in Jan. 2003 closure of ASAT France has led to lengthy (> 3 mo.) delays in packaging tests on chips from first wafer have reasonable yield; remaining 11 sent for pkging
3. Digital wafers (27 wafers of SPAC, CALogic, CONFIG, SMUX, DAC)
 wafer processing underway, with delivery scheduled for August 2003
 failure of ATMEL to deliver would have far-reaching consequences
•
DSM replacements would need to be developed
•
Significant re-design would be needed for ALL boards
 we are closely monitoring the DMILL situation
J. Parsons, LAr Electronics, LHCC, July 1/2003 5


3 LAr-specific DSM ASICs (SCAC, GainSel, CLKFO)

MPW runs used to demonstrate design, rad. tolerance
 PRR passed in September 2002
 Enough devices available for short-term needs

For production, all 3 placed in same reticle (along with ALICE chip from Nikhef for some cost sharing)

Engineering run (2 wafers) delivered April 22
 Goals: produce final masks, determine yield, re-verify rad. tolerance
 Due to pkg’ing delays, we still have not received the chips (expected mid-May)
 We have postponed (twice!) the irrad. tests, now re-scheduled for July 19/20

Once eng. run tests done, submit production order (45 wafers)
 Still in time for FEB production needs, but need to pay attention to schedule
J. Parsons, LAr Electronics, LHCC, July 1/2003 6


ST was contracted by CERN to develop rad-tol Vregs (both + and -)

Pos. Vreg (L4913) successfully developed and now avail. in quantity
 We have been using these devices since early 2002
 We have by now purchased and received the full production quantity

Neg. Vreg (L7913) has gone through several iterations, but continues to suffer from technical problems
 JQ3 (04/2002) – non-functional


JQ4 (11/2002) – functional, but tends to oscillate
JQ5 (05/2003) – more stable, but suffers from thermal instability for large loads

L7913 problems have significantly delayed FE system test, which was originally scheduled for Summer 2002


We have tried hard, but not succeeded, in finding a suitable alternate solution
To minimize delay, we have proceeded with design of boards using L7913, and tested them as best we could (eg. with less-than-perfect L7913 samples, commercial Vregs, etc.) to be ready when L7913 becomes available
J. Parsons, LAr Electronics, LHCC, July 1/2003 7


On June 24, 10 JQ5 samples were received at Nevis, and were immediately added to our existing 2 FEB prototypes


Preliminary tests verify improved stability compared to JQ4
It is possible the JQ5 thermal problem would not be serious in our application

On June 26, P. Farthouat and J. Parsons visited ST Catania

Outcomes of the (very positive) meeting included:
 ST will deliver this week to CERN 200 samples of JQ5 version


By end July, ST will provide new specs for JQ5 as possible backup solution
Tapeout of new (JQ6) version was end of last week


Samples of JQ6 will be delivered October 6 in sufficient quantity for FE tests
Production quantities of either JQ5 or JQ6 could be available by March 2004
 ST will provide monthly status reports to allow us to monitor developments

We plan to proceed now with FE crate test with JQ5, and make further tests with JQ6 once they are available in October
 L7913 continues to represent significant risk to FE electronics development
J. Parsons, LAr Electronics, LHCC, July 1/2003 8

Front End Board (FEB) :
1524 boards @ 128 ch
J. Parsons, LAr Electronics, LHCC, July 1/2003 9

Calibration :
116 boards @ 128 ch
J. Parsons, LAr Electronics, LHCC, July 1/2003 10

Controller :
116 boards
Tower builder (TBB) :
120 boards @ 32 ch
J. Parsons, LAr Electronics, LHCC, July 1/2003 11

 300 VDC brought to area of TileCal “fingers”

FE crate requires 7 different DC voltages

Technical solution with DC-DC convertors was developed through an extended R&D and radiation qualification program
 Produce modules with specially chosen components
 Provide redundancy due to SEU-burnout concerns
 Contract awarded for production of 2 prototypes


Significant delays incurred in finalizing services, requirements
Prototype delivery now scheduled for end August 2003


FE crate will have to start with other LVPS
Have only 60 days after prototype delivery to exercise option for full production
 Need to follow schedule very closely
J. Parsons, LAr Electronics, LHCC, July 1/2003 12


Before proceeding to PRR and then production for the various FEC boards, plan a system test with all boards together, filling the “basic unit” of ½ FEC

FEC test setup will include:


“dummy” calorimeter loads cables (det

FT
 baseplane)
 FE crate, including:
•
PWR/signal distribution
• water cooling


Prototype LV power supply
Controller, CALIB, TTB boards


From 1 FEB, to 14 FEBs
Prototype Monitor boards


DCS monitoring with ELMB
VME-based TTC + SPACMaster
 Temporary VME-based readout for up to 16 FEBs
J. Parsons, LAr Electronics, LHCC, July 1/2003 13


Setup prepared with 1 FEB, commercial PS

Plan to now produce remaining FEBs, populated with new JQ5 Vreg samples
 Start FEC test in August
 Identify and perform tests which can be done before final Vreg, PS solutions are available
 Move to final power devices as available:


Prototype LVPS in September
JQ6 Vreg samples in October
 Aim for FEC boards’ PRRs in late November


FEC test schedule is very tight
Neg. Vreg and LVPS continue to present significant risks
J. Parsons, LAr Electronics, LHCC, July 1/2003 14

FE crate

Boards in 9U VME ROD crates (in USA15) include:
 192 RODs (16 crates) for processing of FEB data


Transition Module for SLink connection to L2/DAQ
Custom backplane for TTC distribution/BUSY collection
 SPAC Master for FE crate control


Trigger Busy Module for interface to global trigger
Prototypes of all boards exist or are in production

TTC crate uses standard ATLAS TTC infrastructure/fanout
J. Parsons, LAr Electronics, LHCC, July 1/2003 15


RODDemo program was used to validate architecture, component choices

ROD Motherboard (MB) architecture:
 Custom ORx modules, GLink deserialisers
 FPGAs re-route data to every other PU in initial “staging” mode
 O/P data serialized and sent thru backplane to TM and then to L2/DAQ

Processing Unit (PU) architecture:
 Two PUs per daughterboard


I/P FPGA for data checking, reformatting
TMS6414 DSP for processing (1 FEB @ 100 kHz)


FIFOs for O/P data interface to MB
O/P FPGA for VME interface, histo. readout

MB and PU prototypes are currently being tested
Input FPGA DSP
J. Parsons, LAr Electronics, LHCC, July 1/2003
Output FPGA
16
FIFO


ROD Injector


VME board which mimics FEB data
Will be used in BEC test and in production ROD testing
 In ATLAS, can be used to isolate
VME
INTERFACE and debug FEB-ROD problems
 2 FEB version successfully tested
 Final (5 FEB) version being built now
TTC / LOCAL

SPAC Master
 6U VME board (2 Masters) tested

TTC
RECEIVE
R
Final 9U VME version (4 Masters) being finalized
DATA INJECTOR FEB1
DATA INJECTOR FEB2
DATA INJECTOR FEB3
DATA INJECTOR FEB4
DATA INJECTOR
FEB5
Clock, BCR, L1A
BCR, L1A
SEQUENCE
GENERATOR

TBM, TM, CP3
 In fabrication

All modules are expected by September (TBM in late September)
GLINK
GLINK
GLINK
GLINK
GLINK
Clock
BCR
L1A
Busy
To ROD or Optical splitter
To LTP or TTCVI or ROD
From TBM or LTP or ROD
J. Parsons, LAr Electronics, LHCC, July 1/2003 17


Before PRR, do system test , including
5 RODs (w/ 12 PUs)
 Use ROD injectors, with optical splitters, for data inputs, but test will include reading out one actual FEB

BE crate test planned at CERN during September through December
 Modules need to be tested and start to be delivered to CERN by September
 Completion of test delayed by late delivery of ATLAS water-cooled 9U
VME rack, expected in mid-Nov.

After BEC test, BE electronics to be used in Combined TB run (beam starts in 04/2004)
 Limited time window for BE test
 Need to watch schedule carefully
J. Parsons, LAr Electronics, LHCC, July 1/2003 18


We are setting up a general LAr electronics production db


CERN-resident, Oracle-based DB
WWW interface

The BNL preamplifier data has already been stored in the db
 Milano preamplifier data will be incorporated once made available
 As first exercise on boards, a zero’th order version of the interface for the
FEB has recently been set up


At Nevis, we have started to enter data from the two FEB prototypes into the db
Structure will evolve as experience is gained

Goal is to provide support for all LAr electronics in order to centralize storage and simplify long-term support and availability
J. Parsons, LAr Electronics, LHCC, July 1/2003 19


LAr electronics installation in ATLAS pit scheduled to begin 11/2004
 During June LAr week, held first “
LAr Electronics Installation Workshop
”
(~ 40 participants) to begin more detailed discussions about:
 Installation and commissioning steps and strategy
 Sharing of work among the various institutions

Some general conclusions/features of the installation scenario:


Complexity of system, and access problems, will mandate careful coordination and planning
Heavy use will be made of LAr Elec. Maint. Fac. as staging area (see next slide)
 Schedule requires two teams working in parallel on FE installation


BE installed in USA15 in parallel with FE on det. for efficient commissioning
Installation will overlap with electronics production

As next step, a smaller group will draft a note describing in detail the steps involved in the installation, as well as the tests to be performed at each stage in order to validate and qualify the electronics
J. Parsons, LAr Electronics, LHCC, July 1/2003 20


LAr EMF will serve a variety of functions, in different phases:
Short-term (from now until Fall 2004)
• Reception/storage area for all LAr electronics (cables, boards, …)
• Staging area for preparing electronics for B180 and combined TB tests in Spring 2004
Installation (beginning Fall 2004)
• “Go/NoGo for Installation” checks (eg. water tightness, perhaps (limited) electrical tests)
• Filling out/tracking of TC-based installation db paperwork
• Grouping of boards of appropriate configurations for installation
• Debugging/repair of faulty/questionable modules
•
Staging area for faulty boards to be returned to lab responsible
Bldg. 2175,
SR1
Long-term
• Storage area for spares
• Debugging/maintenance facility

Area at Point 1 has been identified
 Getting cleaned out; avail. by 09/03
 Fully operational before installation starts
J. Parsons, LAr Electronics, LHCC, July 1/2003 21


Final prototypes of both FE and BE electronics boards are now available

FE and BE system tests are scheduled to be completed by end of 2003
 Electronics production to start in early 2004
 Installation in ATLAS pit to start by 11/2004

Main concerns continue to be:



Negative Vreg
•
Need to determine if either JQ6 or JQ5 version is suitable for production (10/03)
Rad-tol LVPS
• Need to test prototype and launch production (10/03)
DMILL
• Need successful delivery of LAr DMILL Digital Wafers (08/03)

More detailed installation/commissioning plans are being prepared
 Complexity of system and difficulty of access will require careful coordination
 Production and installation are going to have to overlap
 We need to start now to prepare detailed planning
J. Parsons, LAr Electronics, LHCC, July 1/2003 22