POWER OPTIMIZATION OF CMOS PROGRAMMABLE
GAIN AMPLIFIERS WITH HIGH DYNAMIC RANGE
AND COMMON-MODE FEED-FORWARD CIRCUIT
A. J. Ginés*, R. Doldán, A. Rueda and E. Peralías
Instituto de Microelectrónica de Sevilla (CNM-CSIC)
University of Seville (Spain)
IEEE ICECS 2010
Contents
 Motivations
 State-of-the-Art in Low Voltage PGAs
 Close-loop vs. Open-loop Architectures
 Proposed PGA Architecture
 Design Methodology
 Common-Mode Feed-forward Circuit (CMFFC)
 Verification:
 Post-layout Simulation Results (3-stage PGA)
 Experimental Results (stage core)
 Conclusions
Motivations
 Low-IF ZigBee Receiver
Mixers
90º
LNA
Q
RF
Filter
Frequency
Synthesizer
ADC
Channel
Filter
I
PGA
ADC
PGA
PLL

ZigBee should operate with power levels at the antenna from -85dBm
to -20dBm (DR > 64dB).

Adjustable gain through the chain is need to optimize the
sensitivity and signal-to-noise ratio (SNR).

Power consumption is one of the most critical design constraints in
ZigBee standard.
IMSE-CNM
ICECS 2010, Athens (Greece)
1
Motivations
 Low-IF ZigBee Receiver
Mixers
90º
LNA
Q
RF
Filter
Frequency
Synthesizer
ADC
Channel
Filter
I
PGA
ADC
PGA
PLL
This Work

ZigBee should operate with power levels at the antenna from -85dBm
to -20dBm (DR > 64dB).

Adjustable gain through the chain is need to optimize the
sensitivity and signal-to-noise ratio (SNR).

Power consumption is one of the most critical design constraints in
ZigBee standard.
IMSE-CNM
ICECS 2010, Athens (Greece)
1
Contents
 Motivations
 State-of-the-Art in Low Voltage PGAs
 Close-loop vs. Open-loop Architectures
 Proposed PGA Architecture
 Design Methodology
 Common-Mode Feed-forward Circuit (CMFFC)
 Verification:
 Post-layout Simulation Results (3-stage PGA)
 Experimental Results (stage core)
 Conclusions
State-of-the-Art in Low Voltage PGAs
 Close-loop Architectures
Rin
Rf
Vinn
Voutp
+
Vinp
Rin
+
Voutn
Rf
G = Rf / Rin
IMSE-CNM
ICECS 2010, Athens (Greece)
2
State-of-the-Art in Low Voltage PGAs
 Close-loop Architectures
Rin
Rf
Vinn
Voutp
+
Vinp
Take advantage of resistive feedback
to achieve:
Rin

High Linearity

Low Noise
+
Voutn
Rf
G = Rf / Rin
IMSE-CNM
ICECS 2010, Athens (Greece)
2
State-of-the-Art in Low Voltage PGAs
 Close-loop Architectures
Rin
Rf
Vinn
Voutp
+
Vinp
Take advantage of resistive feedback
to achieve:
Rin
G = Rf / Rin
IMSE-CNM
+
Voutn
Rf

High Linearity

Low Noise
Drawbacks of the classical approach:

Gain programmability introduces
stability issues.

Low voltage limitations due to equal
common modes (cmi = cmo).

Buffers are required to deal with low
input impedance.
ICECS 2010, Athens (Greece)
2
State-of-the-Art in Low Voltage PGAs
 Close-loop Architectures
Rin
Rf
Vinn
Voutp
+
Vinp
Take advantage of resistive feedback
to achieve:
Rin
+
Voutn
Rf
G = Rf / Rin

High Linearity

Low Noise
Drawbacks of the classical approach:

Gain programmability introduces
stability issues.

Low voltage limitations due to equal
common modes (cmi = cmo).

Buffers are required to deal with low
input impedance.
(1-D)IS
IS
Rin
Vinn
-
Vinp
+
+
-
Rf
CDN
-
CDN
+
Rin
IS
IMSE-CNM
D
+
-
Voutp
Current Division Network (CDN)
Voutn
Reference: [3]
Rf
ICECS 2010, Athens (Greece)
2
State-of-the-Art in Low Voltage PGAs
 Close-loop Architectures
Rin
Take advantage of resistive feedback
to achieve:
Rf
Vinn
Voutp
+
Vinp
Rin
+
Rf
Rin
Rf
+
Vinp
Rin
High Linearity

Low Noise
Drawbacks of the classical approach:
Voutn
G = Rf / Rin
Vinn

Voutp
+
-

Gain programmability introduces
stability issues.

Low voltage limitations due to equal
common modes (cmi = cmo).

Buffers are required to deal with low
input impedance.
Voutn
Rf
Decoupling common mode (cmi ≠ cmo)
Reference: [4]
VREFin
IMSE-CNM
+
-
+
-
VREFout
ICECS 2010, Athens (Greece)
2
State-of-the-Art in Low Voltage PGAs
 Close-loop Architectures
Rin
Rf
Vinn
Voutp
+
Vinp
Take advantage of resistive feedback
to achieve:
Rin
G = Rf / Rin
+
Voutn
Rf

High Linearity

Low Noise
Drawbacks of the classical approach:

Gain programmability introduces
stability issues.

Low voltage limitations due to equal
common modes (cmi = cmo).

Buffers are required to deal with low
input impedance.
Transimpedance amplifier
Reference: [6]
IMSE-CNM
ICECS 2010, Athens (Greece)
2
State-of-the-Art in Low Voltage PGAs
 Close-loop Architectures
Rin
Take advantage of resistive feedback
to achieve:
Rf
Vinn
Voutp
+
Vinp
Rin

High Linearity

Low Noise
+
Voutn
Rf
G = Rf / Rin
Main drawback for ZigBee:

High power consumption is required
for driving resistive load.

It does not take advantage of the
standard linearity relaxation.
IMSE-CNM
Solution: Open-loop topologies !!!
ICECS 2010, Athens (Greece)
2
State-of-the-Art in Low Voltage PGAs
 Open-loop Architectures
Ro
Vinn
Vinp
+
gm
+
Voutp
Voutn
Ro
G = gmRo
IMSE-CNM
ICECS 2010, Athens (Greece)
3
State-of-the-Art in Low Voltage PGAs
 Open-loop Architectures
Advantages:
Ro
Vinn
Vinp
+
gm
+
Voutp
Voutn

High-speed and high-stability

Low-Power
Ro
G = gmRo
Gilbert’s Cell
Ro
Voutp
Voutn
Ro
+
Vc
Vinn
M1
Vinp
M2
References: [8-10]
IMSE-CNM
ICECS 2010, Athens (Greece)
3
State-of-the-Art in Low Voltage PGAs
 Open-loop Architectures
Advantages:
Ro
Vinn
Vinp
+
gm
+
Voutp
Voutn
Ro
G = gmRo

High-speed and high-stability

Low-Power
Drawbacks:

Gain is not accurately defined.

Low-voltage operation.

Non-linearity
Gilbert’s Cell
Ro
Voutp
Voutn
Ro
+
Vc
Vinn
M1
Vinp
M2
References: [8-10]
IMSE-CNM
ICECS 2010, Athens (Greece)
3
State-of-the-Art in Low Voltage PGAs
 Open-loop Architectures
Advantages:
Ro
Vinn
+
gm
+
Vinp
Voutp
Voutn
Ro
G = gmRo

High-speed and high-stability

Low-Power
Drawbacks:

Gain is not accurately defined.

Low-voltage operation.

Non-linearity
Gilbert’s Cell
Ro
Voutp
Voutn
Voutp
Voutn
Ro
+
Vc
Vinn
-
Vinp
M1
M2
M3
M4
Vinn
M1
Vinp
M2
References: [8-10]
IMSE-CNM
ICECS 2010, Athens (Greece)
3
State-of-the-Art in Low Voltage PGAs
 Open-loop Architectures
Advantages:
Ro
Vinn
+
gm
+
Vinp
Voutp
Voutn
Ro
G = gmRo

High-speed and high-stability

Low-Power
Drawbacks:

Gain is not accurately defined.

Low-voltage operation.

Non-linearity
Gilbert’s Cell
Ro
Voutp
Voutn
Voutp
Voutn
Ro
+
Vc
Vinn
-
Vinp
M1
M2
M3
M4
Vinn
M1
Vinp
M2
References: [8-10]
IMSE-CNM
ICECS 2010, Athens (Greece)
3
State-of-the-Art in Low Voltage PGAs
 Open-loop Architectures with Feed-back
Ioutp
Vinn
2RS
M1
IMSE-CNM
Ioutn
M2
Resistive degeneration
enhances linearity
ICECS 2010, Athens (Greece)
4
State-of-the-Art in Low Voltage PGAs
 Open-loop Architectures with Feed-back
Ioutp
Vinn
Ioutn
2RS
M1
M2
Resistive degeneration
enhances linearity
Further Improvement
This Work
References: [18-22]
Gain Boosting
Servo-loop [20,21]
Super-Source Follower (SSF) [18,19]
2RS
(CS)
OTA
Ioutp
IMSE-CNM
Mfb2
Ioutn
Vinn
+
Vinp
+
M1fb1
2RS
Vinp
Ioutp
ICECS 2010, Athens (Greece)
+
Vinn
+
M1fb1
Mfb2
Ioutn
4
Contents
 Motivations
 State-of-the-Art in Low Voltage PGAs
 Close-loop vs. Open-loop Architectures
 Proposed PGA Architecture
 Design Methodology
 Common-Mode Feed-forward Circuit (CMFFC)
 Verification:
 Post-layout Simulation Results (3-stage PGA)
 Experimental Results (stage core)
 Conclusions
Proposed Low Power PGA Architecture
 A 1.2V 72dB 3-stage PGA in 90nm CMOS process
Vinn,2
-
-
IMSE-CNM
+
+
-
RZ
Vinp,2
STG2
+
-
CZ
STG1
+
-
Vinn
+
STG3
+
-
Vinp
Voutp
Voutn
cmi
ICECS 2010, Athens (Greece)
5
Proposed Low Power PGA Architecture
 A 1.2V 72dB 3-stage PGA in 90nm CMOS process
Vinp,2
+
Vinn,2
+
-
-
v1
M5
Co
IMSE-CNM
C1
M1
M3
BiasN
+
-
Voutp
+
STG3
+
Voutp
Voutn
(FN +F3 )Ib
2RS
Ro
-
Vbp
F5 Ib
+
cmi
RZ
BiasP
STG2
-
CZ
STG1
-
Vinn
+
-
Vinp
Vbn
Ro
Ib
Voutn
M2
M4
FN Ib
M6
Vbn
Co
ICECS 2010, Athens (Greece)
5
Proposed Low Power PGA Architecture
 A 1.2V 72dB 3-stage PGA in 90nm CMOS process
Vinp,2
+
Vinn,2
+
-
-
M5
Co
IMSE-CNM
C1
M3
BiasN
+
-
v1
M1
-
Voutp
(FN +F3 )Ib
2RS
Ro
+
STG3
+
Voutp
Voutn
How much currents in
90nm CMOS?
Vbp
F5 Ib
+
cmi
RZ
BiasP
STG2
-
CZ
STG1
-
Vinn
+
-
Vinp
Vbn
Ro
Ib
Stress due to trench
isolation barriers!!!
Voutn
M2
M4
FN Ib
M6
Vbn
Co
ICECS 2010, Athens (Greece)
5
Proposed Low Power PGA Architecture
 A 1.2V 72dB 3-stage PGA in 90nm CMOS process
Vinp,2
+
Vinn,2
+
-
-
M5
Co
C1
M3
BiasN
+
-
v1
M1
-
Voutp
(FN +F3 )Ib
2RS
Ro
+
STG3
+
Voutp
Voutn
How much currents in
90nm CMOS?
Vbp
F5 Ib
+
cmi
RZ
BiasP
STG2
-
CZ
STG1
-
Vinn
+
-
Vinp
Vbn
Ro
Ib
Stress due to trench
isolation barriers!!!
Voutn
M2
M4
FN Ib
M6
Vbn
Co
All the transistors have
the same width, length
and number of fingers.
The only difference is
the multiplicity.
IMSE-CNM
ICECS 2010, Athens (Greece)
5
Proposed Low Power PGA Architecture
 A 1.2V 72dB 3-stage PGA in 90nm CMOS process
Vinp,2
+
Vinn,2
+
STG2
+
+
-
-
-
CZ
STG1
-
-
Vinn
+
STG3
Voutp
Voutn
+
-
Vinp
cmi
RZ
Gain
G
Vbp
BiasP
Voutp
v1
M5
Co
C1
M1
M3
BiasN
(FN +F3 )Ib
2RS
Ro
+
-
F5 Ib
Vbn
Ro
Voutn
Poles
M2
M4
FN Ib
1 
Ib
M6
1
Ro Co
2  1 
Vbn
1
g m1rds1rds 3C1
Co
Zero
IMSE-CNM
Ro g m5 F5 Ro F5


FS
RS g m3 F3 RS F3
ICECS 2010, Athens (Greece)
z 
1
RZ CZ
5
Proposed Low Power PGA Architecture
 Design Methodology
Vbp
VDD Ib C0 ω2
IMSE-CNM
Ro
Voutp
v1
THD OS Noise
M5
Co
2RS
C1
M1
-
Specifications
G BW Power
BiasP
F5 Ib
+
M3
BiasN
ICECS 2010, Athens (Greece)
Vin
Vbn
( FN +F3 )Ib
Ro
Ib
Voutn
M2
M4
M6
FN Ib
Vbn
Co
6
Proposed Low Power PGA Architecture
 Design Methodology
Vbp
VDD Ib C0 ω2
Ro
Voutp
v1
THD OS Noise
M5
Co
2RS
C1
M1
-
Specifications
G BW Power
BiasP
F5 Ib
+
M3
BiasN
Vin
Vbn
( FN +F3 )Ib
Ro
Ib
Voutn
M2
M4
M6
FN Ib
Vbn
Co
Initial
guess
cmo, cmi
IMSE-CNM
ICECS 2010, Athens (Greece)
6
Proposed Low Power PGA Architecture
 Design Methodology
Vbp
VDD Ib C0 ω2
Initial
guess
cmo, cmi
IMSE-CNM
Ro
Voutp
v1
THD OS Noise
M5
Co
2RS
C1
M1
-
Specifications
G BW Power
BiasP
F5 Ib
+
M3
BiasN
Vin
Vbn
( FN +F3 )Ib
Ro
Ib
Voutn
M2
M4
M6
FN Ib
Vbn
Co
Formulae
BW, C0  R0
cmo, R0 F5
ICECS 2010, Athens (Greece)
6
Proposed Low Power PGA Architecture
 Design Methodology
Vbp
VDD Ib C0 ω2
Initial
guess
cmo, cmi
Ro
Voutp
M1
v1
THD OS Noise
M5
Co
Formulae
BW, C0  R0
cmo, R0 F5
2RS
C1
-
Specifications
G BW Power
BiasP
F5 Ib
+
M3
BiasN
Vin
Vbn
Pick Values
( FN +F3 )Ib
Ro
Ib
Voutn
M2
M4
M6
FN Ib
Vbn
Co
Formulae
G, ω2 F3
Fs=R0/RS
FN
W1, W5, W4, WBP, WBN
OP-AC
Simulation
NO
IMSE-CNM
ICECS 2010, Athens (Greece)
BW, Noise ?
6
Proposed Low Power PGA Architecture
 Design Methodology
Vbp
VDD Ib C0 ω2
Initial
guess
Ro
Voutp
M5
Co
Formulae
BW, C0  R0
cmo, cmi
M1
v1
THD OS Noise
2RS
cmo, R0 F5
C1
-
Specifications
G BW Power
BiasP
F5 Ib
+
M3
BiasN
Vin
Vbn
Pick Values
( FN +F3 )Ib
Ro
Ib
Voutn
M2
M4
M6
FN Ib
Vbn
Co
Formulae
G, ω2 F3
Fs=R0/RS
FN
W1, W5, W4, WBP, WBN
OP-AC
Simulation
NO
YES
END
IMSE-CNM
THD, Power ?
NO
PSS
Simulation
ICECS 2010, Athens (Greece)
BW, Noise ?
YES
6
Proposed Low Power PGA Architecture
 Key Aspects in the Design
Vinn,2
-
-
IMSE-CNM
+
+
-
RZ
Vinp,2
STG2
+
-
CZ
STG1
+
-
Vinn
+
STG3
+
-
Vinp
Voutp
Voutn
cmi
ICECS 2010, Athens (Greece)
7
Proposed Low Power PGA Architecture
 Key Aspects in the Design
+
Vinn,2
+
-
-
RZ
Vinp,2
STG2
+
-
CZ
STG1
+
-
Vinn
+
STG3
+
-
Vinp
Voutp
Voutn
1.- AC-coupling
cmi
2.- CMFF Circuit
IMSE-CNM
ICECS 2010, Athens (Greece)
7
Proposed Low Power PGA Architecture
 Key Aspects in the Design
Vinn,2
-
RZ
+
+
-
AC-coupling
Vinp,2
STG2
+
-
CZ
STG1
+
-
Vinn
+
STG3
+
-
Vinp
Voutp
Voutn
1.- AC-coupling
cmi
2.- CMFF Circuit
IMSE-CNM
ICECS 2010, Athens (Greece)
7
Proposed Low Power PGA Architecture
 Key Aspects in the Design
+
Vinn,2
-
RZ
+
-
AC-coupling
Vinp,2
STG2
+
-
CZ
STG1
+
-
Vinn
+
STG3
+
-
Vinp
Voutp
Voutn
1.- AC-coupling
cmi
2.- CMFF Circuit
 Traditional assumptions for PGAs, such as the convenience of DC-coupling
[1], must be revised in a low-voltage high-dynamic range scenario
S = 2 (Vinpmax - Voutpmin)
≈ 0.28Vpp
VDD/2
0.4
S = 2 (Vinp,outpmax - Vinp,outpmin)
> 0.90Vpp
0.4
DC-coupled
0.2
-0.2
0.2
Voltage Range (V)
IMSE-CNM
-0.2
AC-coupled
Voltage Range (V)
ICECS 2010, Athens (Greece)
7
Proposed Low Power PGA Architecture
 Key Aspects in the Design
+
Vinn,2
-
RZ
+
-
AC-coupling
Vinp,2
STG2
+
-
CZ
STG1
+
-
Vinn
+
STG3
+
-
Vinp
Voutp
Voutn
1.- AC-coupling
cmi
2.- CMFF Circuit
 Traditional assumptions for PGAs, such as the convenience of DC-coupling
[1], must be revised in a low-voltage high-dynamic range scenario
S = 2 (Vinpmax - Voutpmin)
≈ 0.28Vpp
VDD/2
0.4
S = 2 (Vinp,outpmax - Vinp,outpmin)
> 0.90Vpp
0.4
DC-coupled
0.2
-0.2
0.2
Voltage Range (V)
IMSE-CNM
-0.2
AC-coupled
Voltage Range (V)
ICECS 2010, Athens (Greece)
Advantages:




Different cmi and cmo
Greater dynamic range
High linearity without
resistive feedback
Low-power consumption
7
Proposed Low Power PGA Architecture
 Key Aspects in the Design
Vinp,2
+
Vinn,2
+
STG2
+
+
-
-
-
CZ
STG1
-
-
Vinn
+
+
Voutp
Voutn
1.- AC-coupling
cmi
RZ
STG3
-
Vinp
2.- CMFF Circuit
Vbp
BiasP
Voutp
v1
M5
Co
IMSE-CNM
C1
M1
M3
BiasN
(FN +F3 )Ib
2RS
Ro
+
-
F5 Ib
Vbn
Ro
Ib
Voutn
M2
M4
FN Ib
M6
Vbn
Co
ICECS 2010, Athens (Greece)
8
Proposed Low Power PGA Architecture
 Key Aspects in the Design
Vinp,2
+
Vinn,2
+
STG2
+
+
-
-
-
CZ
STG1
-
-
Vinn
+
STG3
Voutp
Voutn
+
-
Vinp
(Vbp,Vbn)
CMFFC
2
cmi
RZ
cmi
VREF
Common-Mode Feed-forward
Circuit (CMFF)
Vbp
BiasP
Voutp
v1
M5
Co
IMSE-CNM
C1
M1
M3
BiasN
(FN +F3 )Ib
2RS
Ro
+
-
F5 Ib
Vbn
Ro
Ib
Voutn
M2
M4
FN Ib
M6
Vbn
Co
ICECS 2010, Athens (Greece)
8
Proposed Low Power PGA Architecture
 Key Aspects in the Design
Vinp,2
+
Vinn,2
+
STG2
+
+
-
-
-
CZ
STG1
-
-
Vinn
+
STG3
Voutp
Voutn
+
-
Vinp
(Vbp,Vbn)
CMFFC
cmi
cmi
Vbp
Voutp
v1
M5
Co
C1
M1
M3
BiasN
(FN +F3 )Ib
2RS
Ro
+
-
F5 Ib
Common-Mode Feed-forward
Circuit (CMFF)
 cmo  Vdd  Ro / RREF  F5VREF
BiasP
Vbn
Ro
Ib
Vbp
Voutn
M2
Vbn
M4
FN Ib
VREF
M6
Vbn
-
RZ
Ib  VREF / RREF
2
Ib
RREF
VREF
+
cmi
Ib
Co
( common for all stage)
IMSE-CNM
ICECS 2010, Athens (Greece)
8
Proposed Low Power PGA Architecture
 Key Aspects in the Design
Vinp,2
+
Vinn,2
+
STG2
+
+
-
-
-
CZ
STG1
-
-
Vinn
+
STG3
Voutp
Voutn
+
-
Vinp
(Vbp,Vbn)
CMFFC
RZ
Ib  VREF / RREF
2
cmi
cmi
 cmo  Vdd  Ro / RREF  F5VREF
VREF
Common-Mode Feed-forward
Circuit (CMFF)
Advantages:
Common-mode feedback circuit can be suppressed since
relatively low impedance is found at the output (Ro is
usually in the order of k).
Vbp

Low-cost low-power solution.
Vbn

Accurately definition of the output common-mode (cmo).

Functionality guaranteed with Corners and Monte-Carlo
simulations.
-

Ib
RREF
VREF
+
cmi
Ib
( common for all stage)
IMSE-CNM
ICECS 2010, Athens (Greece)
8
Contents
 Motivations
 State-of-the-Art in Low Voltage PGAs
 Close-loop vs. Open-loop Architectures
 Proposed PGA Architecture
 Design Methodology
 Common-Mode Feed-forward Circuit (CMFFC)
 Verification:
 Post-layout Simulation Results (3-stage PGA)
 Experimental Results (stage core)
 Conclusions
Verification: 3-stage PGA
 Target Specifications
• Gain = 0 to 72dB in 6-dB steps
• Bandwidth > 15MHz
• ω 2 >> BW
• Power < 2.5mW
• Input referred noise (Gmax) < 15nVrms /Hz
• THD (Gmax) < -36dB
• Vdd = 1.2V  5%
IMSE-CNM
ICECS 2010, Athens (Greece)
9
Verification: 3-stage PGA
 Post-layout Simulation Results (90nm CMOS)
Active Section
65µm
Gain(dB)
60
40
20
0
-20
-40
-60
3-stg PGA
10 3
165µm
G=1
G = 23
G = 43
G = 83
G = 163
10 4
10 5
10 6
Frequency(Hz)
10 7
10 8
10 9
STG Layout
HD 3 (dB)
-30
Decoupling Network
-40
-50
G=1
G=2
G=4
G=8
G = 16
-60
Stage-core
-70
-80
0.2
0.4
110µm
IMSE-CNM
ICECS 2010, Athens (Greece)
0.6
0.8
Vout pp (V)
1
1.2
1.4
9
Verification: 3-stage PGA
 Corners and Monte-Carlo Specifications (Post-layout)
TABLE I.
PGA STATIC AND DYNAMIC SPECIFICATIONS AFTER LAYOUT PARASITIC EXTRACTION:
TT (27ºC, 1.2V), SS(75ºC, 1.08V), FF(0ºC, 1.26V).
AC (Small Signal) @ Co = 2pF
DC
Large Signal @ 2.5MHz with maximum output range
Gain
Corner
G(dB)
f3dB down
(kHz)
f3dB up
(MHz)
Input Noise
(nVrms /Hz)
Power
( mW )
Aout
(Vpp)
G(dB)
HD2
(dB)
HD3
(dB)
THD
(dB)
G=1x1x1
G=16x16x16
G=1x1x1
G=16x16x16
G=1x1x1
G=16x16x16
tt
tt
ff
ff
ss
ss
0.0
72.0
-0.3
73.0
-0.5
71
31.40
28.48
46.91
43.05
21.58
19.48
49.1
20.5
59.5
25.2
39.4
16.7
128.7
10.2
121.9
9.4
131.8
11.4
1.95
1.95
2.58
2.58
1.53
1.53
0.610
1.165
0.602
1.171
0.604
1.134
0.15
71.92
-0.31
72.31
0.55
70.20
-44.67
-83.32
-51.96
-81.04
-36.66
-85.71
-39.53
-42.05
-47.94
-43.78
-32.77
-36.82
-39.23
-42.03
-47.75
-43.76
-32.56
-36.81
TABLE II.
G
Gain
G=8
G=16
mean
7.99
15.98
IMSE-CNM
MONTE-CARLO RESULTS OF THE PGA STAGE FOR THE WORST CASE GAINS
IN TERMS OF OUTPUT REFERRED OFFSET: #200, TT (27ºC, 1.2V).
G(dB)
std
0.034
0.055
mean
18.05
24.07
std
0.037
0.030
f3dB down (Hz)
mean
15.08K
14.66K
std
6.74
11.69
f3dB up (Hz)
mean
26.28M
24.33M
std
123K
128K
Noise (Vrms /Hz)
Output Offset (V)
mean
13.92n
10.11n
mean
22.70μ
264.5μ
ICECS 2010, Athens (Greece)
std
46.83p
22.13p
std
12.90m
18.15m
Power( W)
mean
648.8μ
648.8μ
std
19.03μ
19.03μ
10
Verification: 3-stage PGA
 Corners and Monte-Carlo Specifications (Post-layout)
TABLE I.
PGA STATIC AND DYNAMIC SPECIFICATIONS AFTER LAYOUT PARASITIC EXTRACTION:
TT (27ºC, 1.2V), SS(75ºC, 1.08V), FF(0ºC, 1.26V).
AC (Small Signal) @ Co = 2pF
DC
Large Signal @ 2.5MHz with maximum output range
Gain
Corner
G(dB)
f3dB down
(kHz)
f3dB up
(MHz)
Input Noise
(nVrms /Hz)
Power
( mW )
Aout
(Vpp)
G(dB)
HD2
(dB)
HD3
(dB)
THD
(dB)
G=1x1x1
G=16x16x16
G=1x1x1
G=16x16x16
G=1x1x1
G=16x16x16
tt
tt
ff
ff
ss
ss
0.0
72.0
-0.3
73.0
-0.5
71
31.40
28.48
46.91
43.05
21.58
19.48
49.1
20.5
59.5
25.2
39.4
16.7
128.7
10.2
121.9
9.4
131.8
11.4
1.95
1.95
2.58
2.58
1.53
1.53
0.610
1.165
0.602
1.171
0.604
1.134
0.15
71.92
-0.31
72.31
0.55
70.20
-44.67
-83.32
-51.96
-81.04
-36.66
-85.71
-39.53
-42.05
-47.94
-43.78
-32.77
-36.82
-39.23
-42.03
-47.75
-43.76
-32.56
-36.81
TABLE II.
G
Gain
G=8
G=16
mean
7.99
15.98
std
0.034
0.055
G(dB)
f3dB down (Hz)
f3dB up (Hz)
Noise (Vrms /Hz)
Output Offset (V)
f3dB @ 2pF
mean
std
18.05 (MHz)
0.037
24.07
0.030
Input Noise
mean
std
15.08K
6.74
(nVrms /Hz)
14.66K
11.69
meanPowerstd
26.28M
( mW123K
)
24.33M
128K
Aout std
mean
13.92n
(Vpp) 46.83p
10.11n
22.13p
THD
mean
22.70μ
(dB)
20.5
IMSE-CNM
MONTE-CARLO RESULTS OF THE PGA STAGE FOR THE WORST CASE GAINS
IN TERMS OF OUTPUT REFERRED OFFSET: #200, TT (27ºC, 1.2V).
10.2
1.95
1.165
ICECS 2010, Athens (Greece)
264.5μ
std
12.90m
18.15m
Power( W)
mean
648.8μ
648.8μ
std
19.03μ
19.03μ
-42.03
10
Verification: 3-stage PGA
 Corners and Monte-Carlo Specifications (Post-layout)
TABLE I.
PGA STATIC AND DYNAMIC SPECIFICATIONS AFTER LAYOUT PARASITIC EXTRACTION:
TT (27ºC, 1.2V), SS(75ºC, 1.08V), FF(0ºC, 1.26V).
AC (Small Signal) @ Co = 2pF
DC
Large Signal @ 2.5MHz with maximum output range
Gain
Corner
G(dB)
f3dB down
(kHz)
f3dB up
(MHz)
Input Noise
(nVrms /Hz)
Power
( mW )
Aout
(Vpp)
G(dB)
HD2
(dB)
HD3
(dB)
THD
(dB)
G=1x1x1
G=16x16x16
G=1x1x1
G=16x16x16
G=1x1x1
G=16x16x16
tt
tt
ff
ff
ss
ss
0.0
72.0
-0.3
73.0
-0.5
71
31.40
28.48
46.91
43.05
21.58
19.48
49.1
20.5
59.5
25.2
39.4
16.7
128.7
10.2
121.9
9.4
131.8
11.4
1.95
1.95
2.58
2.58
1.53
1.53
0.610
1.165
0.602
1.171
0.604
1.134
0.15
71.92
-0.31
72.31
0.55
70.20
-44.67
-83.32
-51.96
-81.04
-36.66
-85.71
-39.53
-42.05
-47.94
-43.78
-32.77
-36.82
-39.23
-42.03
-47.75
-43.76
-32.56
-36.81
TABLE II.
G
Gain
G=8
G=16
mean
7.99
15.98
IMSE-CNM
MONTE-CARLO RESULTS OF THE PGA STAGE FOR THE WORST CASE GAINS
IN TERMS OF OUTPUT REFERRED OFFSET: #200, TT (27ºC, 1.2V).
G(dB)
std
0.034
0.055
mean
18.05
24.07
std
0.037
0.030
f3dB down (Hz)
mean
15.08K
14.66K
std
6.74
11.69
f3dB up (Hz)
mean
26.28M
24.33M
std
123K
128K
Noise (Vrms /Hz)
Output Offset (V)
mean
13.92n
10.11n
mean
22.70μ
264.5μ
ICECS 2010, Athens (Greece)
std
46.83p
22.13p
std
12.90m
18.15m
Power( W)
mean
648.8μ
648.8μ
std
19.03μ
19.03μ
10
Verification (not included in the paper)
 Experimental Results (single stage)
Magnitude Bode (dB)
25
20
15
10
5
0
Gain ↑
-5
-10
PCB Test Setup +
HP3589A Analyzer
Simulated: - Measured: ―
-15
Single-to-Differential Input Buffers
& Diff.-to-Single Output Buffers
-20
3
10
4
10
5
6
10
10
Frequency (MHz)
7
10
This work has been partially supported by the
Spanish projects TEC2007-68072 and P09-TIC5386, and by the Catrene European project SR2
2A105 (all co-founded by FEDER).
IMSE-CNM
ICECS 2010, Athens (Greece)
11
Verification (not included in the paper)
 Experimental Results (single stage)
Output Spectrum (dBm @ 50 Ohms)
10
0
THD = -45.0dB
-10
f = 1MHz; A
in
out
= 1.05V ; G = 4
pp
-20
-30
-40
-50
-60
PCB Test Setup +
HP3589A Analyzer
-70
Single-to-Differential Input Buffers
& Diff.-to-Single Output Buffers
-80
0
2
4
6
Frequency (MHz)
8
10
x 10
6
This work has been partially supported by the
Spanish projects TEC2007-68072 and P09-TIC5386, and by the Catrene European project SR2
2A105 (all co-founded by FEDER).
IMSE-CNM
ICECS 2010, Athens (Greece)
11
Contents
 Motivations
 State-of-the-Art in Low Voltage PGAs
 Close-loop vs. Open-loop Architectures
 Proposed PGA Architecture
 Design Methodology
 Common-Mode Feed-forward Circuit (CMFFC)
 Verification:
 Post-layout Simulation Results (3-stage PGA)
 Experimental Results (stage core)
 Conclusions
Conclusions
 In this paper, we have shown that open-loop topologies with gain
boosting present an optimum trade-off between power consumption
and linearity for ZigBee applications.
 We have proposed a design methodology for low-voltage PGAs with
resistive degeneration.
 The developed design flow is shown with a 1.2V 72dB 1.95mW PGA
implementation in a TSMC 90nm CMOS process.
 Power optimization is improved thanks to the use of a front-end
capacitive decoupling network and a common-mode feed-forward
circuit shared between all stages.
 The front-end capacitive decoupling network also improves the PGA
dynamic range. Actually, a THD < -42dB is achieved for a 1.2Vpp output
excursion, G = {4,8,16}.
IMSE-CNM
ICECS 2010, Athens (Greece)
12
POWER OPTIMIZATION OF CMOS PROGRAMMABLE
GAIN AMPLIFIERS WITH HIGH DYNAMIC RANGE
AND COMMON-MODE FEED-FORWARD CIRCUIT
Thank you very much for your attendance
Questions?
A. J. Ginés, Email: gines@imse-cnm.csic.es
Instituto de Microelectrónica de Sevilla (CNM-CSIC)
University of Seville (Spain)