Department of Engineering Science
ES210, Logic Design
Introduction to Verilog
http://www.sonoma.edu/users/k/kujoory
References
• "Digital Design," Morris Mano and Michael Ciletti, 5th ed, Pearson, 2012.
• Dr. Jack Ou’s slides, ES210, Spring 2014
• Dr. Jack Ou's Cadence Tutorials
http://www.sonoma.edu/esee/courses/jack_ou/cadence/
• MobaXterm http://www.sonoma.edu/engineering/resources/remote.html
• http://www.referencedesigner.com/tutorials/verilog/verilog_01.php
• http://www.asic-world.com/verilog/verilog_one_day1.html#Introduction
• http://www.ece.umd.edu/class/enee359a/verilog_tutorial.pdf
Ali Kujoory
6/30/2016
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1
Topics Covered
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What is Verilog
Verilog HDL Syntax and Semantics
Installation and Environment
Verilog File Examples
Verilog Test Bench File Examples
Installing MobaXterm
Running the Simulation of Verilog
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What is Verilog
• Verilog is a Hardware
Description Language (HDL)
• HDL is a programming
language that uses codes to
describe & model digital
circuits
– VHDL is another example of HDL
• Verilog allows to simulate
digital circuits and show the
output vs input waveforms
before building them
• Digital circuits can be
complex when making
integrated circuits
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Verilog HDL Syntax and Semantics
• White space contain characters that are ignored:
blanks, tabs, newlines, and form feeds
• Lower case letters are unique from upper case letters
• All Verilog keywords are lower case
• Identifiers are names used to give an object, such as a register or a
function or a module, a name so that it can be referenced from other
places in a description.
– Identifiers must begin with an alphabetic character or the underscore
character (a−z A−Z _ )
– Identifiers may contain alphabetic characters, numeric characters, the
underscore, and the dollar sign (a−z A−Z 0−9 _ $ )
– Identifiers can be up to 1024 characters long.
• Examples of legal identifiers
– data_input mu
– clk_input my$clk
– i386 A
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Example of Bad and Good Codes
Bad Code:
1. Module addbit(a,b,ci,sum,co);
2. input a,b,ci;output sum co;
3. wire a,b,ci,sum,co;endmodule
Ali Kujoory
6/30/2016
Good Code
1. module addbit (
2. a,
3. b,
4. ci, // Carry In
5. sum,
6. co); // Carry Out
7. input a;
8. input b;
9. input ci;
10. output sum;
11. output co;
12. wire a;
13. wire b;
14. wire ci;
15. wire sum;
16. wire co;
17. 18. endmodule
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Sample Program 1 “hello_world”
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
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13.
14.
//−−−−−−−−−−−−−−−−−−−−−−−−−−
// This is my first Verilog Program
// Design Name: hello_world
// File Name: hello_world.v
// Function: This program prints 'hello world’
• Green words = comments
// Coder: Deepak
• Blue words = reserved
//−−−−−−−−−−−−−−−−−−−−−−−−−−
keywords
• Lines 8 & 14 start & end
module hello_world ;
module
//
• Lines 10 & 13 contains initial
block that begin & end the
initial begin
block.
$display ( "Hello World by Deepak" );
• The module gets executed at
time=0 (0ms)
#10 $finish;
end
Output of the program is:
endmodule // End of Module hello_world
Hello World by Deepak
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Examples of Comments
• Single line comments
begin with token // and
end with a carriage return
• Multi Line comments
– begin with the token /* and
– end with the token */
• Number spec notation:
<size>’<base><number>,
e.g.,
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
/* This is a
Multi line comment
example */
module addbit (
a,
b,
ci,
sum,
co);
a=4’b1010
Start with /*
End with */
4’b1010 if a 4-bit binary value
16’h6cda is a 16 bit hex
number
8’d40 decimal value 40
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6/30/2016
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Examples of Comments
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
// Input Ports Single line comment
input a;
input b;
input ci;
// Output ports
output sum;
output co;
// Data Types
wire a;
wire b;
wire ci;
wire sum;
wire co;
//
endmodule
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6/30/2016
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8
Set Up the Environment
• Assuming that you want to have a library for es210 in which there is
a sandbox for your Verilog files and simulation files.
• Open a terminal.
propmpt
[kujoory@cadence ~]$ mkdir es210
[kujoory@cadence ~]$ cd es210
[kujoory@cadence ~]$ mkdir verilogSandBox
[kujoory@cadence ~]$ cd verilogSandBox
• So the Verilog file fig3p37.v can reside in
[kujoory@cadence ~]$ es210/verilogSandBox/fig3p37.v
Cadence Design Systems is an American electronic design automation
(EDA) software and engineering services company that produces software
and hardware for designing integrated circuits, systems on chips (SoCs) &
printed circuit boards. One of their products is Verilog-AMS for circuit
simulation, and FPGA designs. https://en.wikipedia.org/wiki/Cadence_Design_Systems
Ali Kujoory
6/30/2016
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9
Your First Verilog Program
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
fig3p37 is the name of the module
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
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module....endmodule
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
An example of a Verilog Design program
fig3p37 is the name of the module
Always start the verilog program
with the keyword pair module…endmodule
The keyword module must always be
terminated by the keyword endmodule.
endmodule
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6/30/2016
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Keywords
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
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Semicolon
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
Each Statement end with a
semicolon.
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
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wire
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
Internal connection is declared
with the keyword wire.
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
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Primitive Gates
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and, not, or are primitive gates.
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
G1 is an instance of the and gate.
The output is listed first.
The inputs can be listed in any order.
endmodule
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“assign” keyword
• “assign” keyword is used to assign a value to the output
• It is followed by a Boolean expression.
• To distinguish arithmetic operators from logical operators,
– Verilog uses symbols “&”, “/”, and “~” for AND, OR, and NOT, respectively,
e.g.,
Logical statement
Equivalent statement with “assign”
not (Y, X);
assign Y = ~X;
and (C, A, B);
assign C = A & B;
or (F, D, E);
assign F = D | E;
assign D = (A & B)|~C;
assign D = (A & B)|~C;
assign b[0] = a[0],
b[1] = a[1],
b[2] = a[2],
b[3] = a[3];
See Examples 4.3, 4.4, and 4.5 in Mano textbook.
Ali Kujoory
6/30/2016
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Your First Verilog Program
Without assign
With assign
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
Ali Kujoory
6/30/2016
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
assign w1 = (A & B);
assign E = ~C;
assign D = (w1 | E);
endmodule
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Table 4.10
Some Verilog HDL Operators
Equal by value,
e.g., 111=111
=
for logical assign
Complete list in Table 8.1 &
https://www.utdallas.edu/~akshay.sridharan/index_files/Page5212.htm
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6/30/2016
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18
Set Up the Testbench
• In addition to Verilog design program, one also needs a test bench program
to define the instances of inputs that we apply to the circuit to get the outputs
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Test Bench Module
//fig3p37_tb.v (test bench) file
`timescale 1 ms / 1 us
`include "fig3p37.v"
“//” indicates a comment line
module fig3p37_tb;
wire D,E;
reg A,B,C;
fig3p37 M1(A,B,C,D,E); //Instance name
Initial
begin
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
end
initial #400 $finish;
endmodule
Ali Kujoory
6/30/2016
Fig3p37_tb is the module name
M1 is the instance of the module, required.
Fig3p37 is the main module name (below)
//fig3p37.v is Verilog Design file
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
endmodule
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Test Bench Module
//fig3p37_tb.v (test bench) file
`timescale 1 ms / 1 us
`include "fig3p37.v"
(`) is a back apostrophe before
timescale and include
module fig3p37_tb;
wire D,E;
reg A,B,C;
fig3p37 M1(A,B,C,D,E); //Instance name
required
Initial
begin
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
end
initial #400 $finish;
The first number specifies the unit of
measurement for delays. The second
number specifies the precision for
which delays are rounded off
In Test Bench program the circuit
outputs are declared with keyword
wire and inputs with keyword reg.
The initial keyword is used with a set
of statements that begin executing
when the simulation is initialized.
begin….end
The statements are executed in
sequence from top to bottom
endmodule
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6/30/2016
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Test Bench Module
//fig3p37_tb.v (test bench) file
`timescale 1 ms / 1 us
`include "fig3p37.v"
module fig3p37_tb;
wire D,E;
reg A,B,C;
fig3p37 M1(A,B,C,D,E); //Instance name
required
Initial
begin
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
end
initial #400 $finish;
# specifies the delay in the number of time units
Format for variable: size/’/base/value
e.g., A is one binary bit with a value of 1
# 400 specifies the duration for the display
endmodule
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MobaXterm Installation
You should have an account on Cadence/Verilog server by emailing
Mr. Shahram Marivani (marivani@sonoma.edu)
• Go to http://www.sonoma.edu/engineering/ and click on Resources
• Click on Remote Server Access
• Follow the instruction of MobaXterm for Windows or MAC computer
– MobaXterm opens a Terminal page for Windows7 or Mac, as in Linux
• Click on MobaXterm
– You want to install this application on a flash memory so that you
can use it on the lab or any computer including your laptop
– MobaXterm is a way to initiate a secure shell (ssh) session to
communicate with the server.
• Insert your flash memory into the Lab computer or your laptop
• From the “Home Edition” options select “Portable edition” and click to
download and save the MobaXterm_v8 zip file on the flash memory
• Select MobaXterm_Personal_v8.6.exe and RUN it
• MobaXterm window opens and you can follow the instruction.
(130.157.3.118 is the IP address of the Cadence Server.)
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MobaXterm Page
• For MAC, you may need to download “X11 for MAC” first and follow the
instruction.
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6/30/2016
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Terminal Display – Example 1
• On the Terminal page, make a folder for es210
• In es210 folder make a folder called verilogsandbox
• Use a Linux editor such as vi to make a verilog.v design file that describes the
desired digital circuit
• For the fig3p37 circuit shown, then, the location of the Verilog design file is
es210/verilogsandvox/fig3p37.v
• We need also to make a test bench file that defines the desired inputs to apply to the
circuit as es210/verilogsandvox/fig3p37_tb.v
• The figure shows a typical Terminal display. Next slide shows the Verilog files
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Verilog Files for – Example 1 on fig3p37
//fig3p37.v is the design file
module fig3p37 (A,B,C,D,E);
output D,E;
input A,B,C;
wire w1;
and G1(w1,A,B);
not G2(E,C);
or G3(D,w1,E);
//fig3p37_tb.v is the test bench file
`timescale 1 ms / 1 us
`include "fig3p37.v"
module fig3p37_tb;
wire D,E;
reg A,B,C;
fig3p37 M1(A,B,C,D,E); //Instance name
required
Initial
begin
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
end
initial #400 $finish;
endmodule
endmodule
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6/30/2016
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26
Verilog for Simulation – Example 1
• Compiling and running the Verilog file can simulate the circuit
• Verilog displays the digital output waveforms for the input data as
specified in the test bench file (fig3p37_tb.v)
• TYPE verilog fig3p37_tb.v and ENTER to compile the file
– fig3p37_tb.v and fig3p37.v files will first be checked for syntax errors, and
– will be compiled only if there are no errors
• This file is processed before the digital waveforms are displayed
(next slides)
Note: There are two ways to compile the files:
1. Make two separate files (preferred):
• fig3p37.v and
• one that starts with command `include fig3p37.v followed by the fig3p37_tb.v
module, in which case you need to run the fig3p37_tb.v file (see next slide), or
2. Make one composite file that includes fig3p37_tb.v module followed by the
fig3p37.v module
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Verilog Modules - – Example 1
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The Screen
after
Compiling
fig3p37_tb.v
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29
Windows After Running fig3p37_tb.v File – Example 1
Two tabs open
1. Select “Simulation” & click
on “Reinvoke Simulator”
2. Click on “Yes” on the resulting
Reinvoke tab & go to the lower
screen
3. Click on “+” sign to display
the subfolders & click on the “+” sign
of MI. You will see all the input/output
variables in the left window.
4. Select all these variables.
5. Go to this icon to “Send selected
objects to the waveform”. After a while
the waveforms for all variables are
displayed in a new screen
6. Change time in “Time A” to 100 ms.
Note that you need to change ussec
scale to msec scale on the right
7. Change time in “Search Times Value”
to 0-400 ms. Next slide shows the
Waveforms.
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30
Simulated Waveforms – Example 1
8. Click on Simulation & hit
“Run” for the waveform to
Build the display
9. You can move the vertical
line indicator on the
waveforms to left & right by
clicking on these arrows
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6/30/2016
A=B=C
=
0
1
D
0
1
E
1
0
w1
1
1
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31
Example 2: Simulate the Same Circuit with Different Inputs
//Verilog HDL for fig3p37 with different inputs
`timescale 1 ms / 1 us
`include "fig3p37.v"
module fig3p37_tb;
wire D,E;
reg A,B,C;
fig3p37 M1(A,B,C,D,E); //Instance name
initial
begin
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
#50
A =1'b0; B =1'b0; C =1'b0;
#100
A =1'b1; B =1'b1; C =1'b1;
end
initial #400 $finish;
endmodule
Ali Kujoory
6/30/2016
//module fig3p37 (A,B,C,D,E);
//output D,E;
//input A,B,C;
//wire w1;
//and G1(w1,A,B);
//not G2(E,C);
//or G3(D,w1,E);
//endmodule
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32
Verilog Modules - Example 2
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Input and Output Waveforms for Example 2
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