1. The Test of the GOL chip.
2. First test on the SoS driver chip and the submission of a dedicated test chip for radiation tests.
3. Test results of the GSE laser and a 10 GHz
VCSEL .
The SMU group:
Wickham Chen, Ping Gui, Andy T. Liu, Ryszard Stroynowski,
Annie C. Xiang, John C. Yang, PeiQing Zhu,, Juheng Zhang,
Jingbo Ye
J.Ye / SMU April 11, 2020 GOL + SoS

G-Link
1.25 Gbps
TLK2501
2.5 Gbps
GOL
1.6 Gbps
Rad-hard
Bi-polar, 2.5 W
Rad-soft
360 mW
Rad-hard by design,
400 mW LD driver included
23.2×17.2mm
2 ×2.7mm
Price: $50/pcs
J.Ye / SMU April 11, 2020
12.2×12.2mm
2 ×1mm 13×13mm 2 ×1.7mm
Price: $15/pcs
GOL + SoS


 Transmission speed
 Fast: 1.6Gbps, 32 bit@40MHz
 Slow: 0.8Gbps, 16 bit@40MHz
 Encoding scheme
 CIMT (ex: HDMP-1024)
 8B/10B (ex: TLK2501)
 Program interface
 I2C
 JTAG
 Driver
Package: 144 pin fpBGA with 1 mm solder-ball pitch. Dimensions: 13 mm sides, 1.68 mm tall.
 Internal laser driver (bias: 1 mA to 55 mA in 0.4 mA steps)
 50ohm line driver, minimum 780 mV differential.
 Good for VCSEL and Edge Emitter.
J.Ye / SMU April 11, 2020 GOL + SoS

J.Ye / SMU April 11, 2020 GOL + SoS

[ Ref. GOL CERN website ]
1. Total dose effect: 10Mrad (x-ray, 10 KeV peak) at a dose rate of 10.06 Krad(SiO increase after the irradiation.
)/min. No current
2. SEU: 60 MeV proton, fluence of 3 × 10 12 p/cm 2 at a flux of 3 × 10 8 p/cm 2  sec. No SEU was observed.
Requirements: 10 to 100 Mrad and 10 15 to 10 16 p/cm 2 fluence.
3. BER tests in lab: better than 1.3
× 10 -14 .
4. Power consumption: 400 mW.
J.Ye / SMU April 11, 2020 GOL + SoS

We plan:
 A complete chip characterizing according to the IEEE Gigabit
Ethernet standard. This includes rise/fall times, eye mask test, jitter studies (DJ and RJ at all 4 testing points of the link system, jitter transfer of the GOL), optical power margin
(again in the link system). We did this for the G-Link for the
LAr optical link. Agilent didn’t provide it in the data sheet.
 The PLL lock range.
 Probe the total dose limit to see if it reaches 100 Mrad.
Measure SEUs at different flux levels, using 200 MeV proton beams.
 Gain experience of using this chip, should it be suitable to inner detector upgrade.
J.Ye / SMU April 11, 2020 GOL + SoS

Pattern/clock generator with jitter input
TP1
TP2
PC interface
J.Ye / SMU April 11, 2020 GOL + SoS
TP4
TP3

Control Room 37 m away
RS232
GPIB
2 m away from the beam
Freq. Counter
Prog. V. Source
GPIB
Picoammeter
PC
Switch Board
Flux
USB DIO
Card
FPGA Board
In the beam
Test chip Carrier
Board 1
Test Chip
Carrier Board 2
GOL Board 1
This design is still in progress and is changing on daily basis.
J.Ye / SMU April 11, 2020
TTL

LVDS TLK Rx
TTL

LVDS
GPIB
DMM
TLK Rx
Power Supply
Board
GOL + SoS
GOL Board 2

10/1/05
11/1/05
12/1/05
1/15/05
2/15/06
3/1/06
3/31/06
System design 1 month
We are here
Schematic capture 1 month
PCB layout 1 month FPGA code
1.5 month
Labview code
1 month
Board assembly 3 wk
PCB Debug 3 wk
Lab Test 1 month
Irradiation Tests
J.Ye / SMU April 11, 2020 GOL + SoS

 There is no guarantee that GOL can withstand ~10 times more radiation than what has been tested.
 We do not know if more bandwidth would be needed.
 We are designing a Link-on-Chip ASIC for the LAr upgrade. This chip may be used for the ID upgrade as well.
 This project has just been started. Here I report on the first irradiation test and the actions we take based on the preliminary result.
J.Ye / SMU April 11, 2020 GOL + SoS

 A laser driver chip based on 0.5  m SoS technology was irradiated at MGH (230 MeV proton).
 Total dose: 116 Mrad.
 Error free at 1.5 krad/sec and up to 17 Mrad. LAr upgrade okay.
 Observed current increase at very high dose rate.
J.Ye / SMU April 11, 2020 GOL + SoS

 In CMOS layout, the technique to combat the leakage current is the enclosed layout transistor
(ELT) and the guard-ring around the transistors. In
SoS, only ELT is needed.
 We will use the new 0.25  m SoS technology for the
LOC design. In order to probe the total dose limit, to check ELT on SoS, and to check layout parameters on design blocks like the PLL, we submitted a dedicated test chip mid October.
 The test of this chip is in preparation (3 slides back) and the irradiation test is aimed for April
2006.
J.Ye / SMU April 11, 2020 GOL + SoS

1) 12X9 transistor array, ELT and
“standard” layout, NMOS and
PMOS with different size.Test layout techniques and rad-hard limit.
2) 4 ring oscillators (ELT, “std”, different transistor size). Test
SEUs.
3) 5 shift Registers (… + various resistors, majority voting).
Test SEUs.
4) 6 individual gates (ELT and
“std”).
5) PLL parts:
- Div16
- VCO
- PFD
4 Ring oscillators
PLL parts
5 Shift registers
6 Individual
Gates
12 X 8
Transistor
Array
Many parameters will be measured in lab and in irradiation. The results will guide us in designing of the LOC chip.
J.Ye / SMU April 11, 2020 GOL + SoS

Majority vote circuitry
CMOS Ring
Oscillators
Differential
Ring
Oscillator
Resistors
Shift
Registers
Individual gates
PLL cells
Transistors array
J.Ye / SMU April 11, 2020 GOL + SoS

 We also started to look for laser diodes. We tested two surface emitting lasers. One long wavelength and can couple to single mode fiber, one VCSEL. The preliminary results are briefly reported here.
J.Ye / SMU April 11, 2020 GOL + SoS

We exposed 12 Grating-outcoupled Surface-Emitting laser (1310 nm) up to 22.3 Mrad at IUCF with 200 MeV proton. The lasers that received 11.4 Mrad total dose still pass 2.5 Gbps eye mask test.
1.8 Mrad
Pass.
J.Ye / SMU April 11, 2020
11.4 Mrad
Pass.
GOL + SoS
5.9 Mrad
Pass.
22.3 Mrad
Fail.

3
2.5
2
1.5
1
0.5
0
0
Preliminary test results on the ULM 10 GHz VCSEL:
We irradiated 2 ULM 10 GHz VCSELs at MGH. The VCSEL were biased during irradiation. The total dose received is 116 Mrad. All
DC parameters are still within spec after the irradiation.
V-I curve
5 10 current (mA)
15
2.5
2
1.5
1
0.5
0
0
L-I curve
5 current (mA)
10 rad1 rad2 nonrad3 nonrad4 nonrad5 nonrad6 nonrad7 nonrad8
15
Eye diagram and other AC parameters will be measured soon.
J.Ye / SMU April 11, 2020 GOL + SoS

 The GOL test program has been started and is on track.
 We designed and submitted a dedicated SoS test chip to check out layout techniques and measure related parameters. The lab and irradiation tests of this chip is in preparation.
 We have tested the GSE lasers and find them useful in 11 Mrad environment. The GSE lasers can couple to single mode fibers. The results are accepted for publishing by Photonics Technology
Letters (PLT).
 We have identified a 10 GHz VCSLE and preliminary test results show potential in use with 100 Mrad.
More tests are on going and more VCSELs will be tested.
J.Ye / SMU April 11, 2020 GOL + SoS