inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture 19
CPU Design: The Single-Cycle II & Control
2010-07-22
Instructor Paul Pearce
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CS61C L19 CPU Design: The Single-Cycle II & Control (1)
Pearce, Summer 2010 © UCB
How to Design a Processor: step-by-step
1. Analyze instruction set architecture (ISA) =>
datapath requirements
• meaning of each instruction is given by the register
transfers
• datapath must include storage element for ISA registers
• datapath must support each register transfer
2. Select set of datapath components and establish
clocking methodology
3. Assemble datapath meeting requirements
4. Analyze implementation of each instruction to
determine setting of control points that effects the
register transfer.
5. Assemble the control logic
CS61C L19 CPU Design: The Single-Cycle II & Control (2)
Pearce, Summer 2010 © UCB
Clocking Methodology
Clk
.
.
.
.
.
.
.
.
.
.
.
.
• Storage elements clocked by same edge
• Being physical devices, flip-flops (FF) and
combinational logic have some delays
• Gates: delay from input change to output change
• Signals at FF D input must be stable before active clock
edge to allow signal to travel within the FF (set-up time),
and we have the usual clock-to-Q delay
• “Critical path” (longest path through logic)
determines length of clock period
CS61C L19 CPU Design: The Single-Cycle II & Control (3)
Pearce, Summer 2010 © UCB
Register-Register Timing: One complete cycle
Clk
PC
Old Value
New Value
Rs, Rt, Rd, etc
Old Value
ALUctr
Old Value
RegWr
Old Value
busA, B
Old Value
busW
Old Value
Instruction Memory Access Time
New Value
Delay through Control Logic
New Value
New Value
Register File Access Time
New Value
ALU Delay
New Value
ALUctr
RegWr Rd Rs Rt
5
5
Rw Ra Rb
busA
RegFile
busB
clk
CS61C L19 CPU Design: The Single-Cycle II & Control (4)
Register Write
Occurs Here
32
ALU
busW
5
32
32
Pearce, Summer 2010 © UCB
3c: Logical Operations with Immediate
• R[rt] = R[rs] op ZeroExt[imm16]
31
26
21
op
31 6 bits
rs
16
rt
5 bits
0
immediate
5 bits 16 15
16 bits
0
immediate
0000000000000000
16 bits
16 bits
But we’re writing to Rt register??
ALUctr
RegWr Rd Rs Rt
5
5
Rw Ra Rb
busA
RegFile
busB
clk
CS61C L19 CPU Design: The Single-Cycle II & Control (5)
32
ALU
busW
5
32
32
Pearce, Summer 2010 © UCB
3c: Logical Operations with Immediate
• R[rt] = R[rs] op ZeroExt[imm16] ]
31
26
21
op
rs
31 6 bits
RegDst
RegWr
Rs Rt
5
16 bits
0
immediate
16 bits
ALUctr
5
Rw Ra Rb
busA
RegFile
busB
32
16
ZeroExt
clk
imm16
immediate
5 bits 16 15
32
0
ALU
32
0
What about Rt register read??
0
5
5 bits
rt
0000000000000000
16 bits
Rd Rt
1
16
32
1
32
ALUSrc
• Already defined 32-bit MUX; Zero Ext?
CS61C L19 CPU Design: The Single-Cycle II & Control (6)
Pearce, Summer 2010 © UCB
3d: Load Operations
• R[rt] = Mem[R[rs] + SignExt[imm16]]
Example: lw rt,rs,imm16
31
26
21
op
16
rs
6 bits
0
rt
5 bits
immediate
5 bits
16 bits
RegDst Rd Rt
1
RegWr
5
Rs Rt
5
ALUctr
5
Rw Ra Rb
busA
RegFile
busB
32
imm16
16
ZeroExt
clk
CS61C L19 CPU Design: The Single-Cycle II & Control (7)
32
0
ALU
32
0
32
1
32
ALUSrc
Pearce, Summer 2010 © UCB
3d: Load Operations
• R[rt] = Mem[R[rs] + SignExt[imm16]]
Example: lw rt,rs,imm16
31
26
21
op
16
rs
6 bits
0
rt
5 bits
immediate
5 bits
16 bits
ALUctr
RegDst Rd Rt
1
RegWr
0
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
Extender
clk
ExtOp
CS61C L19 CPU Design: The Single-Cycle II & Control (8)
32
0
1
32
ALU
busW
MemtoReg
MemWr
? 32
Data In
ALUSrc clk
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
3e: Store Operations
• Mem[ R[rs] + SignExt[imm16] ] = R[rt]
Ex.: sw rt, rs, imm16
31
op
26
21
16
rs
5 bits
6 bits
rt
5 bits
immediate
16 bits
ALUctr
RegDst Rd Rt
1
RegWr
0
5
5
5
busA
busB
32
imm16
16
Extender
clk
ExtOp
CS61C L19 CPU Design: The Single-Cycle II & Control (9)
32
0
ALU
RegFile
32
MemtoReg
MemWr
Rs Rt
Rw Ra Rb
busW
0
32
0
32 WrEn Adr
1
32
Data In
ALUSrc clk
Data
Memory
1
Pearce, Summer 2010 © UCB
3e: Store Operations
• Mem[ R[rs] + SignExt[imm16] ] = R[rt]
Ex.: sw rt, rs, imm16
31
op
26
21
16
rs
5 bits
6 bits
rt
5 bits
immediate
16 bits
ALUctr
RegDst Rd Rt
1
RegWr
0
5
5
5
busA
busB
32
imm16
16
Extender
clk
ExtOp
CS61C L19 CPU Design: The Single-Cycle II & Control (10)
32
0
ALU
RegFile
32
MemtoReg
MemWr
Rs Rt
Rw Ra Rb
busW
0
32
0
32 WrEn Adr
1
32
Data In
ALUSrc clk
Data
Memory
1
Pearce, Summer 2010 © UCB
3f: The Branch Instruction
31
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
immediate
16 bits
0
beq rs, rt, imm16
• mem[PC] Fetch the instruction from memory
• Zero = R[rs] - R[rt] Calculate branch condition
• if (Zero) Calculate the next instruction’s address
 PC = PC + 4 + ( SignExt(imm16) x 4 )
else
 PC = PC + 4
CS61C L19 CPU Design: The Single-Cycle II & Control (11)
Pearce, Summer 2010 © UCB
Datapath for Branch Operations
• beq rs, rt, imm16
Datapath generates condition (zero)
31
op
26
6 bits
21
rs
5 bits
16
rt
5 bits
0
immediate
16 bits
Inst Address
Zero
nPC_sel
Adder
4
00
clk
busW
5
ALUctr
Rs Rt
5
5
Rw Ra Rb
busA
RegFile
busB
clk
32
z
ALU
PC
Mux
Adder
PC Ext
imm16
RegWr
32
32
Already have mux, adder, need special sign
extender for PC, need equal compare (sub?)
CS61C L17 Combinational Logic Blocks and Intro to CPU Design (12)
Pearce, Summer 2010 © UCB
Putting it All Together:A Single Cycle Datapath
RegDst
32
0
5
5
5
Rw Ra Rb
RegFile
busA
busB
32
16
Extender
imm16
MemtoReg
MemWr
Rs Rt
clk
clk
ALUctr
Zero
32
z
ALU
busW
PC
PC Ext
Adder
Mux
00
RegWr
Adder
4
Rt Rd Imm16
Rd Rt
1
Instruction<31:0>
<0:15>
nPC_sel
Rs
<11:15>
Adr
<16:20>
<21:25>
Inst
Memory
0
32
1
32
Data In
clk
32
0
WrEn Adr
Data
Memory
1
imm16
ExtOp
CS61C L17 Combinational Logic Blocks and Intro to CPU Design (13)
ALUSrc
Pearce, Summer 2010 © UCB
An Abstract View of the Implementation
Ideal
Instruction
Memory
PC
clk
32
Instruction
Rd Rs Rt
5 5
5
Rw Ra Rb
Register
File
Control Signals Conditions
A
32
ALU
Next Address
Instruction
Address
Control
B
clk
32
32
Data
Addr
Ideal
Data
Memory
Data
Out
Data
In clk
Datapath
CS61C L19 CPU Design: The Single-Cycle II & Control (14)
Pearce, Summer 2010 © UCB
An Abstract View of the Critical Path
Ideal
Instruction
Memory
PC
clk
32
Instruction
Rd Rs Rt
5 5
5
Rw Ra Rb
Register
File
(Assumes a fast controller)
A
32
ALU
Next Address
Instruction
Address
Critical Path (Load Instruction) =
Delay clock through PC (FFs) +
Instruction Memory’s Access Time +
Register File’s Access Time, +
ALU to Perform a 32-bit Add +
Data Memory Access Time +
Stable Time for Register File Write
B
clk
CS61C L19 CPU Design: The Single-Cycle II & Control (15)
32
32
Data
Addr
Ideal
Data
Memory
Data
In clk
Pearce, Summer 2010 © UCB
Administrivia
• HW 7 due Saturday
• Specification update now online. Be sure to
check it out. The changes are designed to
make integration with project 2 easier. They
are very minor.
• Project 2 online now!
• Reminder: Midterm regrades due Monday.
• Paul will be gone on Monday. Noah will
be giving the lecture.
• Paul will have OH on Monday (barring flight
delays)
• Be prepared for a kinetic learning activity
CS61C L19 CPU Design: The Single-Cycle II & Control (16)
Pearce, Summer 2010 © UCB
Review: A Single Cycle Datapath
Instruction<31:0>
Rs Rt Rd Imm16
ALUctr
MemtoReg
Rd Rt
1
RegWr
0
5
Rs Rt
5
busB
32
Extender
clk
imm16
busA
16
ExtOp
CS61C L19 CPU Design: The Single-Cycle II & Control (17)
32
MemWr
Z
ALU
RegFile
32
zero
5
Rw Ra Rb
busW
<0:15>
RegDst
<11:15>
clk
<16:20>
instr
fetch
unit
nPC_sel
<21:25>
• We have
everything but
the values of
control signals
0
32
1
32
Data In
clk
32
0
WrEn Adr
Data
Memory
1
ALUSrc
Pearce, Summer 2010 © UCB
Recap: Meaning of the Control Signals
“+4” 0  PC <– PC + 4
“br” 1  PC <– PC + 4 +
“n”=next
{SignExt(Im16) , 00 }
• Later in lecture: higher-level connection
between mux and branch condition
• nPC_sel:
Inst Address
0
00
nPC_sel
Adder
4
PC
Mux
Adder
PC Ext
1
clk
imm16
CS61C L19 CPU Design: The Single-Cycle II & Control (18)
Pearce, Summer 2010 © UCB
Recap: Meaning of the Control Signals
°MemWr: 1  write memory
°MemtoReg: 0  alu; 1  mem
°RegDst: 0  rt; 1  rd
°RegWr: 1  write register
• ExtOp: zero, sign
• ALUsrc: 0  reg;
1  imm
• ALUctr: ADD, SUB, OR
ALUctr
RegDst Rd Rt
1
RegWr
0
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
Extender
clk
ExtOp
CS61C L19 CPU Design: The Single-Cycle II & Control (19)
32
0
ALU
busW
MemtoReg
MemWr
32
0
32 WrEn Adr
1
32
Data In
ALUSrc clk
Data
Memory
1
Pearce, Summer 2010 © UCB
RTL: The Add Instruction
31
26
op
6 bits
21
rs
5 bits
16
rt
5 bits
11
6
0
rd
shamt
funct
5 bits
5 bits
6 bits
add rd, rs, rt
• MEM[PC]
Fetch the instruction
from memory
• R[rd] = R[rs] + R[rt] The actual operation
• PC = PC + 4
Calculate the next
instruction’s address
CS61C L19 CPU Design: The Single-Cycle II & Control (20)
Pearce, Summer 2010 © UCB
Instruction Fetch Unit at the Beginning of Add
• Fetch the instruction from Instruction
memory: Instruction = MEM[PC]
• same for
all instructions
Inst
Memory
nPC_sel
Inst Address
00
Adder
4
Instruction<31:0>
PC
Mux
Adder
PC Ext
clk
imm16
CS61C L19 CPU Design: The Single-Cycle II & Control (21)
Pearce, Summer 2010 © UCB
The Single Cycle Datapath during Add
31
26
op
21
16
rs
11
rt
rd
6
shamt
R[rd] = R[rs] + R[rt]
RegWr=1
Rs Rt
5
5
5
busA
Rw Ra Rb
RegFile
32
busB
32
imm16
16
Extender
clk
ExtOp=x
CS61C L19 CPU Design: The Single-Cycle II & Control (22)
Rs Rt Rd Imm16
zero ALUctr=ADD
MemtoReg=ALU
MemWr=0
32
Z
ALU
busW
0
32
1
32
<0:15>
0
<11:15>
1
Instruction<31:0>
<16:20>
Rd Rt
funct
<21:25>
instr
fetch
unit
nPC_sel=+4
RegDst=rd
clk
0
Data In
clk
ALUSrc=reg
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
Instruction Fetch Unit at the End of Add
• PC = PC + 4
• This is the same for all instructions except:
Branch and Jump
Inst
Memory
nPC_sel=+4 Inst Address
00
Adder
4
PC
Mux
Adder
PC Ext
clk
imm16
CS61C L19 CPU Design: The Single-Cycle II & Control (23)
Pearce, Summer 2010 © UCB
Single Cycle Datapath during Or Immediate?
31
26
21
op
16
rs
0
rt
immediate
• R[rt] = R[rs] OR ZeroExt[Imm16]
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
ExtOp=
Extender
clk
Rs Rt Rd Imm16
zero ALUctr=
MemtoReg=
MemWr=
32
Z
ALU
busW
0
32
1
32
Data In
ALUSrc=
CS61C L19 CPU Design: The Single-Cycle II & Control (24)
<0:15>
RegWr=
0
<11:15>
1
clk
<16:20>
Rd Rt
Instruction<31:0>
instr
fetch
unit
<21:25>
nPC_sel=
RegDst=
clk
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
Single Cycle Datapath during Or Immediate?
31
26
21
op
16
rs
0
rt
immediate
• R[rt] = R[rs] OR ZeroExt[Imm16]
RegWr=1
5
Rs Rt
5
5
busA
Rw Ra Rb
RegFile
32
32
16
Extender
clk
imm16
busB
ExtOp=zero
Rs Rt Rd Imm16
zero ALUctr=OR
MemtoReg=alu
MemWr=0
32
Z
ALU
busW
0
32
1
32
Data In
clk
ALUSrc=imm
CS61C L19 CPU Design: The Single-Cycle II & Control (25)
<0:15>
0
<11:15>
1
<16:20>
Rd Rt
Instruction<31:0>
<21:25>
instr
fetch
unit
nPC_sel=+4
RegDst=rt
clk
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
The Single Cycle Datapath during Load?
31
26
21
op
16
rs
0
rt
immediate
• R[rt] = Data Memory {R[rs] + SignExt[imm16]}
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
ExtOp=
Extender
clk
Rs Rt Rd Imm16
zero ALUctr=
MemtoReg=
MemWr=
32
Z
ALU
busW
0
32
1
32
Data In
ALUSrc=
CS61C L19 CPU Design: The Single-Cycle II & Control (26)
<0:15>
RegWr=
0
<11:15>
1
clk
<16:20>
Rd Rt
<21:25>
nPC_sel=
RegDst=
Instruction<31:0>
instr
fetch
unit
clk
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
The Single Cycle Datapath during Load
31
26
21
op
16
rs
0
rt
immediate
• R[rt] = Data Memory {R[rs] + SignExt[imm16]}
0
RegWr=1
5
Rs Rt
5
5
busA
Rw Ra Rb
RegFile
32
32
16
Extender
clk
imm16
busB
ExtOp=sign
Rs Rt Rd Imm16
zero ALUctr=ADD
MemtoReg=mem
MemWr=0
32
Z
ALU
busW
0
32
1
32
Data In
clk
ALUSrc=imm
CS61C L19 CPU Design: The Single-Cycle II & Control (27)
<0:15>
1
<11:15>
Rd Rt
<16:20>
nPC_sel=+4
RegDst=rt
clk
Instruction<31:0>
<21:25>
instr
fetch
unit
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
The Single Cycle Datapath during Store?
31
26
21
op
16
rs
0
rt
immediate
• Data Memory {R[rs] + SignExt[imm16]} = R[rt]
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
ExtOp=
Extender
clk
Rs Rt Rd Imm16
zero ALUctr=
MemtoReg=
MemWr=
32
Z
ALU
busW
0
32
1
32
Data In
ALUSrc=
CS61C L19 CPU Design: The Single-Cycle II & Control (28)
<0:15>
RegWr=
0
<11:15>
1
clk
<16:20>
Rd Rt
<21:25>
nPC_sel=
RegDst=
Instruction<31:0>
instr
fetch
unit
clk
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
The Single Cycle Datapath during Store
31
26
21
op
16
rs
0
rt
immediate
• Data Memory {R[rs] + SignExt[imm16]} = R[rt]
0
RegWr=0
5
Rs Rt
5
5
busA
Rw Ra Rb
RegFile
32
32
16
Extender
clk
imm16
busB
ExtOp=sign
Rs Rt Rd Imm16
zero ALUctr=ADD
MemtoReg=x
MemWr=1
32
Z
ALU
busW
0
32
1
32
Data In
clk
ALUSrc=imm
CS61C L19 CPU Design: The Single-Cycle II & Control (29)
<0:15>
1
<11:15>
Rd Rt
<16:20>
nPC_sel=+4
RegDst=x
clk
Instruction<31:0>
<21:25>
instr
fetch
unit
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
The Single Cycle Datapath during Branch?
31
26
21
op
16
rs
0
rt
immediate
• if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0
Rs Rt
5
5
5
Rw Ra Rb
RegFile
32
busA
busB
32
imm16
16
ExtOp=
Extender
clk
Rs Rt Rd Imm16
zero ALUctr=
MemtoReg=
MemWr=
32
Z
ALU
busW
0
32
1
32
Data In
ALUSrc=
CS61C L19 CPU Design: The Single-Cycle II & Control (30)
<0:15>
RegWr=
0
<11:15>
1
clk
<16:20>
Rd Rt
<21:25>
nPC_sel=
RegDst=
Instruction<31:0>
instr
fetch
unit
clk
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
The Single Cycle Datapath during Branch
31
26
21
op
16
rs
0
rt
immediate
• if (R[rs] - R[rt] == 0) then Zero = 1 ; else Zero = 0
0
RegWr=0
Rs Rt
5
5
5
busA
Rw Ra Rb
RegFile
32
busB
32
imm16
16
Extender
clk
ExtOp=x
Rs Rt Rd Imm16
zero ALUctr=SUB
MemtoReg=x
MemWr=0
32
Z
ALU
busW
0
32
1
32
Data In
clk
ALUSrc=reg
CS61C L19 CPU Design: The Single-Cycle II & Control (31)
<0:15>
1
<11:15>
Rd Rt
<16:20>
nPC_sel=br
RegDst=x
clk
Instruction<31:0>
<21:25>
instr
fetch
unit
32
0
WrEn Adr
Data
Memory
1
Pearce, Summer 2010 © UCB
Instruction Fetch Unit at the End of Branch
31
26
21
op
rs
16
0
rt
immediate
• if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ;
else PC = PC + 4
Inst
Memory
nPC_sel
Adr
Zero
Instruction<31:0>
• What is encoding of
nPC_sel?
• Direct MUX select?
MUX
ctrl
nPC_sel
• nPC_sel = +4  0
PC
0
00
• Let’s pick 2nd option
Mux
Adder
PC Ext
imm16
Adder
4
• Branch inst. / not branch
• nPC_sel = br  1
1
clk
nPC_sel
0
1
1
CS61C L19 CPU Design: The Single-Cycle II & Control (32)
zero?
x
0
1
MUX
0
0
1
Q: What
logic gate?
Pearce, Summer 2010 © UCB
Peer Instruction
1) In the worst case, the
delay is the memory access time
2) With only changes to control, our
datapath could write (something)
to memory and registers in one
cycle.
CS61C L19 CPU Design: The Single-Cycle II & Control (33)
a)
b)
c)
d)
12
FF
FT
TF
TT
Pearce, Summer 2010 © UCB
Peer Instruction Answer
1) Memory has by far a higher access
time than combinational logic. TRUE
2) Let’s look back at the datapath. Take a
sw instructions. Can we also write to a
register? If so, which reg? What
value? TRUE
1) In the worst case, the
delay is the memory access time
2) With only changes to control, our
datapath could write (something)
to memory and registers in one
cycle.
CS61C L19 CPU Design: The Single-Cycle II & Control (34)
a)
b)
c)
d)
12
FF
FT
TF
TT
Pearce, Summer 2010 © UCB
Summary: A Single Cycle Datapath
Instruction<31:0>
Rs Rt Rd Imm16
ALUctr
MemtoReg
Rd Rt
1
RegWr
0
5
Rs Rt
5
busB
32
Extender
clk
imm16
busA
16
ExtOp
CS61C L19 CPU Design: The Single-Cycle II & Control (35)
32
MemWr
Z
ALU
RegFile
32
zero
5
Rw Ra Rb
busW
<0:15>
RegDst
<11:15>
clk
<16:20>
instr
fetch
unit
nPC_sel
<21:25>
• We have
everything!
Now we
just need
to know
how to
BUILD
CONTROL
0
32
1
32
Data In
clk
32
0
WrEn Adr
Data
Memory
1
ALUSrc
Pearce, Summer 2010 © UCB
Summary: Single-cycle Processor
°5 steps to design a processor
• 1. Analyze instruction set  datapath requirements
• 2. Select set of datapath components & establish clock
methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to
determine setting of control points that effects the
register transfer.
• 5. Assemble the control logic
Processor
• Formulate Logic Equations
• Design Circuits
Control
Memory
Datapath
CS61C L19 CPU Design: The Single-Cycle II & Control (36)
Input
Output
Pearce, Summer 2010 © UCB