Lecture 20
Today we will
 Look at why our NMOS and PMOS inverters might
not be the best inverter designs
 Introduce the CMOS inverter
 Analyze how the CMOS inverter works
NMOS Inverter
5V
R
ID = 5/R
VIN
5V
D
+
VDS
_
5V
When VIN is logic 1,
VOUT is logic 0.
R
Constant nonzero
VOUT current flows through
transistor.
0V
ID = 0
VIN
Power is used even
though no new
0V
computation is being
performed.
D
+
VOUT
5V
VDS
_
When VIN changes to logic 0, transistor gets cutoff. ID goes to 0.
Resistor voltage goes to zero. VOUT “pulled up” to 5 V.
PMOS Inverter
5V
Constant nonzero
VIN
current flows through
VDS
VOUT transistor.
+
0V
ID = -5/R
R
5V
5V
When VIN is logic 0,
VOUT is logic 1.
Power is used even
though no new
computation is being
performed.
VIN
VDS
VOUT
+
5V
ID = 0
0V
R
When VIN changes to logic 1, transistor gets cutoff. ID goes to 0.
Resistor voltage goes to zero. VOUT “pulled down” to 0 V.
Analysis of CMOS Inverter
VDD (Logic
S1)
D
VIN

We can follow the same
procedure to solve for currents
and voltages in the CMOS
inverter as we did for the single
NMOS and PMOS circuits.

Remember, now we have two
transistors so we write two I-V
relationships and have twice
the number of variables.

We can roughly analyze the
CMOS inverter graphically.
VOUT
D
S
NMOS is “pull-down device”
PMOS is “pull-up device”
Each shuts off when not pulling
NMOS Inverter
ID
VGS = 3 V
X
Linear ID vs VDS given
by surrounding circuit
X
VGS = 1 V
VDS
Linear KVL and KCL Equations
VDD (Logic
S1)
VOUT
D
VIN
D
S
+
VDS(n)
_
Use these equations
to write both I-V equations in
terms of VDS(n) and ID(n)
VGS(n) = VIN
VGS(p) = VIN – VDD
VGS(p) = VDS(n) - VDD
ID(p) = -ID(n)
VDS(n) = VOUT
VDS(p) = VOUT – VDD
VDS(p) = VDS(n) - VDD
CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.
NMOS I-V curve
PMOS I-V curve
(written in terms of
NMOS variables)
VIN =
VGS(n) =
0.9 V
VDS(n)
VDD
CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.
NMOS I-V curve
PMOS I-V curve
(written in terms of
NMOS variables)
VIN =
VGS(n) =
1.5 V
VDS(n)
VDD
CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.
NMOS I-V curve
PMOS I-V curve
(written in terms of
NMOS variables)
VIN =
VGS(n) =
2.0 V
VDS(n)
VDD
CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.
NMOS I-V curve
PMOS I-V curve
(written in terms of
NMOS variables)
VIN =
VGS(n) =
2.5 V
VDS(n)
VDD
CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.
NMOS I-V curve
PMOS I-V curve
(written in terms of
NMOS variables)
VIN =
VGS(n) =
3.0 V
VDS(n)
VDD
CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.
NMOS I-V curve
PMOS I-V curve
(written in terms of
NMOS variables)
VIN =
VGS(n) =
3.5 V
VDS(n)
VDD
CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger
and VGS(p) gets less negative.
NMOS I-V curve
PMOS I-V curve
(written in terms of
NMOS variables)
VIN =
VGS(n) =
4.1 V
VDS(n)
VDD
CMOS Inverter VOUT vs. VIN
VOUT
both
sat.
VDD
curve very
steep here;
only in “C” for
small interval
of VIN
NMOS:
cutoff
PMOS:
triode
NMOS:
saturation
NMOS:
triode
NMOS:
triode
PMOS:
saturation
PMOS:
cutoff
PMOS:
triode
A
B
C
D
E
VIN
VDD
ID
CMOS Inverter ID
A
B
C
D
E
VIN
VDD
Important Points


No ID current flow in Regions A and E if nothing attached to
output; current flows only during logic transition
If another inverter (or other CMOS logic) attached to output,
transistor gate terminals of attached stage do not permit
current: current still flows only during logic transition
VDD
VDD
S
D
VIN
S
VOUT1
D
D
D
S
S
VOUT2