GOMAC, March 25, 2010, Reno, NV.
THz Bipolar Transistors:
Design and Process Technologies
Mark Rodwell
University of California, Santa Barbara
E. Lobisser, V. Jain, A. Baraskar, M. Seo, B. J. Thibeault,
University of California, Santa Barbara
M. Seo, Z. Griffith, J. Hacker, M. Urteaga, Richard Pierson, B. Brar
Teledyne Scientific Company
rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax
Why
THz Transistors ?
Why Build THz Transistors ?
500 GHz digital logic
→ fiber optics
THz amplifiers→ THz radios
→ imaging, sensing,
communications
precision analog design
at microwave frequencies
→ high-performance receivers
Higher-Resolution
Microwave ADCs, DACs,
DDSs
Why Bipolars for Fast Analog Applications ?
digital frequency synthesis
mm-wave
phased arrays
high resolution ADCs and DACs for 2-20, 38 GHz
CMOS does not serve all ICs
low analog gain
low analog precision
low breakdown voltage
high Cds /Cgs , high Cgd /Cgs
→ less bandwidth
than ft suggests
0.35 fF
0.7 fF
0.7 fF
jammer on chip
BJTs, particularly InP,
have high breakdown
How to Make
THz Transistors
Changes required to double transistor bandwidth
We
emitter
length LE 
HBT parameter
emitter & collector junction widths
current density (mA/mm2)
current density (mA/mm)
collector depletion thickness
base thickness
emitter & base contact resistivities
change
decrease 4:1
increase 4:1
constant
decrease 2:1
decrease 1.4:1
decrease 4:1
nearly constant junction temperature → linewidths vary as (1 / bandwidth)2
LG
gate width WG 
constant voltage, constant velocity scaling
FET parameter
gate length
current density (mA/mm), gm (mS/mm)
channel 2DEG electron density
gate-channel capacitance density
dielectric equivalent thickness
channel thickness
channel density of states
source & drain contact resistivities
change
decrease 2:1
increase 2:1
increase 2:1
increase 2:1
decrease 2:1
decrease 2:1
increase 2:1
decrease 4:1
fringing capacitance does not scale → linewidths scale as (1 / bandwidth )
40
Z. Griffith
340 GHz dynamic frequency divider
H
mA/mm2
10
30
dB
256 nm Generation
InP HBT
150 nm thick collector
U
21
20
fmax = 780 GHz
10
M. Seo, UCSB/TSC
t
10
10
10
11
10
Vtune
max
2
3
4
5
12
11
10
20
21
U
f
1
V
2
E. Lind
mA/mm
M. Seo, UCSB/TSC
dB
340 GHz VCO
0
12
10
ce
10
10
10
9
10
H
20
4
0
Hz
70 nm thick collector
30
6
2
f = 424 GHz
0
9
10
8
= 560 GHz
15
10
5
f = 560 GHz
t
0
0
9
10
VBB
VEE
10
10
11
10
0
12
10
1
2
V
Hz
Vout
3
4
ce
60 nm thick collector
40
30
H
U
Z. Griffith
2
dB
30
mA/mm
324 GHz amplifier J. Hacker, TSC
21
20
10 fmax = 218 GHz
20
10
f = 660 GHz
t
0
9
10
10
10
11
10
Hz
10
12
0
0
1
2
V
ce
3
InP Bipolar Transistor Scaling Roadmap
emitter 512
16
256
8
128
4
64
2
32 nm width
1 mm2 access r
base
300
20
175
10
120
5
60
2.5
30 nm contact width,
1.25 mm2 contact r
collector 150
4.5
4.9
106
9
4
75
18
3.3
53
36
2.75
37.5 nm thick,
72 mA/mm2 current density
2-2.5 V, breakdown
520
850
430
240
730
1300
660
330
1000
2000
1000
480
1400 GHz
2800 GHz
1400 GHz
660 GHz
ft
fmax
power amplifiers
digital 2:1 divider
370
490
245
150
We
Tb
Wbc
Tc
Conventional ex-situ contacts are a mess
THz transistor bandwidths: very low-resistivity contacts are required
textbook contact
with surface oxide
with metal penetration
Interface barrier → resistance
Further intermixing during high-current operation → degradation
In-Situ Refractory Ohmics on Regrown N-InGaAs
5
8
In-situ Mo on n-InAs
Resistance ()
Resistance ()
4
3
2
ρc = 0.6 ± 0.4 Ω·µm2
1
In-situ Mo on n-InGaAs
6
4
ρc = 1.0 ± 0.6 Ω·µm2
2
n = 5×1019 cm-3
n = 1×1020 cm-3
0
0
0.5
1
1.5
2
2.5
3
Gap Spacing (mm)
In-situ emitter contacts good
enough for 64 nm node
3.5
00
0.5
1
1.5
2
2.5
3
3.5
Gap Spacing (mm)
HAADF-STEM*
InGaAs
regrowth
Interface
InGaAs
2 nm
TEM by Dr. J. Cagnon, Stemmer Group, UCSB
A. Baraskar
Process Must Change Greatly for 128 / 64 / 32 nm Nodes
control undercut
→ thinner emitter
thinner emitter
→ thinner base metal
Undercutting of emitter ends
{101}A planes: fast
{111}A planes: slow
thinner base metal
→ excess base metal resistance
128 / 64 nm process: Dry-Etched Emitter Metal
In-situ MBE emitter contacts:
refractory→ high J
low contact r: ~0.7 -mm2
Refractory emitter contact
dry-etched→ nm resolution
refractory→ high current
Wet/dry etched emitter
dry-etched→ nm resolution
conventional base liftoff
high penetration→ thick bases
moderate contact r ~4-mm2
yield issues ?
V. Jain
E. Lobisser
Dry-Etched W/TiW Emitter Contact Process
Sputtered
W/ Ti0.1W0.9
process
Vertical ICP
etch profile
Low-stress film
Good adhesion
between layers
Refractory
Metals
W/TiW bilayer:
stress and
etch bias
compensation
V. Jain
E. Lobisser
Sub-100 nm devices: lifted-off base metal
V. Jain
E. Lobisser
After Sidewall Etch
Base Contact, Post and Mesa Etch
Device Isolation Etch
HBT before BCB processing
Sub-100 nm devices: lifted-off base metal
V. Jain
E. Lobisser
Sub-100 nm devices: lifted-off base metal
15 MAG/MSG
A = 0.11mm x 3.5mm
je
U
I = 9.1mA; V = 1.75V
c
ce
40
30
A = 0.11mm x 3.5mm
je
f = 400 GHz
U
H
20
t
f
max
= 660 GHz
21
Gain (dB)
2
J = 23.6mA/mm ; V
10
e
H
10 I = 8.9mA; V = 1.74V
c
ce
2
J = 23.1mA/mm ; V
e
0
9
10
10
cb
11
50 mW/mm
50
0
11
10
2
t
:V
:V
I
b,step
= 0.2 mA
cb
cb
=0V
20
V
cb
10
=0V
I = 0.01 mA
b
0
1
2
V
ce
(V)
3
Peak f /f
t max
12
750
= 0.7 V
600
600
450
450
300
300
max
30
(GHz)
A = 0.11mm x 3.5mm
10
freq (Hz)
750
je
0
= 660 GHz
t
e
2
10
40
max
= 0.7V
f (GHz)
J (mA/um )
12
10
freq (Hz)
60 40 mW/mm2
f
cb
f = 465 GHz
= 0.7V
10
21
5
f
Gain (dB)
MAG/MSG
V. Jain
E. Lobisser
150
0
5
150
10 15 20 25 30 35
2
J (mA/mm )
e
128 / 64 nm process: Sputtered Refractory Base
In-situ MBE emitter contacts:
refractory→ high J
low contact r: ~0.7 -mm2
Refractory emitter contact
dry-etched→ nm resolution
refractory→ high current
Wet/dry etched emitter
dry-etched→ nm resolution
Refractory base contacts
low penetration→ thin bases
low contact r ~2.5 -mm2
self-aligned/ liftoff-free
V. Jain
E. Lobisser
In-Situ Refractory Ohmics on P-InGaAs
Metal Contact
ρc (Ω-µm2)
ρh (Ω-µm)
In-situ Ir
1.0 ± 0.7
11.5 ± 3.3
Resistance ()
20
Iridium
15
10
5
0
2  rC  RSh
2  RC 
W
0
1
2
3
Gap Spacing (mm)
In-situ base contacts good enough for 32 nm node
Remaining work: contacts on processed surfaces
contact thermal stability & reliability
4
A. Baraskar
Benefits of refractory base contacts
15 nm Pd/Ti diffusion
100 nm InGaAs grown in MBE
30 nm Mo
After 250°C anneal, Pd/Ti/Pd/Au diffuses 15nm into semiconductor
deposited Pd thickness: 2.5nm
base now 30 nm thick: observed to degrade with thinner bases
Refractory Mo contacts do not diffuse measurably
Refractory, non-diffusive metal contacts for thin base semiconductor
A.. Baraskar
Sputtered Process for in-situ base contacts
20
• Planarization and etch back
• Low contact resistivity
• Lift-off free and Au free base process
• Self-aligned process for thin emitters
• Enables refractory, in-situ base contacts
Resistance ()
• Blanket ex-situ Pd/W contacts
Iridium
15
10
5
0
ρc =1.0 ± 0.7 Ω-µm2
0
1
2
3
Gap Spacing (mm)
4
Planarization boundary
SiNx Sidewall
V. Jain
E. Lobisser
Sub-100 nm HBTs : planarized base contact
Emitter projecting from PR for
planarization
Base Contact, Post and Mesa Etch
Planarized Emitter
Contact Via Etch
V. Jain
E. Lobisser
670 GHz Transceiver Simulations in 128 nm InP HBT
transmitter exciter
Simulations @ 670 GHz (128 nm HBT)
LNA: 9.5 dB Fmin at 670 GHz
30
PA: 9.1 dBm Pout at 670 GHz
35
35
20
30
20
30
620
receiver
640
660
680
SP.freq, GHz
freq, GHz
(a)
700
10
0
0
720
800
820
64nm
-10
840 -10
-8860 -6
-4880 -2
(b)
VCO:
-50 dBc (1 Hz)
@ 100 Hz offset
at 620 GHz (phase 1)
128nm
4 0.986
(c)
free-running
VCO
0
Total PLL
phase noise
-50
closed-loop
VCO noise
-100
multiplied
reference noise
-150
1
10
2
3
4
10
6
10
7
950 GHz Input
-0.9
-0.95
-0.95
Vout, Vout_bar
Vout , Vout_bar
5
10
10
10
offset from carrier, Hz
-1
-1.05
-1.1
-1.15
-1
-1.05
-1.1
-1.15
197.5 10
-12
200 10
-1.2
-12
195 10
-12
Noise Figure, Conversion Gain (dB)
197.5 10
-12
time, seconds
time, seconds
Mixer:
10.4 dB noise figure
11.9 dB gain
-8
50
-0.9
-1.2
-12
195 10
1.04
-10
SP.freq, THz
freq, THz
690 GHz Input
Dynamic divider:
novel design,
simulates to 950 GHz
3
-10
1.02 -12
8 1.0010
(a)
10
3-layer thin-film THz interconnects
thick-substrate--> high-Q TMIC
thin -> high-density digital
0
-5
Pin
SP.freq, GHz
freq, GHz
5
10
0
0900 2
10
20
Gain
Pout
5
-5
128nm
0
nf(2)
dB(S(2,1))
10
15
10
20
PLL single-sideband
phase noise spectral density, dBc (1 Hz)
20
Gain
Pout
nf(2)
dB(S(2,1))
nf(2)
dB(S(2,1))
15
30
25
20
15
10
5
0
-5
-15.00
-10.00
-5.000
0.0000 5.000
LO Power
10.00
200 10
-12
1.-
InP HBT Fundamental Oscillators to > 340 GHz
M. Seo UCSB
M. Rodwell UCSB
M. Urteaga TSC
TSC HBT Technology
Differential Topology, Cascode output buffer, ECL outputs
Fixed frequency and voltage controlled designs
R1
Lout2
Vtune
VOUT
R3
Lout1
Q5
Q3
Q4
LC3
R2
LC2
R4
LC1
VBB
VEE
Q6
LB
Q1
LE1
CVar
Q2
CVar
LE2
Vout
RE
C1
C2
VEE VTUNE
C3
VBB
InP HBT 331 GHz Dynamic Frequency Dividers
Topology: Double-balanced mixer with emitter
follower feedback and resonant loading
M. Seo UCSB
M. Rodwell UCSB
M. Urteaga TSC
Z. Griffith TSC
TSC HBT Technology
Circuit Schematic
Modified version of modern dynamic divider (H.M. Rein)
Inverted microstrip wiring
Design variations with input for external clock
source and with integrated fixed frequency and
voltage controlled oscillators for testing.
Output spectrum with 331.2 GHz clock input
“Signal Identification” test at fIN= 331.2 GHz
Chip photograph
THz 240 GHz PA Design
Teledyne InP HBTs We=256nm, Tc=150nm
Two-finger design achieves S21 = 4.9dB @ 238GHz
T. Reed UCSB
M. Urteaga TSC
Z. Griffith TSC
TSC HBT Technology
THz Transistors
THz Integrated Circuits
Device scaling (Moore's Law) is not yet over.
Scaling→ multi-THz transistors.
Challenges in scaling:
contacts, dielectrics, heat
Multi-THz transistors:
for systems at very high frequencies
for better performance at moderate frequencies
Vast #s of THz transistors
complex systems
new applications.... imaging, radio, and more
end
On-Wafer TRL Calibration Envirnoment
Ref Plane for TRL
Ref Plane for TRL
0.5-67GHz Data: Lumped Pads, Off Wafer LRRM Cal.
m7
freq=1.103GHz
dB(h21d)=26.624
Fmax_fit = 660GHz
Ft_fit = 400GHz
m7
Standard Off Wafer OSLT
Open & Short Pad Cap Extraction
Open
Short
THz
Bipolar Transistors
Sub-100 nm devices: lifted-off base metal
15 MAG/MSG
A = 0.11mm x 3.5mm
je
U
I = 9.1mA; V = 1.75V
c
ce
40
A = 0.11mm x 3.5mm
je
f = 400 GHz
U
H
20
t
f
max
= 660 GHz
21
Gain (dB)
30
2
J = 23.6mA/mm ; V
10
e
H
2
J = 23.1mA/mm ; V
e
10
10
11
12
10
freq (Hz)
f
max
cb
= 0.7V
= 660 GHz
f = 465 GHz
= 0.7V
10
0
11
10
t
S21/5
:V
:V
cb
cb
=0V
750
= 0.7 V
600
600
450
450
300
300
max
t
--- : Measured
x : Simulated
S11
S22
150
0
5
150
10 15 20 25 30 35
2
J (mA/mm )
freq (1.000GHz to 67.00GHz)
freq (100.0MHz to 67.00GHz)
12
f (GHz)
(GHz)
S12x5
10
freq (Hz)
750
f
0
9
10
cb
21
5
10 I = 8.9mA; V = 1.74V
c
ce
S_parameter_Deembed_PNA..S21d/5
S_parameter_Deembed_PNA..S12d*5
S(2,1)/5
S(1,2)*5
S(2,2)
S_parameter_Deembed_PNA..S22d
S_parameter_Deembed_PNA..S11d
S(1,1)
Gain (dB)
MAG/MSG
V. Jain
E. Lobisser
e
Sub-100 nm devices: lifted-off base metal
-2
60 40 mW/mm2
Dashed Line: V
cb
b
-6
n = 3.04
b
10
10
A = 0.11mm x 3.5mm
je
I
b,step
20
V
c
cb
10
-10
0
0.4
V
be
0.6
(V)
0.8
1
=0V
I = 0.01 mA
b
0
1
2
V
ce
(V)
3
Peak f /f
t max
8
V
7
cb
0.2
(fF)
0
= 0.2 mA
30
C
10
n = 1.41
2
40
e
b
-8
50 mW/mm
50
= 0.7 V Ic
I
c
I , I (A)
10
-4
cb
=0V
2
Solid Line: V
J (mA/um )
10
V. Jain
E. Lobisser
cb
=0V
6
5
V
cb
= 0.4 V
4
V
3
0
cb
5
= 0.7 V
10 15 20
2
J (mA/mm )
e
25
30
2008 UCSB Dry-Etched Ti/TiW Emitter Process
a
b
Litho
Cr
pattern
metal
c
SF6/Ar ICP
SiNsidewall
x sidewall
d
dry/N
etch
Cl
2 2 ICP
SiO2
e
Wetetch
Etch
wet
HCl:H3PO4
BHF
TiW
Ti
InGaAs n++
InP n
InP n
InP n
InGaAs p++ Base
InGaAs p++ Base
InGaAs p++ Base
InGaAs p++ Base
H
10
10
10
9
10
30
Worked well @ 200 nm
21
U
20
dB
base contact
by liftoff
f
10
max
InGaAs p++ Base
12
InP n
11
InGaAs n++
10
InGaAs n++
Low yield @ 128 nm:
stress→ poor adhesion
= 560 GHz
f = 560 GHz
t
0
9
10
10
10
11
10
Hz
12
10
Substantial revision
required