2001 GOMAC Conference
Ultra high speed heterojunction bipolar
transistor technology
Mark Rodwell
University of California, Santa Barbara
rodwell@ece.ucsb.edu 805-893-3244, 805-893-3262 fax
Scaling and high speed electronics
Fast electronics:
10, 40,160 …(?) Gb/s fiber optics
Gigabit radio on 60 GHz band
180 GHz amplifiers,
sensitive 2.5 THz diode mixers
cheap 2 GHz phones, cheap 1 GHz PCs, cheap 20 GHz TV
electronics gets ~10:1 faster each decade
Are we reaching the limits ?
...radically different materials ?
...resonant tunneling ??
…the electronic bottleneck ?
Improving high frequency devices by Scaling:
dimensions, current density, contacts
near-THz transistors, ~10 THz diodes,
towards 100-GHz logic
 applications in ADCs/DACs for RADAR
Fast electronics can still get much faster
Bandwidth of bipolar transistors:
current-gain cutoff frequency
 kT

1
kT
  base   collector  C je
 Cbc 
 Rex  Rcoll 
2f
qI E
 qI E

 base  Tb2 2 Dn
 collector  Tc 2vsat
Thinner base, thinner collector
 higher f ,
but….
Bandwidth of bipolar transistors:
power-gain cutoff frequency
f max 
f 8RbbCcbi
emitter
base
base
subcollector
Ccbi : effective fraction of Ccb charged through Rbb
Thinner base, thinner collector
 more base resistance, more collector capacitance
 reduced power gain cutoff frequency fmax
What matters: ft or fmax ?
How do we scale device to get high values for both ?
base contact pad
Scaling Laws for fast HBTs
transferred-substrate
for x 2 improvement of all parasitics:
ft, fmax, logic speed…
base 2: 1 thinner
collector 2:1 thinner
emitter, collector junctions 4:1 narrower
current density 4:1 higher
emitter Ohmic 4:1 less resistive
undercut-collector
emitter
Challenges with Scaling:
Collector
mesa HBT: collector under base Ohmics.
Base Ohmics must be one transfer length
sets minimum size for collector
Emitter Ohmic:
hard to improve…how ?
Current Density:
dissipation, reliability
Loss of breakdown
avalanche Vbr never less than collector Egap
(1.12 V for Si, 1.4 V for InP)
….sufficient for logic, insufficient for power
base contact
InGaAs
collector
undercut
collector junction
collector
-base
junction
InGaAs base
InP collector
collector
contact
InGaAs subcollector
InP subcollector
SI substrate
collector
contact
Narrow-mesa with 1E20 carbon-doped base
emitter
base contact
base contact
base
polymer
polymer
sub collector
SI substrate
What HBT parameters determine analog bandwidth ?
Tuned ICs (MIMICs, RF):
fmax sets gain,
& max frequency, not ft.
…low ft/fmax ratio makes
tuning design hard (high Q)
Lumped analog circuits
need high & comparable ft
and fmax.
(1.5:1 fmax/ft ratio often
cited as good…)
Distributed Amplifiers
in principle, fmax-limited,
ft not relevant….
(low ft makes design hard)
What HBT parameters determine logic speed ?
MS latch: key digital element :
resynchronizes data to clock
often sets system maximum clock
1 / 2 f clock  T
 6.4  Ccb
Vlogic
893 fsec
I
 11.9  Ccb Rex
640 fsec
  wiring
600 fsec
 1.5   b   c 
 0.6  Csubstrate
Vlogic
in
in
341 fsec
I
clock
229 fsec
 1.5  Ccbi Rb
208 fsec
 0.2  C je Rb
191 fsec
I
 0.3  Rb  b   c 
187 fsec
Vlogic
Vlogic
I
 0.8  C je Rex
 0.6  Cwiring
out
528 fsec
 8.2  Cwiring Rex
 0.4  C je
out
166 fsec
121 fsec
Vlogic
I
42 fsec
120 GHz clock predicted
clock
clock
clock
fmax does not predict digital speed
f does not predict digital speed
CcbVlogic/Ic is very important
 increased III-V current density is critical
CcbRex is very important
Rbb(Cje+gmb+gmc) is important
What is needed for 200 GHz Logic ?
Emitter
parasitic
width
resistance
1.2
50
0.7
50
0.7
50
0.7
50
0.35
50
0.35
50
0.35
25
0.35
12.5
m Ohm-m2
width
1.8
1.5
1.5
0.8
0.45
0.45
0.45
0.45
m
UCSB
Miguel Urteaga
Clock
Collector
Base
current
thickness
density material thickness
doping
3000
1.0E+05 InGaAs
400 4E19 Be
115
3000
1.0E+05 InGaAs
400 4E19 Be
125
3000
1.0E+05 InGaAs
300 4E19 Be
128
3000
1.0E+05 InGaAs
300 4E19 Be
159
3000
1.0E+05 InGaAs
300 4E19 Be
176
3000
1.0E+05 InGaAs
300 1E20 C
182
2120
2.0E+05
InP
300 1E20 C
250
1500 4.0E+05
InP
300 1E20 C
285
A/cm2
cm-3
Å
-Å
GHz
SPICE simulation
Interconnects are not considered.
Transferred Substrate HBTs
2000
TransferredSubstrate HBT
Mesa HBT
1000
0.5 m base Ohmics
f
max
, GHz
1500
500
finite-element device simulation
0
0
0.5
1
emitter width, microns
1.5
• UCSB “transferred substrate” process allows lateral scaling of
collector. Record fmax more than tripled.
• Most circuits demand high ft. Laterally scalable device allows
fmax to be retained when ft is improved by vertical scaling.
Transferred Substrate HBT Process
Objectives:
1) Normal emitter, base processes. 2) Coat with BCB polymer.
Deposit silicon nitride insulator.
Etch vias.
• 1000 GHz transistor
bandwidth
• Thermal management
for high power density
• Low wiring & packaging
parasitics at 100+ GHz
Approach:
• BCB process:
standard IC materials
• Metal substrate,
thermal vias
• Microstrip wiring:
ground vias
backside ground plane
r=2.7: low capacitance
insulator
InP substrate
3) Electroplate gold vias
solder bond to carrier
InP substrate
4) Invert wafer.
Remove InP substrate.
Deposit collector.
solder bond
Gold
thermal
via
InP substrate
Gold
thermal
via
solder bond
Submicron Transferred-Substrate HBT
UCSB
Michelle Lee
3000 Å collector
400 Å base with 52 meV grading
AlInAs / GaInAs
30 / GaInAs HBT
Mason's
gain, U
Gains, dB
25
20
MSG
15
H
10
emitter, 0.4 x 6 m
2
5
21
f = 204 GHz

collector, 0.4 x 6 m
I = 6 mA, V = 1.2 V
2
c
f
max
= 1.1 THz
(?)
ce
0
10
100
Frequency, GHz
1000
High Fmax Transistor Measurement
UCSB
Miguel Urteaga
Submicron HBT Program
( K< 1 at all measured frequencies)
U
U
MAG/MSG
H21
MSG
Unpublished
140-220 GHz Unilateral power gain:
high but difficult to measure
fmax appears to be near 1 THz.
Future work must address:
improved 220 GHz measurements,
measurements at > 220 GHz.
Record f HBT
2000 Å collector
300 Å base with 52 meV grading
AlInAs / GaInAs / GaInAs HBT
50
h
21
Gains (dB)
40
30
U
20
V
10
f
2
CE
= 1 V, J = 1.5 mA/um

= 295 GHz
C
f
MAX
= 295 GHz
Emitter 1 x 8 m2, Collector 2 x 8.5 m2.
0
1
10
Frequency (GHz)
10
2
UCSB
Yoram Betser
UCSB
Record f HBT
Ccbx  6.4 fF
B
Rc  6500 
Ccbi  3.7 fF
Rbb  49 
C bg 
0.1 fF
Vb'e
R 
350 
Cdiff  C je 
182 fF 38 fF C s  3.7 fF
g m  g mo exp(  j c )
Cdiff  g mo  f
 f  395 fs
 c  290 fs
Rex Ccb  39 fs
Yoram Betser
C
g mVb 'e
Rex  4.3 
E
g mo  460 mS
C je / g m  82 fs
Ccb / g m  20 fs
 Rex  1 / g m  Cbg  1 fs
1 2f  EC   C BC je / g m 0  Ccb / g m 0  Rex Ccb
537fs
290fs 105fs
82fs
20fs
39fs
UCSB
I - V characteristics
c
20
ce
3 kÅ collector, 400 Å base
8
15
I in steps
B
7
1x 8 micron emitter,
2x 10 micron collector
10
m2
freq=165.0GHz
dB(short..S(2,1))=0.000
5
of 20 uA
6
5
I (mA)
m2 m1
0
4
c
dB(short..S(2,1))
U
dB(h21)
6.2 DHBT
program
Fast InP DHBTs for higher power
pk Sundararajan
M Dahlstrom
-5
m1
freq=303.0GHz
dB(short..S(2,1))=0.000
-10
f = 165 GHz;
fmax = 303 GHz
-15
3
5 V breakdown at 105 A/cm2
2
>9 V at 2*104 A/cm2
1
0
-20
1E9
1E10
1E11
0
1E12
1
2
3
V (volts)
freq, Hz
4
5
6
ce
20
2 kÅ collector, 400 Å base
Jc - Vce characteristics
15
5
10
4
8 10
5
Jc (A/cm )
m1
2
dB(short..S(2,1))
U
dB(h21)
1 10
1x 8 micron emitter,
2x 10 micron collector
0
-5
m1
freq=216.0GHz
dB(short..S(2,1))=-1.086E-10
f = 216 GHz;
fmax = 210 GHz
-10
-15
1E10
1E11
freq, Hz
4 V breakdown at 105 A/cm2
4
4 10
>6 V at 2*104 A/cm2
4
2 10
-20
1E9
6 104
1E12
0
0
1
2
3
V (volts)
ce
4
5
200 GHz Single-Stage Amplifier
UCSB
Miguel Urteaga
Submicron HBT Program
• Single-stage Reactively-tuned
Measured Gain
8
amplifier at 180 GHz with 6 dB gain
6
• Gain-per-stage ~2:1 higher than
HEMT amplifiers at same frequency
S21, dB
4
• Simple design to provide directions for
future work
2
0
-2
• Future Work: Multi-stage amplifiers
with improved devices
-4
140 150 160 170 180 190 200 210 220
Frequency, GHz
Measured Return Loss
0
S22
S11, S22, dB
-5
S11
-10
-15
-20
-25
140 150 160 170 180 190 200 210 220
Frequency, GHz
UCSB
James Guthrie
InP-HBT W-band Amplifiers
balanced amplifier: 10.7dBm at 78GHz
(transferred-substrate HBT)
InGaAs-collector:
 Vbr=1.5 V  low power
InP-collector:
 Vbr~5 V
 higher powers expected
ARO
common-base amplifier: 9.7dBm at 82.5 GHz
High Speed Amplifiers
18 dB, DC--50+ GHz
20
S21
15
>397 GHz
gain x bandwidth
from 2 HBTs
10
5
0
S11
-5
-10
S22
-15
-20
0
10
20
30
40
50
8.2 dB, DC-80 GHz
10
Gains, dB
S
21
5
0
S
-5
11
-10
S
22
-15
0
10
20
30
40
50
Frequency, GHz
60
70
80
UCSB
Dino Mensa
PK Sundararajan
HBT distributed amplifier
AFOSR
11 dB, DC-87 GHz
15
S
10
21
Gains, dB
5
0
-5
S
-10
22
S
11
-15
-20
0
20
40
60
Frequency, GHz
80
TWA with internal ft-doubler cells
UCSB
PK Sundararajan
75 GHz HBT master-slave latch UCSB
connected as Static frequency divider
Thomas Mathew
Hwe-Jong Kim
200 GHz Logic Program
re-fabricated 1999 (Q. Lee) UCSB design
In 1999 operated to 66 GHz limit of available sources
technology:
400 Å base, 2000 Å collector HBT
0.7 um mask (0.6 um junction) x 12 um emitters
1.5 um mask (1.4 um junction) x 14 um collectors
1.8105 A/cm2 operation, 180 GHz ft, 260 GHz fmax
simulations: 95 GHz clock rate in SPICE
test data to date:
tested, works over full 26-40 and 50-75 GHz bands
now testing in 75-110 GHz band (limited signal power)
3.92 V,
224 mA,
0.88 W
f =75GHz, f =37.5GHz
f =69GHz, f =34.5GHz
in
out
-0.03
0
-0.04
-0.02
-0.05
-0.04
Vout (Volts)
Vout(Volts)
in
-0.06
-0.07
out
~3.5 dBm input power
-0.06
-0.08
-0.08
-0.1
-0.09
-0.12
-0.1
modulation is synthesizer 6 GHz subharmonic
-0.14
-0.11
0
50
100
Time(PS)
150
200
0
50
100
Time(ps)
150
200
19 GHz adder-accumulator
UCSB
Thomas Mathew
Objectives:
40-60 GHz clock rate adder for 20 GHz DDS
Approach:
building blocks for a pipelined adder
Simulations:
40-60 GHz clock rate in SPICE
Significance:
Design to meet 20GHz DDS requirements
Status:
Component blocks built, working at 19 GHz
2 bit carry logic: f
max ck
= 19GHz
0
-0.05
Vout(Volts)
-0.1
-0.15
-0.2
-0.25
-0.3
0
100
200
300
Time(ps)
400
500
20 GHz S ADC
UCSB
S Jaganathan
ONR ADC Program
Design
comparator is 75 GHz flip flop
DC bias provided through 1 K resistors
Integration obtained with 3 pF capacitors
RTZ gated DAC
Integrated Circuit
150 HBTs, 1.2 x 1.5 mm, 1.5 W
Integrator-1
Integrator-2
Bias
Rz
Current
Summing
node
Vin
Bias
RL
RL
C
gm1
C
gm2
C
C
RL
RL
Rz
MasterSlave
Flip-flop
Clock
Bias
Bias
Delayed
Clock
Idac
Out
Submicron device scaling: towards THz bandwidths
Scaling drift-diffusion electron devices for 2 x increased speed:
2 x thinner layers, 4 x narrower junctions
4 x higher current density, 4 x improved vertical contacts
Results with submicron III-V HBT scaling:
300 GHz f , high (1100 GHz ?) fmax
Challenges with scaling:
power density, improved vertical contacts, breakdown
Opportunities:
aggressive parasitic reduction of III-V's (as in Silicon)
III-V HBT scaling to below 0.1 um
Prognosis:
much faster transistors, amplifiers, and logic
are still feasible
In Case of
Questions
Submicron Transferred-Substrate HBT
UCSB
Michelle Lee
S
21
/5
10 x S
12
S
S
22
11
measured
equivalent circuit
Why Mason’s Gain, U, is used to find fmax:
40
40
30
Gains, dB
MAG/MSG can
be above U
...above -20
dB/dec line
U
MAG/MSG
25
20
15
10
U
30
MAG/MSG
25
20
15
10
(CE, small Ccbx )
5
( CE, large Ccbx )
5
0
0
1
10
Frequency, GHz
100
40
U: all 3
35
30
Gains, dB
MAG/MSG can
be below U
…below -20
dB/dec line
35
Gains, dB
35
25
U is same for
CE , CB, & CC
MAG/MSG
common emitter
20
15
MAG/MSG
common base
10
5
MAG/MSG
common collector
10
Frequency, GHz
100
U is not changed by pad parasitics
U has -20 dB / decade slope to fmax
MSG slope is -10 dB / decade
MAG has no fixed slope
-for hybrid- model
comment: U is not given by:
0
1
1
10
Frequency, GHz
100
S 21
2
1  S 1  S 
2
11
Plots generated using HP / EESOF simulator and standard hybrid- model
2
22
Measuring High fmax Transistors I
DC-50 GHz & 75-110 GHz Network Analysis
waveguide-coupled micro-coax probes
Parasitic probe-probe coupling
S12 error background: not corrected by calibration
 gain measurements corrupted, worse for W-band
corrupted
W-band
measurement
Measuring High fmax Transistors II
Offset reference planes, on-wafer LRL calibration standards
separate probes to reduce coupling
reference planes at transistor terminals
230 m
230 m
Line-reflect-line on-wafer cal. standards
Lo+1275 m+Lo
20-60 GHz
LINE
Lo+560 m+Lo
75-110 GHz
LINE
Lo+Lo
20-60 GHz
Calibration standards
THROUGH
LINE
SHORT
Lo
Lo
75-110 GHz
Calibration standards
Calibration verification
OPEN (reflect)
DUT
Lo
Lo
Lo
Lo
V= 2.04 x 108 m/s
(r = 2.7)
Device under test
185 GHz Single-Stage Amplifier:
High fmax demonstration
6.2 Submicron HBT Program
also supported by AFOSR
• Single-stage reactively-tuned amplifier
at 185 GHz with 3.0 dB gain
• Gain-per-stage is comparable to
results from HEMT technologies
• Simple design to provide directions for
future work
Measured Gain
4
3
2
S21, dB
1
0
-1
-2
-3
-4
-5
140
150
160
170
180
190
Frequency, GHz
200
210
220
80
1.2ps
30
0.2ps
IN
OUT
80
1.2ps
50
• Future Work: Multi-stage amplifiers
with improved devices
50
0.2pF
30
1.2ps
50

0.6ps
Ultra-High fmax Transferred-Substrate HBTs
6.2 Submicron HBT Program
f max 
f / 8RbbCcb
• Sub-micron scaling of emitter and
collector widths has resulted in record
values for extrapolated fmax (1 THz)
25
MAG/MSG
20
Gain (dB)
• Transferred-substrate process results
in dramatic reduction in collector base
capacitance (Ccb)
15
U
10
h21
5
0
-5
1E10
1E11
1E12
Frequency (Hz)
• Improved E-beam lithography at
UCSB will allow more aggressive device
scaling
Sub-micron HBT measured from 0-50 GHz and
140-220 GHz
• Reduce base resistance with carbon
base doping and improved base
Ohmics
High speed device measurements require
careful attention to measurement and
calibration methodology
•Goal: Build the World’s Fastest
Electron Device