Single-stage G-band HBT Amplifier with
6.3 dB Gain at 175 GHz
M. Urteaga, D. Scott, T. Mathew, S. Krishnan, Y.
Wei, M. Rodwell.
Department of Electrical and Computer Engineering,
University of California, Santa Barbara
urteaga@ece.ucsb.edu 1-805-893-8044
GaAsIC 2001 Oct. 2001, Baltimore, MD
GaAs IC 2001
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Outline
UCSB
Introduction
Ultra-low parasitic InP HBT technology
Circuit design
Results
Conclusion
G-band Electronics (140-220 GHz)
Applications:
 Wideband communication systems
 Atmospheric sensing
 Automotive radar
Transistor-based ICs realized through submicron device scaling
State-of-the-art InP-based HEMT Amplifiers with submicron gate lengths
 3-stage amplifier with 30 dB gain at 140 GHz.
Pobanz et. al., IEEE JSSC, Vol. 34, No. 9, Sept. 1999.
 3-stage amplifier with 12-15 dB gain from 160-190 GHz
Lai et. al., 2000 IEDM, San Francisco, CA.
 6-stage amplifier with 20  6 dB from 150-215 GHz.
Weinreb et. al., IEEE MGWL, Vol. 9, No. 7, Sept. 1999.
HBT is a vertical-transport device (vs. lateral-transport)
Presents Challenges to Scaling
Transferred-Substrate HBTs
• Substrate transfer allows simultaneous
scaling of emitter and collector widths
Mesa HBT
• Maximum frequency of oscillation

f max 
f / 8RbbCcb
• Submicron scaling of emitter and collector
widths has resulted in record values of
measured transistor power gains
(U=20 dB at 110 GHz)
• Promising technology for ultra-high
frequency tuned circuit applications
This Work
 Single-stage tuned amplifier
with 6.3 dB gain at 175 GHz
 Gain-per-stage amongst
highest reported in this band
Transferred-substrate HBT
InAlAs/InGaAs HBT Material System
Layer Structure
Band Diagram
InGaAs 1E19 Si 1000 Å
Grade 1E19 Si 200 Å
InAlAs 1E19 Si 700 Å
InAlAs 8E17 Si 500 Å
Grade 8E17 Si 233 Å
Grade 2E18 Be 67 Å
InGaAs 4E19 Be 400 Å
InGaAs 1E16 Si 400 Å
2kT base bandgap grading
InGaAs 1E18 Si 50 Å
InGaAs 1E16 Si 2550 Å
InAlAs UID 2500 Å
S.I. InP
Bias conditions for the band diagram
Vbe = 0.7 V, Vce = 0.9 V
Transferred-Substrate Process Flow
• Emitter metal
• Emitter etch
• Self-aligned base
• Mesa isolation
• Polyimide planarization
• Interconnect metal
• Silicon nitride insulation
• Benzocyclobutene, etch vias
• Electroplate gold
• Bond to carrier wafer with solder
• Remove InP substrate
• Collector metal
• Collector recess etch
Ultra-high fmax Submicron HBTs
• Electron beam lithography used to define
submicron emitter and collector stripes
• Minimum feature sizes
 0.2 m emitter widths
 0.3 m collector widths
• Amplifier device dimensions:
 Emitter area: 0.4 x 6 m2
 Collector area: 0.7 x 6.4 m2
0.3 m Emitter before polyimide planarization
• Aggressive scaling of transistor
dimensions predicts progressive
improvement of fmax
As we scale HBT to <0.4 um,
fmax keeps increasing, device
measurements become very difficult
Submicron Collector Stripes
(typical: 0.7 um collector)
Device Measurements
RF Gains
RF Measurements:
U
• Unilateral power gain shows peaking
in DC-45 GHz band
MSG/MAG
• 75-110 GHz measurements corrupted
by excessive probe-to-probe coupling
MSG/MAG
h21
• Recent device measurements have
shown negative unilateral power gain in
W- and G- bands (2001 DRC, Notre
Dame)
h21
• Second-order device physics may be
important in ultra-low parasitic devices
Implications
Devices have extremely high power
gains in 140-220 GHz bands, but
fmax cannot be determined from
20 dB/decade extrapolation
• Bias Conditions: VCE = 1.2 V, IC = 4.8 mA
• Device dimensions:
 Emitter area: 0.4 x 6 m2
 Collector area: 0.7 x 6.4 m2
• f = 160 GHz
• DC properties:  = 20, BVCEO = 1.5 V
Amplifier Design
7.5
• Designed using hybrid-pi model
derived from DC-50 GHz
measurements of previous
generation devices
• Electromagnetic simulator
(Agilent’s Momentum) was used to
characterize critical passive
elements
S21
10
5.0
0
2.5
-10
S11,
S22
0.0
-20
-2.5
-30
-5.0
140
-40
150
160
170
180
190
200
210
220
Frequency, GHz
Schematic
50
0.2pF
• Shunt R-C network at output
provides low frequency stabilization
80
1.2ps
30
0.2ps
IN
OUT
80
1.2ps
50
30
1.2ps
50

0.6ps
S11, S22, dB
• Simulations predicted 6.2 dB gain
S21, dB
• Simple common-emitter design
conjugately matched at 200 GHz
Design Considerations in Sub-mmwave Bands
• Transferred-substrate technology provides
low inductance microstrip wiring environment
 Ideal for Mixed Signal ICs
• Advantages for MMIC design:
 Low via inductance
 Reduced fringing fields
• Disadvantages for MMIC design:
 Increased conductor losses
• Resistive losses are inversely proportional
to the substrate thickness for a given Zo
• Amplifier simulations with lossless matching
network showed 2 dB more gain
• Possible Solutions:
 Use airbridge transmission lines
 Find optimum substrate thickness
140-220 GHz VNA Measurements
• HP8510C VNA with Oleson
Microwave Lab mmwave Extenders
• GGB Industries coplanar wafer
probes with WR-5 waveguide
connectors
• Full-two port T/R measurement
capability
• Line-Reflect-Line calibration with
on-wafer standards
• Internal bias Tee’s in probes for
biasing active devices
UCSB 140-220 GHz VNA Measurement Set-up
Amplifier Measurements
8
• Measured 6.3 dB peak gain at 175 GHz
4
S21, dB
• Device dimensions:
 Emitter area: 0.4 x 6 m2
 Collector area: 0.7 x 6.4 m2
S21
6
2
0
• Device bias conditions:
 Ic= 4.8 mA, VCE = 1.2 V
-2
-4
140 150 160 170 180 190 200 210 220
Frequency, GHz
0
S22
S11, S22, dB
-4
-8
S11
-12
-16
Cell Dimensions: 690m x 350 m
-20
140 150 160 170 180 190 200 210 220
Frequency, GHz
Simulation vs. Measurement
7.5
Sim.
Meas.
5.0
• Peak gain measured at 175 GHz
2.5
• Possible sources for discrepancy:
S21, dB
• Amplifier designed for 200 GHz
 Matching network design
 Device model
0.0
-2.5
-5.0
140
150
160
170
180
190
200
210
220
Frequency, GHz
0
-5
S11,S22, dB
-10
-15
Meas.
-20
Sim.
-25
-30
-35
-40
140
150
160
170
180
190
Frequency, GHz
200
210
220
Matching Network Design
Matching Network Breakout
• Breakout of matching network without
Simulation Vs. Measurement
active device was measured on-wafer
• Measurement compared to circuit
simulation of passive components
• Simulation shows good agreement
with measurement
• Verifies design approach of combining
E-M simulation of critical passive
elements with standard microstrip
models
S11
S21
S22
freq (140.0GHz to 220.0GHz)
Red- Simulation
Blue- Measurement
Device Modeling I: Hybrid-Pi Model
• Design used a hybrid-pi device model
based on DC-50 GHz measurements
HBT Hybrid-Pi Model
Derived from DC-50 GHz Measurements
• Measurements of individual devices in
140-220 GHz band show poor
agreement with model
• Discrepancies may be due to
weakness in device model and/or
measurement inaccuracies
• Device dimensions:
 Emitter area: 0.4 x 6 m2
 Collector area: 0.7 x 6.4 m2
• Bias Conditions:
 VCE = 1.2 V, IC = 4.8 mA
1.59
17
43
45
0.4
7.0
9.5
281
0.60
76
0.126
Device Modeling II: Model vs. Measurement
• Measurements and simulations of device
from 6-45 GHz and 140-220 GHz
S21
• Large discrepancies in S11 and S22
• Anomalous S12 believed to be due to
excessive probe-to-probe coupling
-5
-4
-3 -2
-1
0
1
2
3
4
5
Red- Simulation
Blue- Measurement
S11, S22
S12
freq (140.0GHz to 220.0GHz)
freq (6.000GHz to 45.00GHz)
freq (6.000GHz to 45.00GHz)
freq (140.0GHz to 220.0GHz)
-0.15 -0.10 -0.05 0.00
0.05
0.10
freq (140.0GHz to 220.0GHz)
freq (6.000GHz to 45.00GHz)
freq (6.000GHz to 45.00GHz)
freq (140.0GHz to 220.0GHz)
0.15
Simulation vs. Measurement
device S-parameters in the 140-220 GHz
band
• Simulation shows good agreement with
measured amplifier results
• Results point to weakness in hybrid-pi
model used in the design
Simulation Using Measured Device S-parameters
7.5
Meas.
Sim.
5.0
S21, dB
• Simulated amplifier using measured
Simulation versus Measured Results
2.5
0.0
-2.5
• Improved device models are necessary
for better physical understanding but
measured S-parameter can be used in
future amplifier designs
-5.0
140
150
160
170
180
190
200
210
220
Frequency, GHz
0
-5
Meas.
S11,S22, dB
-10
-15
Sim.
-20
-25
-30
-35
-40
140
150
160
170
180
190
Frequency, GHz
200
210
220
Multi-stage Amplifier Design
Simulation Results
• Three-stage amplifier designed using
measured transistor S-parameters
30
• Simulated 20 dB gain at 175 GHz
10
S21 (dB)
• Design currently being fabricated
20
0
-10
-20
-30
140 150 160 170 180 190 200 210 220
Multi-stage amplifier layout
S11,S22 (dB)
Freq (GHz)
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
140 150 160 170 180 190 200 210 220
Freq (GHz)
GaAs IC 2001
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Conclusions
UCSB
Single-stage HBT amplifier with 6.3 dB at 175 GHz
Simple design provides direction for future high frequency MMIC work in
transferred-substrate process
Observed anomalies in extending hybrid-pi model to higher frequencies
Future Work
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Multi-stage amplifiers and oscillators
Improved device performance for higher frequency operation
Acknowledgements
This work was supported by the ONR under grant N0014-99-1-0041
And the AFOSR under grant F49620-99-1-0079