Project: PDA Smart Car Integration via Bluetooth
Team: Team Blue
Members: Sharad Desai, Mahmoud Toure, Lochan KC
Agenda
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Points to be covered
 System Overview
 Detailed Design Specifications
 Software Processes
 Test Results
 Parts List
 Updated Schedule
 Updated Division of Labor and Responsibilities
6/27/2016
University of Colorado -- Boulder
2
System Overview -- Revisions
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
After PDR, we have made some modifications to our project (all
add-ons)
 Add proximity sensors which offer info on obstacles
 Give an external display using an LCD to display such data
 Add a keypad which will allow the LCD to act as a menu
6/27/2016
University of Colorado -- Boulder
3
System Overview -- Block Diagram
Agenda
Overview
6/27/2016
Design Specs
Software Processes
University of Colorado -- Boulder
Parts List
Schedule
Labor
Questions
4
Detailed Design Specs – Comm. Protocol
Agenda
Overview
Design Specs
Command (ASCII)
6/27/2016
Software Processes
Parts List
Schedule
Labor
Questions
Description
A
Door Unlock
B
Door Lock
C
Windows Roll-up
D
Windows Roll-down
E
Trunk Open
F
Headlight On
G
Remote Start
H
Custom Feature
University of Colorado -- Boulder
5
Detailed Design Specs – LCD
Agenda





Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
CFA-634 Serial LCD (Crystalfontz)
20 columns by 4 rows
White edge LED backlight
DB9 connector for simple RS-232
Supports 19200, 9600, 4800 and
2400 baud
6/27/2016
University of Colorado -- Boulder
6
Detailed Design Specs – Keypad
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
 Grayhill – 96BB2-056-F
 4 x 4 inches
 Matrix circuitry
6/27/2016
University of Colorado -- Boulder
7
Detailed Design Specs – Keypad
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Schematic
6/27/2016
University of Colorado -- Boulder
8
Detailed Design Specs – T-Mobile Dash
Agenda




Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Microsoft Windows Mobile 5
32 bit Texas Instrument OMAP 850
ROM capacity 128 Mb (accessible:77Mb)
RAM capacity 64 Mb(accessible:44Mb)
6/27/2016
University of Colorado -- Boulder
9
Detailed Design Specs – Bluetooth Rec.
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
WRL-00582
 Class 1 Bluetooth Radio Modem(Range 100m)
 Low power consumption : 82.5mW
 Encrypted connection
 Frequency: 2.4~2.524 GHz
 Operating Voltage: 3.3V-6V
 Serial communications: 2400-115200bps
 Built-in antenna
WRL-00582 - Bluetooth Modem
6/27/2016
University of Colorado -- Boulder
10
Detailed Design Specs – Bluetooth Rec.
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Schematic
Figure 3
Bluetooth Receiver Schematic
6/27/2016
University of Colorado -- Boulder
11
Detailed Design Specs – Sensor
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Sharp GP2D12 IR Sensor
 10-80cm (4”-32”) range
 Simple 4-wire I2C interface
 Request data in cm, inches or raw analog
(ie: 0-255)
 User-selectable device addressing
 Technical Data:
6/27/2016
University of Colorado -- Boulder
12
Detailed Design Specs – Sensor
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Schematic
Figure 2
Sensor Schematic
6/27/2016
University of Colorado -- Boulder
13
Detailed Design Specs – I2C CP
Agenda




Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Send a start sequence
Send I2C address of the slave w/ R/W bit (20)H
Read data byte from IR sensor
Send the stop sequence
6/27/2016
University of Colorado -- Boulder
14
Detailed Design Specs – Power System
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
The main control unit will be powered by the car battery
 The system will need 5 different voltage levels:
 12 V Relay
 5V for LCD and I2C device
 3.3V, 2.5V and 1.3V for FPGA
 200kHz Simple 3A Buck Regulator (MIC4576) – 5V
 Voltage Regulator (FAN1086M33) – 3.3V
 Voltage Regulator (LD1085D2M25R) – 2.5V
 Voltage Regulator (APII22EG-13) – 1.3V
6/27/2016
University of Colorado -- Boulder
15
Detailed Design Specs – Power System
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
K
uF
K
D
N
G
D
1.5
D
N
G
D
F
u
5V_FPGA
D
N
G
D
0
0
0
1
C200
D
N
G
D
D
N
G
D
D
N
G
D
D
N
G
D
D
N
G
D
2
3
D
R
MIC4576WT
2
2
50V
47uF
N
D
H
S
C501
5
B
F
4.7
4
uF
0.1
4.7
5
R
D
N
G
1
1
3
uF
4.7
6.8V
8
C
C13
H
u
8
6
2
C
NET00017
W
S
VIN
2
1
2
1
5V_FPGA
V
2
1
+
1
U
8
4
L
D
N
G
D
1
D
B360A-13-F
Schematic
Figure 1
200KHz Buck Regulator
6/27/2016
University of Colorado -- Boulder
16
Detailed Design Specs – MCU
Agenda





Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
500K-gate Xilinx Spartan 3E FPGA (XC3S500E-4PQG208C)
4Mb Xilinx XCF02S Platform Flash PROM
50MHz Crystal oscillator
RS-232 transceiver/level translator (using MAX3232)
2 DB9 9-pin female connector
6/27/2016
University of Colorado -- Boulder
17
Detailed Design Specs – MCU
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Schematic
Figure 3
XCFO2 to FPGA
6/27/2016
University of Colorado -- Boulder
18
6/27/2016
D
9
Connector
D
1
6
2
1
1
1
7
6
3
0
1
2
8
7
University of Colorado -- Boulder
D
N
9
8
5
4
9
?
J
5
?
J
D
N
G
D
MAX232D
D
N
G
D
D
N
G
D
N
G
D
5
1
uF
0.1
R2OUT
R2IN
D
N
R1OUT
R1IN
uF
0.1
2
1
3
1
T2OUT
T2IN
7
0
1
T1OUT
T1IN
uF
0.1
C123
4
1
1
1
VS-
C2-
C123
6
5
VS+
C2+
2
4
C1-
C123
3
C
C
V
C1+
6
1
1
6
U
Parts List
G
D
9
8
Software Processes
G
D
4
3
0
1
C123
Design Specs
N
9
Connector
D
1
1
uF
0.1
Overview
G
D
D
N
C123
Agenda
G
D
uF
0.1
Detailed Design Specs – MCU
Schedule
Labor
Questions
Figure 4
DB9 Connector to FPGA
19
Detailed Design Specs – Relay Driver
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
V
2
1
8
Q91
1N4148
Q90
2
V
R
D
CONTACT2:2
4
1
BSS138LT1G
KL2A
NET00516
D
N
G
D
D138
3
8
1
3
2
+
KL2B
CONTACT2:1
1
V
R
D
1
BSS138LT1G
CONTACT1:2
4
NET00517
D
N
G
D
KL1A
1N4148
1
D139
3
2
+
3
KL1B
+
CONTACT1:1
Agenda
6/27/2016
University of Colorado -- Boulder
20
D
N
G
D
N
G
D
D
N
D
*
3
F
O
E
T
A
D
*
*
0
0
0
0
1
0
0
C41
1
ENGINEERING
DOCUMENTATION
T
E
E
H
S
V
E
R
E
T
A
D
A
DIAGRAM
SCHEMATIC
Bead
Ferrite
*
*
1.3V_FPGA_VCC_INT
2
1
0
7
1
9
6
4
1
7
3
2
6
4
8
3
1
1
1
1
1
1
2
1
1
1
1
1
5
3
L
6
1
9
6
4
8
7
7
Vccint
Vccint
Vccint
Vccint
VccAux
VccAux
VccAux
VccAux
VccAux
VccAux
VccAux
VccAux
Vcco
Vcco
Vcco
Vcco
Vcco
Vcco
Vcco
Vcco
Vcco
Vcco
Vcco
Vcco
XC3S500E-4PQG208C
NET00003
B
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
5
1
1
1
6
3
2
8
8
8
0
7
7
7
2
3
0
9
5
5
0
2
3
4
5
7
8
8
9
0
1
1
2
3
5
5
7
7
8
9
1
1
1
1
1
1
1
1
1
2
D
N
G
D
B
NET00287
OUTPUT8
4
D48
KL8A
KL8B
3
+
1
+
J
C
C
V
0
2
D
CLK
D
R
1N4148
8
1
3
V
2
7
Q39
0
1
uF
0.1
C137
3
O
C
C
V
9
1
0
D
1
3.3_FPGA_VCC_OUT
VCCINT
1
8
1
Q94
BSS138LT1G
U45
NET00171
D
N
4
C\E\
G
D
N
G
D
TDI
I
D
T
3
1
D
5
C\E\O\
N
2
FPGA_TMS
S
M
T
8
FPGA_DIN_DEBUG28
G
6
OE/R\E\S\E\T\
CCLK_DEBUG27
D
D
FPGA_TCK
K
C
T
7
FPGA_DONE
V
1
BSS138LT1G
1
1
C\F\
FPGA_PROGRAM_N
8
NET00094
D
N
G
7
1
FPGA_INIT
V
R
D
XCF04SVOG20C
O
D
T
FPGA_TDI
D
N
G
D
OUTPUT7
4
D42
R172
C
KL7A
FPGA_MASTER_CLOCK
2
16V
10uF
2
C303
+
R173
KL7B
3
1
C12
3.3_FPGA_VCC_OUT
0
0
R175
4
5
1
+
D
J
D
A
IP_B2
3.3_FPGA_VCC_OUT
T
U
O
IN
1
0
2
3
BSS138LT1G
I/O_B1
KL6A
0
IP_B3
1
5
REG
3.3V
I/O_B1
FAN1086M33
1N4148
K
4.7
8
1
3
K
4.7
2
1
0
0
K
4.7
1
1
1
9
8
7
6
4
3
1
0
9
3
2
0
8
7
6
5
4
2
1
9
8
5
4
3
2
8
7
9
9
9
9
9
9
9
9
8
8
8
8
7
7
7
7
7
7
7
6
6
6
6
6
6
5
5
V
2
6
V
R
I/O_B2
IP_B2
I/O_B2
I/O_B2
I/O_B2_VREF
I/O_B2
I/O_B2
I/O_B2
I/O_B2
IP_B2
I/O_B2
I/O_B2
I/O_B2
I/O_B2
IP_B2
I/O_B2
I/O_B2
I/O_B2
I/O_B2
I/O_B2
IP_B2_VREF
IP_B2
I/O_B2
I/O_B2
I/O_B2
I/O_B2
I/O_B2
I/O_B2
IP_B2
IP_B2
OUTPUT6
I/O_B1
4
Q78
7
1
6
1
0
1
8
NET00518
I/O_B3
3.3VF
D
0
5
I/O_B1
3
0
1
5
U
I/O_B3
9
4
I/O_B3
8
4
1
+
+
I/O_B3
7
4
I/O_B1
1
1
I/O_B3_VREF
5
4
I/O_B1_VREF
D
D
N
G
D
D
N
G
D
1
1
IP_B3
3
4
1
I/O_B3
2
4
2
16V
10uF
I/O_B3
2
16V
10uF
1
4
C310
OUTPUT5
4
C312
NET00514
I/O_B3
D
uF
0.1
IP_B1
KL5A
1
1
1
I/O_B3
1
C311
1
I/O_B3
6
3
D
+
I/O_B3
D
N
G
5
3
D
1.3V_FPGA_VCC_INT
T
U
O
IN
4
3
2
3
1
+
I/O_B3
3
3
AP1122EG-13
1
IP_B3
2
3
BSS138LT1G
Q86
1.3V1
I/O_B3
NET00511
1
3
I/O_B3
0
3
D
I/O_B3
D
9
2
D
D
N
G
D
D
N
G
D
D
N
G
D
I/O_B3
8
2
2
4
+
IP_B3
6
2
IP_B1
2
16V
10uF
KL4A
3
1
2
I/O_B3
C304
5
2
C217
uF
0.1
1
I/O_B1
uF
0.1
XC3S500E-4PQG208C
C
1
4
2
1
I/O_B1
5
C
3
1
1
I/O_B3
3
2
I/O_B1
NET00515
3
1
D
I/O_B3
2
2
J
D
A
I/O_B1
3
1
IP_B3_VREF
2.5V_FPGA_VCC_INT
T
U
O
IN
5V_FPGA
2
3
I/O_B3
4
9
1
+
I/O_B3
REG
2.5V
KL3A
8
1
LD1085D2M25R
I/O_B1
3
1
I/O_B3
D
D
N
G
1N4148
D135
9
IP_B1
8
1
3
2
0
1
1
V
2
KL6B
2
5
V
R
D
3
I/O_B1
Q87
BSS138LT1G
5
1
1
I/O_B1
6
1
1
D
N
G
0
4
1N4148
D150
8
9
3
I/O_B1
8
1
3
2
9
1
1
3
I/O_B1
0
2
1
4
V
R
KL5B
I/O_B1
I/O_B3
2
2
1
V
2
I/O_B1_VREF
3
2
1
IP_B1
4
2
1
Q89
I/O_B1
6
2
1
1N4148
D136
I/O_B1
7
2
1
D
N
G
I/O_B1
D
N
G
8
2
1
D
N
G
D
N
G
I/O_B1
9
2
1
CONTACT4:2
8
1
3
3
V
R
D
KL4B
0
2
3
1
Q37
BSS138LT1G
I/O_B3
6
3
3
U39A
4
D
N
G
CONTACT4:1
1N4148
D151
5
0
2
CONTACT3:2
8
1
3
2
IP_B1_VREF
6
3
1
KL3B
7
D
N
uF
0.1
1
D
N
G
D
5V_FPGA
16V
10uF
N
uF
0.1
C11
5V_FPGA
G
C299
1
G
D
D
N
G
D
16V
10uF
6
1
2.5V
I/O_B1
4
U
8
3
1
2
V
R
D
I/O_B3
8
V
R
D
3
5
1
I/O_B1
K
1.5
9
3
1
IP_B3
4
1
I/O_B1
D
N
G
D
0
4
1
F
CONTACT3:1
I/O_B3
1
2
1
E
IP_B1
4
1
Q90
BSS138LT1G
2
I/O_B3
6
V
R
1
D
0
7
0
V
0
R
5V_FPGA
D
N
G
D
D
u
C200
D
N
G
D
1
1
D
N
G
D
D
N
G
D
I/O_B1
D
N
G
D
D
N
G
D
4
4
1
I/O_B3
5
V
R
D
9
2
3
NET00516
I/O_B1
D
D
N
G
D
R
5
4
1
MIC4576WT
CONTACT2:2
I/O_B3
4
V
R
D
4
1N4148
D138
8
I/O_B1
2
2
6
4
1
IP_B3
N
D
H
S
C501
KL2A
6
5
I/O_B1
8
1
3
2
7
4
1
I/O_B3_VREF
B
F
+
5
uF
4.7
4
uF
0.1
IP_B1
K
4.7
5
R
D
N
G
1
1
8
4
1
3
uF
4.7
6.8V
KL2B
I/O_B3
3
V
R
D
3
4
8
C
C13
1
V
R
D
I/O_B1
0
5
1
H
u
8
6
2
C
I/O_B3
2
V
R
D
3
I/O_B1
1
5
1
NET00017
CONTACT2:1
I/O_B3
1
V
R
D
W
S
VIN
I/O_B0_VREF
I/O_B0_VREF
I/O_B0_VREF
I/O_B0_VREF
I/O_B0_VREF
1
2
2
1
2
1
I/O_B1
5V_FPGA
V
2
1
+
Q91
BSS138LT1G
2
5
1
1
U
8
4
L
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B0
I/O_B1
IP_B0
IP_B0
IP_B0
IP_B0
IP_B0
IP_B0
IP_B0
IP_B0
3
5
1
CONTACT1:2
4
NET00517
IP_B1
D
N
G
D
4
5
1
9
0
1
2
3
4
5
7
8
9
1
2
4
5
7
8
9
0
1
3
4
5
6
7
9
0
2
3
4
6
7
9
0
2
3
4
5
KL1A
1N4148
D139
5
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
9
9
9
9
9
9
9
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
D
N
G
D
8
1
3
2
3
+
1
D
B360A-13-F
KL1B
CONTACT1:1
V
2
1
+
D
N
G
D
D
N
G
D
D
N
G
D
D
N
G
D
D
N
G
D
9
Connector
D
Bead
Ferrite
JP4
2
1
9
Connector
D
1
K
4.7
R168
K
15
6
NET00887
2
1
1
1
2
1
C497
7
6
JP3
2
1
3
0
1
2
1
1
0
5
L
K
4.7
R169
8
7
F
F
2
uF
0.1
p
p
D
N
G
D
50MHz
0
0
4
3
0
1
0
0
0
0
9
8
uF
0.1
JP2
3.3_FPGA_VCC_OUT
16V
10uF
1
1
2
1
R219
5
4
K
4.7
R170
C16
C10
9
C
N
D
N
G
?
J
1
C124
1
4
5
C178
?
J
Bead
Ferrite
uF
0.1
XC3S500E-4PQG208C
NET00886
D
N
G
D
5V_FPGA
Vcc
Output
1
2
8
5
K
10
R171
G
9
L
C123
IO/DIN
FPGA_DIN_DEBUG28
7
8
U49
F
p
0
3
3
FPGA_M0
IO/M0
6
8
MAX232D
E
N
O
D
FPGA_DONE
4
0
1
D
N
G
D
FPGA_M1
IO/M1
D
N
G
4
8
D
N
G
D
5
1
CCLK
CCLK_DEBUG27
FPGA_MASTER_CLOCK
3
0
1
uF
0.1
FPGA_M2
GCLK1/M2
R2OUT
R2IN
1
8
C61
D
N
G
D
9
8
R1OUT
R1IN
NET00931
uF
0.1
2
1
3
1
uF
0.1
CSI_B
T2OUT
T2IN
R
K
R
M
1
6
7
0
1
TMS
FPGA_TMS
T1OUT
T1IN
5
5
1
uF
0.1
C123
4
1
1
1
NET00934
DOUT/BUSY
BUSY
TDO
FPGA_TDO
VS-
C2-
0
6
7
5
1
C123
6
5
C123
VS+
C2+
2
4
FPGA_INIT
INIT_B
TCK
FPGA_TCK
C1-
6
5
8
5
1
C123
3
C
C
V
C1+
NET00457
6
1
1
CS0_B
HSWAP
G
5
5
6
0
2
6
U
K
4.7
R488
1
2
3
FPGA_PROGRAM_N
PROG_B
1
TDI
FPGA_TDI
7
0
2
3.3_FPGA_VCC_OUT
U39B
4
5
6
7
8
Schedule
2
*
NAME
FILE
*
p
p
C54
C252
C253
C181
C251
2.5V_FPGA_VCC_INT
NET00497
7
5
6
9
1
0
9
7
4
2
1
5
4
3
2
2
50V
47uF
F
Parts List
*
DESIGN
F
F
C175
C142
C136
C123
C134
C122
1
1
6
3
5
4
9
6
8
1
U39C
D
N
G
D
D
N
G
D
E
Software Processes
DOCUMENT
TO
NOT
D
N
uF
0.1
uF
0.1
uF
0.1
uF
0.1
C135
3.3_FPGA_VCC_OUT
D
Design Specs
SCALE
D
N
G
D
N
G
D
D
N
G
D
D
N
G
G
University of Colorado -- Boulder
D
uF
0.1
uF
0.1
uF
0.1
uF
0.1
uF
0.1
uF
0.1
C133
C121
C132
C120
C131
C119
C130
C129
C118
C
Overview
G
D
uF
0.1
uF
0.1
uF
0.1
uF
0.1
uF
0.1
uF
0.1
uF
0.1
uF
0.1
uF
0.1
uF
0.1
B
Agenda
D
6/27/2016
D
A
Detailed Design Specs – Rev 1 Schema
Labor
Questions
21
Software Processes
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Block Diagram
6/27/2016
University of Colorado -- Boulder
22
Software Processes – Implementation
Agenda
Overview
6/27/2016
Design Specs
Software Processes
University of Colorado -- Boulder
Parts List
Schedule
Labor
Questions
23
Software Processes – UART
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Schematic
Figure: UART
6/27/2016
University of Colorado -- Boulder
24
Software Processes – 8bit Comparator
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Schematic
6/27/2016
University of Colorado -- Boulder
25
Software Processes – Keypad Scan
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Schematic
6/27/2016
University of Colorado -- Boulder
26
Software Processes – I2C Master
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Schematic
6/27/2016
University of Colorado -- Boulder
27
Software Processes – UI Code
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Private Sub Form1_Load(ByVal sender As System.Object, ByVal e As System.EventArgs) Handles MyBase.Load
'Team Blue
'Loading the main for of the API and setting the bluetooth connection
' UI coding
Try
' October 9/2008
cli.Connect(ep)
Imports InTheHand.Net
peerStream = cli.GetStream()
Imports InTheHand.Net.Bluetooth
Catch es As NullReferenceException
Imports InTheHand.Net.Sockets
MessageBox.Show("Connection to the receiver Failed")
Imports System.IO
End Try
Imports System.Net.Sockets
End Sub
Imports System.Text
Imports InTheHand.Net.Sockets.BluetoothClient
End Class
Imports Microsoft.VisualBasic
Public Class Form1
Dim addr As BluetoothAddress = BluetoothAddress.Parse("00066600D722") ‘Address of the bluettooth Receiver
' Variable holding the ASCI values
Dim a As Byte = Asc("a")
Dim b As Byte = Asc("b")
Dim c As Byte = Asc("c")
' Set the right serial port COM
Dim ep As New BluetoothEndPoint(addr, BluetoothService.SerialPort)
Dim cli As New BluetoothClient
Dim peerStream As Stream
' Roll Down Windows
Private Sub RollDown_Click(ByVal sender As System.Object, ByVal e As System.EventArgs) Handles RollDown.Click
peerStream.WriteByte(b)
End Sub
'Turn on headlights
Private Sub TurnonH_Click(ByVal sender As System.Object, ByVal e As System.EventArgs) Handles TurnonH.Click
peerStream.WriteByte(c)
End Sub
' unlock doors
Private Sub door_Click(ByVal sender As System.Object, ByVal e As System.EventArgs) Handles door.Click
peerStream.WriteByte(a)
End Sub
'Close connection
Private Sub Close_Click(ByVal sender As System.Object, ByVal e As System.EventArgs) Handles Close.Click
cli.Close()
Me.Dispose()
End Sub
6/27/2016
University of Colorado -- Boulder
28
Parts List
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Comprehensive parts list:
 Sharp GP2D12 IR Sensor
 WRL-00582 (Bluetooth module)
 Xilinx Spartan 3E 500K FPGA
 RS-232 transceiver/level translator (using MAX3232)
 2 DB9 9-pin female connector
 Relay (all components)
 CFA-634 Serial LCD
 Keypad
 Door panel
 Any circuit components (ie: resistors, capacitors, etc.)
6/27/2016
University of Colorado -- Boulder
29
Updated Schedule
Agenda
Overview
6/27/2016
Design Specs
Software Processes
University of Colorado -- Boulder
Parts List
Schedule
Labor
Questions
30
Updated Schedule
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Here are the deliverables for each Milestone
 Milestone I
 First revision of PCB working
 Correct API functionality
 Correct relay driver functionality
 Milestone II
 Proximity sensors working
 Correct integration of sensors and LCD
 Final Design Expo
 Integration of car functions with the above functionality
6/27/2016
University of Colorado -- Boulder
31
Updated Division of Labor/Responsibilities
Agenda
Overview
Design Specs
Software Processes
Parts List
Schedule
Labor
Questions
Since PDR, we have accomplished the following tasks:
 Setting up communication between Bluetooth modules
 Writing FSM on FPGA
 Building relay driver
 Writing API (UI still pending)
 Building power supply
The following tasks are still pending:
 Sharad Desai
 Coding LCD
 Lochan KC
 Integrating with I2C
 Building PCB board
 Mahmoud Toure
 Writing UI and LCD
6/27/2016
Documentation!
University of Colorado -- Boulder
32
Questions and Comments
Agenda
Overview
6/27/2016
Design Specs
Software Processes
University of Colorado -- Boulder
Parts List
Schedule
Labor
Questions
33