Lecture 21
OUTLINE
The MOSFET (cont’d)
• P-channel MOSFET
• CMOS inverter analysis
• Sub-threshold current
• Small signal model
Reading: Pierret 17.3; Hu 6.7, 7.2
P-Channel MOSFET
• The PMOSFET turns on when VGS < VT
– Holes flow from SOURCE to DRAIN
 DRAIN is biased at a lower potential than the SOURCE
VG
VS
• VDS < 0
VD
GATE
P+
ID
P+
N
VB
• IDS < 0
• |IDS| increases with
• |VGS - VT|
• |VDS| (linear region)
• In a CMOS technology, the PMOS & NMOS threshold
voltages are usually symmetric about 0, i.e. VTp = -VTn
EE130/230A Fall 2013
Lecture 21, Slide 2
Long-Channel PMOSFET I-V
• Linear region:
I DS
0  VDS 
VGS  VTp
m
W
m
  Coxe  p ,eff (VGS  VTp  VDS )VDS
L
2
• Saturation region:
I DS  I Dsat
VDS 
VGS  VTp
m
W

Coxe  p ,eff (VGS  VTp ) 2
2mL
m = 1 + (3Toxe/WT) is the bulk-charge factor
EE130/230A Fall 2013
Lecture 21, Slide 3
CMOS Inverter: Intuitive Perspective
SWITCH MODELS
VDD
VDD
CIRCUIT
VDD
G
S
Rp
D
VOUT = 0V
VOUT = VDD
VOUT
VIN
D
G
S
Low static power consumption, since
one MOSFET is always off in steady state
EE130/230A Fall 2013
Rn
VIN = VDD
Lecture 21, Slide 4
VIN = 0V
Voltage Transfer Characteristic
N: sat
P: sat
VOUT
N: off
P: lin
VDD
C
N: sat
P: lin
A
B
D
E
N: lin
P: sat
N: lin
P: off
0
0
EE130/230A Fall 2013
VDD
Lecture 21, Slide 5
VIN
CMOS Inverter Load-Line Analysis
VIN = VDD + VGSp
IDn=-IDp
increasing
VIN
VIN = 0 V
–
VOUT = VDD + VDSp
VDSp=VOUT-VDD
+
VIN = VDD
IDn=-IDp
increasing
VIN
0
VDD
0
VDSp = - VDD
EE130/230A Fall 2013
VDSp = 0
Lecture 21, Slide 6
VOUT=VDSn
Load-Line Analysis: Region A
–
IDn=-IDp
VDSp=VOUT-VDD
VIN  VTn
+
IDn=-IDp
0
VDD
0
EE130/230A Fall 2013
Lecture 21, Slide 7
VOUT=VDSn
Load-Line Analysis: Region B
–
IDn=-IDp
VDSp=VOUT-VDD
+
IDn=-IDp
VDD/2 > VIN > VTn
0
VDD
0
EE130/230A Fall 2013
Lecture 21, Slide 8
VOUT=VDSn
Load-Line Analysis: Region D
–
IDn=-IDp
VDSp=VOUT-VDD
+
IDn=-IDp
VDD – |VTp| > VIN > VDD/2
0
VDD
0
EE130/230A Fall 2013
Lecture 21, Slide 9
VOUT=VDSn
Load-Line Analysis: Region E
–
IDn=-IDp
VDSp=VOUT-VDD
VIN > VDD – |VTp|
+
IDn=-IDp
0
VDD
0
EE130/230A Fall 2013
Lecture 21, Slide 10
VOUT=VDSn
MOSFET Effective Drive Current, IEFF
M. H. Na et al., IEDM Technical Digest, pp. 121-124, 2002
CMOS inverter chain:
V1
V2
V3
VDD
CMOS VDD
S
inverter:
D
VIN
D
GND
VOUT
S
NMOS DRAIN CURRENT
VDD/2
IH + IL
IEFF =
2
V2 t
V3
pLH
V1 tpHL
TIME
IH
VIN = VDD
IL
0.5VDD
NMOS DRAIN VOLTAGE = VOUT
EE130/230A Fall 2013
IDsat
Lecture 21, Slide 11
VIN = ½VDD
VDD
Propagation Delay, td
CMOS inverter chain:
C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Fig. 6-20
VDD
Voltage waveforms:
VDD
1
CVDD
t d  t pHL  t pLH  
2
I EFF
td is reduced by increasing IEFF and reducing load capacitance C
EE130/230A Fall 2013
Lecture 21, Slide 12
Sub-Threshold Current
• For |VG| < |VT|, MOSFET current flow is limited by carrier
diffusion into the channel region.
• The electric potential in the channel region varies linearly with
VG, according to the capacitive voltage divider formula:
Coxe
1
VC 
VG  VG
Coxe  Cdep
m
• As the potential barrier to diffusion increases linearly with
decreasing VG, the diffusion current decreases exponentially:
I DS  e
EE130/230A Fall 2013
qVG / mkT
Lecture 21, Slide 13
Sub-Threshold Swing, S
1
 d (log 10 I DS ) 

S  
dVGS


Cdep,min
kT

ln (10)(1 
)
q
Coxe
log ID
NMOSFET Energy Band Profile
increasing E
n(E)  exp(-E/kT)
Source
increasing
VGS
Drain
distance
EE130/230A Fall 2013
Lecture 21, Slide 14
Inverse slope is
subthreshold swing, S
[mV/dec]
0 VT
VGS
VT Design Trade-off
• Low VT is desirable for high ON current:
IDsat  (VDD - VT)
1<<2
• But high VT is needed for low OFF current:
log ID
Low VT
 VT cannot be
aggressively reduced!
High VT
IOFF,low VT
IOFF,high VT
0
EE130/230A Fall 2013
VGS
Lecture 21, Slide 15
How to minimize S?
Cdep,min
kT
S
ln (10)(1 
)
q
Coxe
EE130/230A Fall 2013
Lecture 21, Slide 16
MOSFET Small Signal Model
(Saturation Region)
• Conductance parameters:
low-frequency:
high-frequency:
A small change in VG or VDS will result
in a small change in ID
id  g d vd  g m vg
gd 
I D
VD
I D
gm 
VG
R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.12
EE130/230A Fall 2013
Lecture 21, Slide 17
 I Dsat0
VG  const

VD  const
W eff Coxe
mL
(VGS  VT )
Parasitic Components
EE130/230A Fall 2013
Lecture 21, Slide 18
R.S. Muller & T.I. Kamins, Device Electronics for Integrated Circuits, Fig. 8.12
MOSFET Cutoff Frequency, fT
The cut-off frequency fT is defined as the frequency when the
current gain is reduced to 1.
input current = j CG vG
output current = g m vG
vG here is ac signal
CG is approximately equal to the
gate capacitance,  W L Cox
g m vG
 1
At the cutoff frequency (T = 2fT):
2 fT  CG vG
eff
gm
fT 

(VGS  VT )
2
2Coxe 2mL
 Higher MOSFET operating frequency is achieved by
decreasing the channel length L
EE130/230A Fall 2013
Lecture 21, Slide 19