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Lecture 17 OUTLINE • The MOS Capacitor (cont’d) – Small-signal capacitance (C-V characteristics) Reading: Pierret 16.4; Hu 5.6 MOS Capacitance Measurement C-V Meter iac vac EE130/230A Fall 2013 MOS Capacitor GATE Semiconductor Lecture 17, Slide 2 • VG is scanned slowly • Capacitive current due to vac is measured dvac iac C dt dQGATE dQs C dVG dVG MOS C-V Characteristics (p-type Si) accumulation depletion inversion VG VFB VT dQs C dVG Qinv C slope = -Cox Cox Ideal C-V curve: VG VFB accumulation EE130/230A Fall 2013 Lecture 17, Slide 3 VT depletion inversion Capacitance in Accumulation (p-type Si) • As the gate voltage is varied, incremental charge is added (or subtracted) to (or from) the gate and substrate. The incremental charges are separated by the gate oxide. M O S DQ Q dQacc C Cox dVG -Q DQ Cox EE130/230A Fall 2013 Lecture 17, Slide 4 Flat-Band Capacitance (p-type Si) • At the flat-band condition, variations in VG give rise to the addition/subtraction of incremental charge in the substrate, at a depth LD – LD is the “extrinsic Debye Length,” a characteristic screening distance, or the distance where the electric field emanating from a perturbing charge falls off by a factor of 1/e LD Cox CDebye EE130/230A Fall 2013 Si kT q2 N A 1 1 LD CFB Cox Si Lecture 17, Slide 5 Capacitance in Depletion (p-type Si) • As the gate voltage is varied, the depletion width varies. Incremental charge is effectively added/subtracted at a depth W in the substrate. M DQ Q O S C W dQdep dVG 2(VG VFB ) 1 2 qN A Si Cox DQ -Q 1 1 1 1 W C Cox Cdep Cox Si Cox Cdep EE130/230A Fall 2013 Lecture 17, Slide 6 Capacitance in Inversion (p-type Si) CASE 1: Inversion-layer charge can be supplied/removed quickly enough to respond to changes in gate voltage. Incremental charge is effectively added/subtracted at the surface of the substrate. DQ M O S WT Time required to build inversion-layer charge = 2NAto/ni , where to = minority-carrier lifetime at surface DQ dQinv C Cox dVG Cox EE130/230A Fall 2013 Lecture 17, Slide 7 Capacitance in Inversion (p-type Si) CASE 2: Inversion-layer charge cannot be supplied/removed quickly enough to respond to changes in gate voltage. Incremental charge is effectively added/subtracted at a depth WT in the substrate. 1 1 1 C Cox Cdep DQ M O S WT DQ Cox Cdep EE130/230A Fall 2013 1 WT Cox Si 1 2(2F ) 1 Cox qN A Si C min Lecture 17, Slide 8 Supply of Substrate Charge (p-type Si) Accumulation: Inversion: EE130/230A Fall 2013 Depletion: Case 1 Lecture 17, Slide 9 Case 2 C. C. Hu, Modern Semiconductor Devices for ICs, Figure 5-17 MOS Capacitor vs. MOS Transistor C-V (p-type Si) C MOS transistor at any f, MOS capacitor at low f, or quasi-static C-V Cmax=Cox CFB MOS capacitor at high f Cmin accumulation EE130/230A Fall 2013 VFB depletion Lecture 17, Slide 10 VT inversion VG Quasi-Static C-V Measurement (p-type Si) C Cmax=Cox CFB Cmin accumulation VFB depletion VT inversion VG The quasi-static C-V characteristic is obtained by slowly ramping the gate voltage (< 0.1V/s), while measuring the gate current IG with a very sensitive DC ammeter. C is calculated from IG = C·(dVG/dt) EE130/230A Fall 2013 Lecture 17, Slide 11 Deep Depletion (p-type Si) • If VG is scanned quickly, Qinv cannot respond to the change in VG. Then the increase in substrate charge density Qs must come from an increase in depletion charge density Qdep depletion depth W increases as VG increases C decreases as VG increases C Cox Cmin VFB EE130/230A Fall 2013 VT Lecture 17, Slide 12 VG MOS C-V Characteristic for n-type Si MOS transistor at any f, MOS capacitor at low f, or quasi-static C-V C Cmax=Cox CFB MOS capacitor at high f inversion EE130/230A Fall 2013 Cmin VT depletion Lecture 17, Slide 13 VFB accumulation VG Examples: C-V Characteristics C QS Cox HF-Capacitor VT VFB VG Does the QS or the HF-capacitor C-V characteristic apply? (1) MOS capacitor, f=10kHz (2) MOS transistor, f=1MHz (3) MOS capacitor, slow VG ramp (4) MOS transistor, slow VG ramp EE130/230A Fall 2013 Lecture 17, Slide 14 Example: Effect of Doping • How would the normalized C-V characteristic below change if the substrate doping NA were increased? – VFB – VT – Cmin C/Cox 1 VFB EE130/230A Fall 2013 VT Lecture 17, Slide 15 Example: Effect of Oxide Thickness • How would the normalized C-V characteristic below change if the oxide thickness xo were decreased? – VFB – VT – Cmin C/Cox 1 VFB EE130/230A Fall 2013 VT Lecture 17, Slide 16 Derivation of Time to Build Inversion-Layer Charge (for an NMOS device, i.e. p-type Si) 2 n D n D p i pn The net rate of carrier generation is: t t t p (n n1 ) t n ( p p1 ) (ref. Lecture 5, Slide 24) ( ET Ei ) / kT ( Ei ET ) / kT n n e n and p n e ni where 1 i i 1 i since trap states that contribute most significantly to G-R have an associated energy level near the middle of the band gap. Within the depletion region, n and p are negligible, so where tn tp to n Dn Dp i t t 2t o Therefore, the rate at which the inversion-layer charge density Qinv (units: C/cm2) increases due to thermal generation within the depletion region (of width W) is dQinv ni q W dt 2t o EE130/230A Fall 2013 Lecture 17, Slide 17 For a fixed value of gate voltage, the total charge in the semiconductor is fixed: QS Qinv Qdep constant Therefore dQdep dQinv d qN AW dt dt dt qni dW W qN A 2t o dt ni dW W 0 dt 2 N At o The solution to this differential equation is where EE130/230A Fall 2013 W e ni / 2 N At o t e t /t 2 N At o t ni Lecture 17, Slide 18