Week 9b
OUTLINE
The metal-oxide field-effect transistor (MOSFET)
Structure and operation of the MOSFET
MOSFET as a 3-terminal device
pn diodes isolate transistors in an IC
MOSFET current-voltage characteristics
The MOSFET as a controlled resistance
MOSFET as an amplifier or electronically
controlled switch
EE42/100, Spring 2006
Week 9b, Prof. White
1
Modern Field Effect Transistor
(FET)
• An electric field is applied normal to the surface of the
semiconductor (by applying a voltage to an overlying
“gate” electrode), to modulate the conductance of the
semiconductor
 Modulate drift current flowing between 2 contacts
(“source” and “drain”) by varying the voltage on the
“gate” electrode
N-channel metal-oxidesemiconductor field-effect
transistor (NMOSFET)
EE42/100, Spring 2006
Week 9b, Prof. White
2
MOSFET
• NMOS: N-channel Metal
Oxide Semiconductor
W
• L = channel length
• W = channel width
GATE
L
“Metal” (heavily
doped poly-Si)
DRAIN
SOURCE
• A GATE electrode is placed above (electrically insulated
from) the silicon surface, and is used to control the
resistance between the SOURCE and DRAIN regions
EE42/100, Spring 2006
Week 9b, Prof. White
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N-channel MOSFET
Gate
Source
IS
IG
Drain
gate
oxide insulator
n
ID
n
p
• Without a gate-to-source voltage applied, no current can
flow between the source and drain regions.
• Above a certain gate-to-source voltage (threshold
voltage VT), a conducting layer of mobile electrons is
formed at the Si surface beneath the oxide. These
electrons can carry current between the source and drain.
EE42/100, Spring 2006
Week 9b, Prof. White
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N-channel vs. P-channel
MOSFETs
NMOS
PMOS
n+ poly-Si
p+ poly-Si
n+
n+
p+
p-type Si
p+
n-type Si
• For current to flow, VGS > VT
• For current to flow, VGS < VT
• Enhancement mode: VT > 0
• Enhancement mode: VT < 0
• Depletion mode: VT < 0
• Depletion mode: VT > 0
– Transistor is ON when VG=0V
– Transistor is ON when VG=0V
(“n+” denotes very heavily doped n-type material; “p+” denotes very heavily doped p-type material)
EE42/100, Spring 2006
Week 9b, Prof. White
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Why are pn Junctions Important for ICs?
• The basic building block in digital ICs is the
MOS (metal-oxide-semiconductor) transistor,
which contains reverse-biased diodes.
– pn junctions are important for electrical isolation of
transistors located next to each other at the
surface of a silicon wafer.
– The junction capacitance of these diodes can limit
the performance (operating speed) of digital
circuits
EE42/100, Spring 2006
Week 9b, Prof. White
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Device Isolation using pn Junctions
regions of n-type Si
a
b
n
n
n
n
n
p-type Si
No current flows if voltages are applied between n-type
regions, because two pn junctions are “back-to-back”
n-region
a
b
n-region
p-region
=> n-type regions isolated in p-type substrate and vice versa
EE42/100, Spring 2006
Week 9b, Prof. White
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Transistor A
Transistor B
n
n
n
n
p-type Si
We can build large circuits consisting of many transistors
without worrying about current flow between devices. The
p-n junctions isolate the transistors because there is
always at least one reverse-biased p-n junction in every
potential current path.
EE42/100, Spring 2006
Week 9b, Prof. White
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MOSFET Circuit Symbols
G
NMOS
G
n+ poly-Si
n+
n+
S
S
p-type Si
PMOS
Body
G
G
p+ poly-Si
p+
p+
S
S
n-type Si
EE42/100, Spring 2006
Body
Week 9b, Prof. White
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Water Model for P-channel MOSFET
Source
Gate
Spring
Source
Gate
Drain
Drain
Flexible
membrane
Figure 0.1 Schematic symbol and water model for a
p-channel MOSFET
EE42/100, Spring 2006
Week 9b, Prof. White
10
MOSFET Terminals
• The voltage applied to the GATE terminal determines whether
current can flow between the SOURCE & DRAIN terminals.
– For an n-channel MOSFET, the SOURCE is biased at a lower
potential (often 0 V) than the DRAIN
(Electrons flow from SOURCE to DRAIN when VG > VT)
– For a p-channel MOSFET, the SOURCE is biased at a higher
potential (often the supply voltage VDD) than the DRAIN
(Holes flow from SOURCE to DRAIN when VG < VT )
• The BODY terminal is usually connected to a fixed potential.
– For an n-channel MOSFET, the BODY is connected to 0 V
– For a p-channel MOSFET, the BODY is connected to VDD
EE42/100, Spring 2006
Week 9b, Prof. White
11
NMOSFET IG vs. VGS Characteristic
Consider the current IG (flowing into G) versus VGS :
IG
G
S
oxide
semiconductor
VGS +

IG
D
VDS
+

The gate is insulated from the
semiconductor, so there is no
significant steady gate current.
always zero!
VGS
EE42/100, Spring 2006
Week 9b, Prof. White
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NMOSFET ID vs. VDS Characteristics
Next consider ID (flowing into D) versus VDS, as VGS is varied:
S
VGS +

D
oxide
semiconductor
ID
VGS > VT
zero if VGS < VT
VDS
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ID
G
VDS
+

Above threshold (VGS > VT):
“inversion layer” of electrons
appears, so conduction
between S and D is possible
Below “threshold” (VGS < VT):
no charge  no conduction
Week 9b, Prof. White
13
The MOSFET as a Controlled Resistor
• The MOSFET behaves as a resistor when VDS is low:
– Drain current ID increases linearly with VDS
– Resistance RDS between SOURCE & DRAIN depends on VGS
• RDS is lowered as VGS increases above VT
oxide thickness  tox
NMOSFET Example:
ID
VGS = 2 V
VGS = 1 V > VT
VDS
IDS = 0 if VGS < VT
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Inversion charge density Qi(x) = -Cox[VGS-VT-V(x)]
where Cox  eox / tox
Week 9b, Prof. White
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MOSFET as a Controlled Resistor (cont’d)
VDS
ID 
RDS
RDS
L /W
L /W
 Rs ( L / W ) 

 nQi  C (V  V  VDS )
n ox
GS
T
2
VDS
W
I D   nCox (VGS  VT 
)VDS
L
2
average value
of V(x)
We can make RDS low by
• applying a large “gate drive” (VGS  VT)
• making W large and/or L small
EE42/100, Spring 2006
Week 9b, Prof. White
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ID vs. VDS Characteristics
The MOSFET ID-VDS curve consists of two regions:
1) Resistive or “Triode” Region: 0 < VDS < VGS  VT
W
ID
L
where k n
 k n
VDS 

VGS  VT  2 VDS


  n Cox
process transconductance parameter
2) Saturation Region:
VDS > VGS  VT
k n W
VGS  VT 2
I DSAT 
2 L
where k n   nCox
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“CUTOFF” region: VG < VT
Week 9b, Prof. White
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MOSFET regions of operation
Cutoff: VGS </= VT
ID = 0
correction
Resistive: ID ~ (VGS – VT)VDS
Saturation: ID ~ (VGS – VT)2
EE42/100, Spring 2006
Week 9b, Prof. White
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MOSFET Uses
A MOSFET can be used as
A linear amplifier: Input voltage applied between
gate and source; output voltage
appears between source and drain
or
An electronic switch: Switches between no
current conduction between source and drain,
and heavy conduction between source and
drain as voltage applied between gate and
source changes from low to high for
NMOSFET
EE42/100, Spring 2006
Week 9b, Prof. White
18
Common-Source (CS) Amplifier
• The input voltage
vs causes vGS to
vary with time,
which in turn
causes iD to vary.
• The changing voltage
drop across RD causes
an amplified (and
inverted) version of the
input signal to appear
at the drain terminal.
VDD
RD
iD

vs
VBIAS +
–
EE42/100, Spring 2006
D+
+
S
+
vOUT = vDS
vIN = vGS


Week 9b, Prof. White
19
Load-Line Analysis of CS Amplifier
• The operating point of the circuit can be determined
by finding the intersection of the appropriate
MOSFET iD vs. vDS characteristic and the load line:
iD (mA)
load-line equation:
VDD  RDiD  vDS
vGS (V)
EE42/100, Spring 2006
v
(V)
DS
Week 9b, Prof. White
20
Voltage Transfer Function
vOUT
vIN
Goal:
Operate the amplifier
in the high-gain region,
so that small changes
in vIN result in large
changes in vOUT
(1): transistor biased in cutoff region
(2): vIN > VT ; transistor biased in saturation region
(3): transistor biased in saturation region
(4): transistor biased in “resistive” or “triode” region
EE42/100, Spring 2006
Week 9b, Prof. White
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Notation
• Subscript convention:
 VDS  VD – VS , VGS  VG – VS , etc.
• Double-subscripts denote DC sources:
 VDD , VCC , ISS , etc.
• To distinguish between DC and incremental components of an
electrical quantity, the following convention is used:
– DC quantity: upper-case letter with upper-case subscript
 ID , VDS , etc.
– Incremental quantity: lower-case letter with lower-case subscript
 id , vds , etc.
– Total (DC + incremental) quantity:
lower-case letter with upper-case subscript
 iD , vDS , etc.
EE42/100, Spring 2006
Week 9b, Prof. White
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Quiescent Operating Point
• The operating point of the amplifier for zero input
signal (vs = 0) is often referred to as the quiescent
operating point. (Another word: bias.)
– The bias point should be chosen so that the output
voltage is approximately centered between VDD and 0 V.
– vs varies the input voltage around the input bias point.
Note: The relationship between vOUT and vIN is not linear;
this can result in a distorted output voltage signal. If the
input signal amplitude is very small, however, we can
have amplification with negligible distortion.
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Week 9b, Prof. White
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Week 9b, Prof. White
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