– CMOS transistors
– Digital logic
12/10/2004 EE 42 fall 2004 lecture 42 1

12/10/2004 EE 42 fall 2004 lecture 42 2

12/10/2004 EE 42 fall 2004 lecture 42 3

V
GS
< V t
+ gate source n oxide insulator
P n drain
Below threshold, there are no electrons under the gate oxide, and the holes in the substrate are blocked from carrying current by reverse biased diode junctions
12/10/2004 EE 42 fall 2004 lecture 42 4

NMOS in the linear (Triode) region
V
GS
> V t
+ source n gate oxide insulator
P n drain
If the gate voltage is above threshold, but the source to drain voltage is small, the charge under the gate is uniform, and carries current much like a resistor
The electrons move under the influence of the
Electric field at a velocity: ν=μE where E=volts/distance
And they must travel a distance L to cross the gate
Since the total charge is Q=CV gs
I d
= μC gate
V ds
(V gs
-V th
)/L 2 =
μ(ε ox
, we will have a current
/d ox
)V ds
(V gs
-V th
)W/L
12/10/2004 EE 42 fall 2004 lecture 42 5

NMOS with increasing V ds
V
GS
> V t
+ gate source n oxide insulator
P n drain
As the voltage from the source to the drain is increased, the current increases, but not by as much because the charge is attracted out from under the oxide, beginning to pinch off the channel
12/10/2004 EE 42 fall 2004 lecture 42 6

• As the Source-Drain voltage is increased, there will be a significant change in the charge at different distances along the gate
• When the voltage across the device at the drain end goes below threshold, the current is pinched off.
• If there is no current out the drain end, however, the current due to the carriers which are available from the source cause the voltage to be closer to that of the source.
• These two effects cause a small region to form near the drain which limits the current. This is called saturation
12/10/2004 EE 42 fall 2004 lecture 42 7

A little more MOS “Theory”
We have two regions: the resistive region at smaller V
DS
saturation region at higher V
DS
.
and the
In the resistive region we start out like a simple resistor between source and drain (whose value depends on gate voltage) and gradually the curve “bends over” as we approach saturation
In the saturation we have a small gradual increase of I with V
DS
I
D
V
GS
V
GS
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S
G
D i
D
-
+ V
DS
EE 42 fall 2004 lecture 42
V
DS
8

IN
Inverter
V
DD
Basic CMOS Inverter
V
DD CMOS
Inverter
IN
OUT p-ch
OUT n-ch
Example layout of
CMOS Inverter
12/10/2004 EE 42 fall 2004 lecture 42 9

IN
Al “wires”
V
DD
PMOS Gate
N-WELL
NMOS Gate
OUT
GROUND
12/10/2004 EE 42 fall 2004 lecture 42 10

source
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V
DS
- +
V
-
GS gate
+
I
G metal oxide insulator metal n-type metal n-type
I
D p-type
S metal
G
I
G
V
DS
I
D
+
D
EE 42 fall 2004 lecture 42 drain
11

G
I
G
I
D
S
+
D
V
DS
• Since the transistor is a 3-terminal device, there is no single I-V characteristic.
• Note that because of the insulator, I
G
= 0 A.
• We typically define the MOS I-V characteristic as
I
D vs. V
DS for a fixed V
GS
.
• The I-V characteristic changes as V
GS
12/10/2004 EE 42 fall 2004 lecture 42 changes.
12

I
D
triode mode saturation mode
V
GS
= 3 V
V
DS
= V
GS
- V
TH(n)
V
GS
= 2 V
V
GS
= 1 V cutoff mode (when V
GS
EE 42 fall 2004 lecture 42
< V
TH(N)
)
V
DS
13 12/10/2004

• At low Source to drain voltages, a MOS transistor looks like a resistor which is “turned on” by the gate voltage
• If a more voltage is applied to the drain to pull more current through, the amount of current which flows stops increasing → an effect called pinch-off .
• Think of water being sucked through a flexible wall tube.
Dropping the pressure at the end in order to try to get more water to come through just collapses the tube.
• The current flow then just depends on the flow at the input: VGS
• This is often the desired operating range for a MOS transistor (in a linear circuit), as it gives a current source at the drain as a function of the voltage from the gate to the source.
12/10/2004 EE 42 fall 2004 lecture 42 14

V
DD
CMOS DIGITAL LOGIC
A
NAND gate
A B A B
C=
A B
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0 B
C
Making a NAND gate: (NMOS pulls “down”, PMOS “up”)
NMOS portion: both inputs need to be high for output to be low  series
PMOS portion: either input can be low for output to be high  parallel
EE 42 fall 2004 lecture 42 15

Logic Gates
These are circuits that accomplish a given logic function such as “OR”. We will shortly see how such circuits are constructed. Each of the basic logic gates has a unique symbol, and there are several additional logic gates that are regarded as important enough to have their own symbol. The set is: AND, OR, NOT, NAND,
NOR, and EXCLUSIVE OR.
A A
AND C=A·B NAND C = A

B
B B
A
B
OR C=A+B
A
B
NOR
C = A

B
A
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NOT
A
A
B
EXCLUSIVE OR
EE 42 fall 2004 lecture 42
C

A

B
16

It may be simpler to just think of PMOS and NMOS transistors instead of a general 3 terminal pull-up or pull-down devices or networks.
V
DD
V
DD
V
IN-U
I
OUT
Pull-Up
Network
Output
Pull-Down
Network
V
IN-D
V
OUT
V
IN-U
I
OUT
V
IN-D p-type MOS
Transistor
(PMOS)
Output n-type MOS
Transistor
(NMOS)
V
OUT
12/10/2004 EE 42 fall 2004 lecture 42 17

• If inputs A and B are connected to parallel NMOS, A and B must be connected to series PMOS.
• The reverse is also true.
• Determining the logic function from CMOS circuit is not hard:
– Look at the NMOS half. It will tell you when the output is logic zero.
– Parallel transistors: “like or”
– Series transistors: “like and”
12/10/2004 EE 42 fall 2004 lecture 42 18

Some Useful Theorems
1) A

B

B

A
Communicative
2)
A

B

B

A
Defined from truth tables
3)
A

B

C

C

B

A
Associative
4) A

B

C

C

B

A
5) A

A

0
A

A

1
Each of these can be
6)
7)

B

A

C

A

(B

C)
Distributive
8)
A

B

A

B proved by writing out truth tables
de Morgan’s Laws
9)
A

B

A

B
12/10/2004 EE 42 fall 2004 lecture 42 19

Evaluation of Logical Expressions with “Truth Tables”
The Truth Table completely describes a logic expression
In fact, we will use the Truth Table as the fundamental meaning of a logic expression.
Two logic expressions are equal if their truth tables are the same
A truth table can be turned into a sum-of-products by writing each row which results in a “1” output as an “and” (the product), and then ORing them together (the sum)
12/10/2004 EE 42 fall 2004 lecture 42 20

Going from a Boolean expression to gates
NAND GATE SYNTHESIS. Using De Morgan’s theorem we can turn any
Boolean expression into NAND gates.
Simply expand the Boolean expression into a SUM-OF-PRODUCTS expression:
Y = ABC+DEF
Then rewrite it by “inverting” with De Morgan:
Y


(ABC)

(DEF)

Clearly this expression is realized with three NAND gates: one three-input NAND for (ABC) , one for
B
A
C
(DEF) , and one two-input gate to combine them:
D
E
F
Y The NAND realization, while based on
DeMorgan’s theorem, is in fact much simpler: just look at the sum of products expression and use one NAND for each term and one to combine the terms.
12/10/2004 EE 42 fall 2004 lecture 42 21

Synthesis
Designing the combinatorial logic circuit, con’t
Method 3: NAND GATE SYNTHESIS (CONTINUED).
X
Two Examples of SUM-OF-PRODUCTS expressions:

A B

A B (X-OR function) Y

ABC

A B C
A B C
A
X
B
(No connection)
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Y
We could make the drawings simpler by just using a circle for the NOT function rather than showing a oneinput NAND gate
EE 42 fall 2004 lecture 42 22

CMOS NAND GATE
NMOS switches in series from output to ground; PMOS switches in parallel from output to the supply (Here we left out the A-A and B-B connection for clarity) v
A v
B
V
DD
NAND: If either output is low then one of the bottom (pull down) series switches is open and one of the upper (pull up) switches are closed.
v
OUT
Thus the output is pulled high.
v
B v
A
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Behaves like 2 R n
’s in series when both A and B are high
EE 42 fall 2004 lecture 42 23

v
A v
B v
A v
B
NAND Gate Pull-Up Model*
V
DD
Output is loaded by the gate capacitance of the next stage: C= C
Gn
+C
Gp
R p
R p v
OUT

C

C
Gn

C
Gp
C
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One or both switches closed
(worse case: one switch) t
= RC = R p
C

R p
( C
Gn

C
Gp
)
EE 42 fall 2004 lecture 42 24

V
DD
A
V
DD
A
F
F
B
B
C
2-input NAND
3-input NAND
Each input loads with C
GN
+C
GP
Output drives with 2R
DN or R
DP
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Each input loads with C
GN
+C
GP
Output drives with 3R
DN or R
DP
EE 42 fall 2004 lecture 42 25

NOR function (two inputs)
CMOS NOR GATE
A B A +B
0 0 0
0 1 1
1
C=A +B
0
1 0 1 0
1 1 1 0
Output is high only if both inputs are low 
PMOS switches (between the supply and the output) in series
Output is low if either input is high 
NMOS switches (between ground and the output) in parallel
12/10/2004 EE 42 fall 2004 lecture 42
A
B
V
DD
C
A B
26

CMOS NOR GATE
“Complementary” configuration to the NAND gate
V
DD
NAND
V
DD v
A
NOR v
A v
B
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OUT v
B
EE 42 fall 2004 lecture 42 v
OUT
27

Definition of Fanout
Fanout = number of gates that are connected to the driver
1
2
n
Fanout leads to increased capacitive load (and higher delay)
12/10/2004 EE 42 fall 2004 lecture 42 28

• If we put two latches into every feedback path, and make sure both latches are never open at the same time, we can insure predicable results.
A
B
C
Outputs
 
EE 42 fall 2004 lecture 42 12/10/2004 29

• If we use an edge trigger, then a single phase clock can be used. An edge triggered flip flop will only change at a rising or falling edge of the clock, so that the new state will not feedback to its own value
A
B
C
Outputs
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
EE 42 fall 2004 lecture 42

30

• The timing rules for sequential logic can be summarized:
• Only one transition of the latches are allowed per clock cycle, the change from one clock is not allowed to circulate back through the logic to effect itself.
• The clock speed will be limited by the slowest path
• The fastest path must not be allowed to change the state before changes have been latched out
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