CS 152 Computer Architecture and
Engineering
Lecture 13 - Out-of-Order Issue,
Register Renaming,
& Branch Prediction
Krste Asanovic
Electrical Engineering and Computer Sciences
University of California at Berkeley
http://www.eecs.berkeley.edu/~krste
http://inst.eecs.berkeley.edu/~cs152
Last time in Lecture 12
• Pipelining is complicated by multiple and/or variable
latency functional units
• Out-of-order and/or pipelined execution requires
tracking of dependencies
– RAW
– WAR
– WAW
• Dynamic issue logic can support out-of-order
execution to improve performance
– Last time, looked at simple scoreboard to track out-of-order
completion
• Hardware register renaming can further improve
performance by removing hazards.
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Out-of-Order Issue
ALU
IF
ID
Issue
Mem
WB
Fadd
Fmul
• Issue stage buffer holds multiple instructions waiting to issue.
• Decode adds next instruction to buffer if there is space and the instruction does
not cause a WAR or WAW hazard.
–
Note: WAR possible again because issue is out-of-order (WAR not possible with in-order issue and
latching of input operands at functional unit)
• Any instruction in buffer whose RAW hazards are satisfied can be issued (for now
at most one dispatch per cycle). On a write back (WB), new instructions may get
enabled.
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Overcoming the Lack of Register
Names
Floating Point pipelines often cannot be kept filled
with small number of registers.
IBM 360 had only 4 floating-point registers
Can a microarchitecture use more registers than
specified by the ISA without loss of ISA
compatibility ?
Robert Tomasulo of IBM suggested an ingenious
solution in 1967 using on-the-fly register renaming
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Instruction-level Parallelism via Renaming
1
LD
F2,
34(R2)
2
LD
F4,
45(R3)
latency
1
2
4
3
long
3
MULTD
F6,
F4,
F2
3
4
SUBD
F8,
F2,
F2
1
5
DIVD
F4’,
F2,
F8
4
6
ADDD
F10,
F6,
F4’
1
In-order:
Out-of-order:
1
X
5
6
1 (2,1) . . . . . . 2 3 4 4 3 5 . . . 5 6 6
1 (2,1) 4 4 5 . . . 2 (3,5) 3 6 6
Any antidependence can be eliminated by renaming.
(renaming  additional storage)
Can it be done in hardware? yes!
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Register Renaming
ALU
IF
ID
Mem
Issue
WB
Fadd
Fmul
• Decode does register renaming and adds instructions to
the issue stage reorder buffer (ROB)
 renaming makes WAR or WAW hazards impossible
• Any instruction in ROB whose RAW hazards have been
satisfied can be dispatched.
 Out-of-order or dataflow execution
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Dataflow execution
Ins#
use exec
op
p1
src1
src2
t1
t2
.
.
.
ptr2
next to
deallocate
ptr1
next
available
p2
Reorder buffer
tn
Instruction slot is candidate for execution when:
• It holds a valid instruction (“use” bit is set)
• It has not already started execution (“exec” bit is clear)
• Both operands are available (p1 and p2 are set)
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Renaming & Out-of-order Issue
An example
Renaming table
v1
F1
F2
F3
F4
F5
F6
F7
F8
p
data
v1
t1
t5
t2
Reorder buffer
Ins# use exec
op p1
src1
p2 src2
0
1
1
0
LD
LD
3
0
1
10
1
0
MUL
10
v2
t2
11
v1
v1
4
5
10
1
1
0
0
SUB
DIV
1
1
v1
v1
1
0
1
v1
t4
v4
1
22
t3
t1
t2
t3
t4
t5
.
.
v4
t4
data / ti
1
2
3
4
5
6
LD
LD
MULTD
SUBD
DIVD
ADDD
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F2,
F4,
F6,
F8,
F4,
F10,
34(R2)
45(R3)
F4,
F2,
F2,
F6,
F2
F2
F8
F4
• When are tags in sources
replaced by data?
Whenever an FU produces data
• When can a name be reused?
Whenever an instruction completes
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Data-Driven Execution
Renaming
table &
reg file
Ins# use exec
op
p1
src1
p2
src2
Reorder
buffer
Replacing the
tag by its value
is an expensive
operation
Load
Unit
FU
FU
t1
t2
.
.
tn
Store
Unit
< t, result >
• Instruction template (i.e., tag t) is allocated by the
Decode stage, which also associates tag with register in regfile
• When an instruction completes, its tag is deallocated
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Simplifying Allocation/Deallocation
Ins#
use exec
op
p1
src1
p2
t1
t2
.
.
.
ptr2
next to
deallocate
ptr1
next
available
src2
Reorder buffer
tn
Instruction buffer is managed circularly
•“exec” bit is set when instruction begins execution
•When an instruction completes its “use” bit is marked free
• ptr2 is incremented only if the “use” bit is marked free
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IBM 360/91 Floating-Point Unit
R. M. Tomasulo, 1967
1
2
3
4
5
6
distribute
instruction
templates
by
functional
units
p
p
p
p
p
p
tag/data
tag/data
tag/data
tag/data
tag/data
tag/data
load
buffers
(from
memory)
instructions
...
1
2
3
4
p
p
p
p
tag/data
tag/data
tag/data
tag/data
Floating
Point
Reg
1 p tag/data p tag/data
2 p tag/data p tag/data 1 p tag/data p tag/data
3 p tag/data p tag/data 2 p tag/data p tag/data
Adder
Mult
< tag, result >
store buffers
(to memory)
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p tag/data
p tag/data
p tag/data
Common bus ensures that data is made available
immediately to all the instructions waiting for it.
Match tag, if equal, copy value & set presence “p”.
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Effectiveness?
Renaming and Out-of-order execution was first
implemented in 1969 in IBM 360/91 but did not
show up in the subsequent models until midNineties.
Why ?
Reasons
1. Effective on a very small class of programs
2. Memory latency a much bigger problem
3. Exceptions not precise!
One more problem needed to be solved
Control transfers
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Precise Interrupts
It must appear as if an interrupt is taken between
two instructions (say Ii and Ii+1)
• the effect of all instructions up to and including Ii is
totally complete
• no effect of any instruction after Ii has taken place
The interrupt handler either aborts the program or
restarts it at Ii+1 .
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Effect on Interrupts
Out-of-order Completion
I1
I2
I3
I4
I5
I6
out-of-order comp
DIVD
LD
MULTD
DIVD
SUBD
ADDD
1
2
f6,
f2,
f0,
f8,
f10,
f6,
2
3
f6,
45(r3)
f2,
f6,
f0,
f8,
1 4 3 5
restore f2
f4
f4
f2
f6
f2
5
4 6 6
restore f10
Consider interrupts
Precise interrupts are difficult to implement at high speed
- want to start execution of later instructions before
exception checks finished on earlier instructions
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Exception Handling
Commit
Point
(In-Order Five-Stage Pipeline)
Inst.
Mem
PC
Select
Handler
PC
PC Address
Exceptions
Kill F
Stage
•
•
•
•
D
Decode
E
Illegal
Opcode
+
M
Overflow
Data
Mem
Data Addr
Except
W
Kill
Writeback
Exc
D
Exc
E
Exc
M
Cause
PC
D
PC
E
PC
M
EPC
Kill D
Stage
Kill E
Stage
Asynchronous
Interrupts
Hold exception flags in pipeline until commit point (M stage)
Exceptions in earlier pipe stages override later exceptions
Inject external interrupts at commit point (override others)
If exception at commit: update Cause and EPC registers, kill
all stages, inject handler PC into fetch stage
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Phases of Instruction Execution
PC
I-cache
Fetch
Buffer
Issue
Buffer
Func.
Units
Result
Buffer
Arch.
State
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Fetch: Instruction bits retrieved
from cache.
Decode: Instructions placed in appropriate
issue (aka “dispatch”) stage buffer
Execute: Instructions and operands sent to
execution units .
When execution completes, all results and
exception flags are available.
Commit: Instruction irrevocably updates
architectural state (aka “graduation” or
“completion”).
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In-Order Commit for Precise Exceptions
In-order
Fetch
Out-of-order
Reorder Buffer
Decode
Kill
In-order
Commit
Kill
Kill
Execute
Inject handler PC
Exception?
• Instructions fetched and decoded into instruction
reorder buffer in-order
• Execution is out-of-order (  out-of-order completion)
• Commit (write-back to architectural state, i.e., regfile &
memory, is in-order
Temporary storage needed to hold results before commit
(shadow registers and store buffers)
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Extensions for Precise Exceptions
Inst# use exec
op
p1
src1 p2 src2
pd dest
data cause
ptr2
next to
commit
ptr1
next
available
Reorder buffer
• add <pd, dest, data, cause> fields in the instruction template
• commit instructions to reg file and memory in program
order  buffers can be maintained circularly
• on exception, clear reorder buffer by resetting ptr1=ptr2
(stores must wait for commit before updating memory)
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Rollback and Renaming
Register File
(now holds only
committed state)
Ins# use exec
op
p1
src1
p2
src2
pd dest
t1
t2
.
.
tn
data
Reorder
buffer
Load
Unit
FU
FU
FU
Store
Unit
Commit
< t, result >
Register file does not contain renaming tags any more.
How does the decode stage find the tag of a source register?
Search the “dest” field in the reorder buffer
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Renaming Table
Rename
Table
r1
r2
t
tag
valid bit
v
Ins# use exec
op
p1
Register
File
src1
p2
src2
pd dest
t1
t2
.
.
tn
data
Reorder
buffer
Load
Unit
FU
FU
FU
Store
Unit
Commit
< t, result >
Renaming table is a cache to speed up register name look up.
It needs to be cleared after each exception taken.
When else are valid bits cleared?
Control transfers
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CS152 Administrivia
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Control Flow Penalty
Next fetch
started
PC
I-cache
Modern processors may have
> 10 pipeline stages between
next PC calculation and branch
resolution !
Fetch
Buffer
Fetch
Decode
Issue
Buffer
How much work is lost if
pipeline doesn’t follow
correct instruction flow?
Func.
Units
Execute
~ Loop length x pipeline width
Branch
executed
Result
Buffer
Commit
Arch.
State
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MIPS Branches and Jumps
Each instruction fetch depends on one or two pieces
of information from the preceding instruction:
1) Is the preceding instruction a taken branch?
2) If so, what is the target address?
Instruction
Taken known?
Target known?
J
After Inst. Decode
After Inst. Decode
JR
After Inst. Decode
After Reg. Fetch
BEQZ/BNEZ
After Reg. Fetch*
After Inst. Decode
*Assuming
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zero detect on register read
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Branch Penalties in Modern Pipelines
UltraSPARC-III instruction fetch pipeline stages
(in-order issue, 4-way superscalar, 750MHz, 2000)
Branch
Target
Address
Known
Branch
Direction &
Jump
Register
Target
Known
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A
P
F
B
I
J
R
E
PC Generation/Mux
Instruction Fetch Stage 1
Instruction Fetch Stage 2
Branch Address Calc/Begin Decode
Complete Decode
Steer Instructions to Functional units
Register File Read
Integer Execute
Remainder of execute pipeline
(+ another 6 stages)
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Reducing Control Flow Penalty
Software solutions
• Eliminate branches - loop unrolling
Increases the run length
• Reduce resolution time - instruction scheduling
Compute the branch condition as early
as possible (of limited value)
Hardware solutions
• Find something else to do - delay slots
Replaces pipeline bubbles with useful work
(requires software cooperation)
• Speculate - branch prediction
Speculative execution of instructions beyond
the branch
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Branch Prediction
Motivation:
Branch penalties limit performance of deeply pipelined
processors
Modern branch predictors have high accuracy
(>95%) and can reduce branch penalties significantly
Required hardware support:
Prediction structures:
• Branch history tables, branch target buffers, etc.
Mispredict recovery mechanisms:
• Keep result computation separate from commit
• Kill instructions following branch in pipeline
• Restore state to state following branch
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Static Branch Prediction
Overall probability a branch is taken is ~60-70% but:
backward
90%
forward
50%
JZ
JZ
ISA can attach preferred direction semantics to branches,
e.g., Motorola MC88110
bne0 (preferred taken) beq0 (not taken)
ISA can allow arbitrary choice of statically predicted direction,
e.g., HP PA-RISC, Intel IA-64
typically reported as ~80% accurate
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Dynamic Branch Prediction
learning based on past behavior
Temporal correlation
The way a branch resolves may be a good
predictor of the way it will resolve at the next
execution
Spatial correlation
Several branches may resolve in a highly
correlated manner (a preferred path of
execution)
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Branch Prediction Bits
• Assume 2 BP bits per instruction
• Change the prediction after two consecutive mistakes!
taken
taken
take
right
¬ taken
¬take
wrong
taken
¬ taken
¬take
right
¬ taken
taken
take
wrong
¬ taken
BP state:
(predict take/¬take) x (last prediction right/wrong)
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Branch History Table
Fetch PC
00
k
I-Cache
Instruction
Opcode
BHT Index
2k-entry
BHT,
2 bits/entry
offset
+
Branch?
Target PC
Taken/¬Taken?
4K-entry BHT, 2 bits/entry, ~80-90% correct predictions
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Acknowledgements
• These slides contain material developed and
copyright by:
–
–
–
–
–
–
Arvind (MIT)
Krste Asanovic (MIT/UCB)
Joel Emer (Intel/MIT)
James Hoe (CMU)
John Kubiatowicz (UCB)
David Patterson (UCB)
• MIT material derived from course 6.823
• UCB material derived from course CS252
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