CS 152 Computer Architecture and Engineering Lecture 15 - Advanced Superscalars Krste Asanovic
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CS 152 Computer Architecture and Engineering Lecture 15 - Advanced Superscalars Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste http://inst.eecs.berkeley.edu/~cs152 Last time in Lecture 14 • Control hazards are serious impediment to superscalar performance • Dynamic branch predictors can be quite accurate (>95%) and avoid most control hazards • Branch History Tables (BHTs) just predict direction (later in pipeline) – Just need a few bits per entry (2 bits gives hysteresis) – Need to decode instruction bits to determine whether this is a branch and what the target address is • Branch Target Buffer (BTB) predicts whether a branch, and target address – Needs PC tag, predicted Next-PC, and direction – Just needs PC of instruction to predict target of branch (if any) • Return address stack: special form of BTB used to predict subroutine return addresses 4/1/2008 CS152-Spring’08 2 “Data in ROB” Design (HP PA8000, Pentium Pro, Core2Duo) Register File holds only committed state Ins# use exec op p1 src1 p2 src2 pd dest data Reorder buffer Load Unit FU FU FU Store Unit t1 t2 . . tn Commit < t, result > • On dispatch into ROB, ready sources can be in regfile or in ROB dest (copied into src1/src2 if ready before dispatch) • On completion, write to dest field and broadcast to src fields. • On issue, read from ROB src fields 4/1/2008 CS152-Spring’08 3 Unified Physical Register File (MIPS R10K, Alpha 21264, Pentium 4) r1 r2 ti tj Rename Table t1 t2 . tn Snapshots for mispredict recovery Load Unit FU FU FU (ROB not shown) Reg File FU Store Unit < t, result > • One regfile for both committed and speculative values (no data in ROB) • During decode, instruction result allocated new physical register, source regs translated to physical regs through rename table • Instruction reads data from regfile at start of execute (not in decode) • Write-back updates reg. busy bits on instructions in ROB (assoc. search) • Snapshots of rename table taken at every branch to recover mispredicts • On exception, renaming undone in reverse order of issue (MIPS R10000) 4/1/2008 CS152-Spring’08 4 Pipeline Design with Physical Regfile Branch Resolution kill Branch Prediction PC Fetch kill kill Decode & Rename Update predictors kill Out-of-Order Reorder Buffer In-Order Commit In-Order Physical Reg. File Branch ALU MEM Unit Store Buffer D$ Execute 4/1/2008 CS152-Spring’08 5 Lifetime of Physical Registers • Physical regfile holds committed and speculative values • Physical registers decoupled from ROB entries (no data in ROB) ld r1, (r3) add r3, r1, #4 sub r6, r7, r9 add r3, r3, r6 ld r6, (r1) add r6, r6, r3 st r6, (r1) ld r6, (r11) Rename ld P1, (Px) add P2, P1, #4 sub P3, Py, Pz add P4, P2, P3 ld P5, (P1) add P6, P5, P4 st P6, (P1) ld P7, (Pw) When can we reuse a physical register? When next write of same architectural register commits 4/1/2008 CS152-Spring’08 6 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 4/1/2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 <R6> <R7> <R3> <R1> p p p p p2 Rd Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) Pn ROB use ex Physical Regs op p1 PR1 PR2 CS152-Spring’08 LPRd PRd (LPRd requires third read port on Rename Table for each instruction) 7 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P5 P6 4/1/2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 <R6> <R7> <R3> <R1> p p p p p2 Rd r1 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) Pn ROB use ex x Physical Regs op ld p1 p PR1 P7 PR2 CS152-Spring’08 LPRd P8 PRd P0 8 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P5 P6 4/1/2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 <R6> <R7> <R3> <R1> p p p p p2 Rd r1 r3 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) Pn ROB use ex x x Physical Regs op p1 ld p add PR1 P7 P0 PR2 CS152-Spring’08 LPRd P8 P7 PRd P0 P1 9 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P5 P3 P6 4/1/2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 <R6> <R7> <R3> <R1> p p p p p2 PR2 p P5 Rd r1 r3 r6 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) Pn ROB use ex x x x Physical Regs op p1 ld p add sub p PR1 P7 P0 P6 CS152-Spring’08 LPRd P8 P7 P5 PRd P0 P1 P3 10 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P2 P5 P3 P6 x x x x 4/1/2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 <R6> <R7> <R3> <R1> p p p p p2 PR2 Rd p P5 P3 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) Pn ROB use ex Physical Regs op p1 ld p add sub p add PR1 P7 P0 P6 P1 r1 r3 r6 r3 CS152-Spring’08 LPRd P8 P7 P5 P1 PRd P0 P1 P3 P2 11 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P2 P5 P3 P4 P6 4/1/2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 <R6> <R7> <R3> <R1> p p p p p2 PR2 p P5 P3 Rd r1 r3 r6 r3 r6 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) Pn ROB use ex x x x x x Physical Regs op p1 ld p add sub p add ld PR1 P7 P0 P6 P1 P0 CS152-Spring’08 LPRd P8 P7 P5 P1 P3 PRd P0 P1 P3 P2 P4 12 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P2 P5 P3 P4 P6 x x x x x x 4/1/2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 <R1> Free List p <R6> <R7> <R3> <R1> p p p p p2 PR2 Rd p P5 P3 P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P8 Pn ROB use ex Physical Regs op p1 ld p add p sub p add ld p PR1 P7 P0 P6 P1 P0 r1 r3 r6 r3 r6 CS152-Spring’08 LPRd P8 P7 P5 P1 P3 PRd P0 P1 P3 P2 P4 Execute & Commit 13 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P2 P5 P3 P4 P6 x x x x x x x 4/1/2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 Free List <R1> <R3> p p <R6> <R7> <R3> p p p p2 PR2 Rd p P5 P3 P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P8 P7 Pn ROB use ex Physical Regs op p1 ld p add p sub p add p ld p PR1 P7 P0 P6 P1 P0 r1 r3 r6 r3 r6 CS152-Spring’08 LPRd P8 P7 P5 P1 P3 PRd P0 P1 P3 P2 P4 Execute & Commit 14 CS152 Administrivia • New shifted schedule - see website for details • Lab 4, PS 4, due Tuesday April 8 – PRIZE (TBD) for winners in both unlimited and realistic categories of branch predictor contest • Quiz 4, Thursday April 10 • Quiz 5, Thursday April 24 • Quiz 6, Thursday May 8 (last day of class) 4/1/2008 CS152-Spring’08 15 Reorder Buffer Holds Active Instruction Window … (Older instructions) ld r1, (r3) add r3, r1, r2 sub r6, r7, r9 add r3, r3, r6 ld r6, (r1) add r6, r6, r3 st r6, (r1) ld r6, (r1) … (Newer instructions) Commit Execute Fetch Cycle t 4/1/2008 … ld r1, (r3) add r3, r1, sub r6, r7, add r3, r3, ld r6, (r1) add r6, r6, st r6, (r1) ld r6, (r1) … r2 r9 r6 r3 Cycle t + 1 CS152-Spring’08 16 Superscalar Register Renaming • During decode, instructions allocated new physical destination register • Source operands renamed to physical register with newest value • Execution unit only sees physical register numbers Update Mapping Op Dest Src1 Src2 Write Ports Inst 1 Op Dest Src1 Src2 Inst 2 Read Addresses Register Free List Rename Table Read Data Op PDest PSrc1 PSrc2 Op PDest PSrc1 PSrc2 Does this work? 4/1/2008 CS152-Spring’08 17 Superscalar Register Renaming Update Mapping Write Ports Inst 1 Op Dest Src1 Src2 Read Addresses =? Rename Table Read Data Must check for RAW hazards between instructions issuing in same cycle. Can be done in parallel with rename Op PDest PSrc1 PSrc2 lookup. Inst 2 Op Dest Src1 Src2 =? Register Free List Op PDest PSrc1 PSrc2 MIPS R10K renames 4 serially-RAW-dependent insts/cycle 4/1/2008 CS152-Spring’08 18 Memory Dependencies st r1, (r2) ld r3, (r4) When can we execute the load? 4/1/2008 CS152-Spring’08 19 In-Order Memory Queue • Execute all loads and stores in program order => Load and store cannot leave ROB for execution until all previous loads and stores have completed execution • Can still execute loads and stores speculatively, and out-of-order with respect to other instructions 4/1/2008 CS152-Spring’08 20 Conservative O-o-O Load Execution st r1, (r2) ld r3, (r4) • Split execution of store instruction into two phases: address calculation and data write • Can execute load before store, if addresses known and r4 != r2 • Each load address compared with addresses of all previous uncommitted stores (can use partial conservative check i.e., bottom 12 bits of address) • Don’t execute load if any previous store address not known (MIPS R10K, 16 entry address queue) 4/1/2008 CS152-Spring’08 21 Address Speculation st r1, (r2) ld r3, (r4) • Guess that r4 != r2 • Execute load before store address known • Need to hold all completed but uncommitted load/store addresses in program order • If subsequently find r4==r2, squash load and all following instructions => Large penalty for inaccurate address speculation 4/1/2008 CS152-Spring’08 22 Memory Dependence Prediction (Alpha 21264) st r1, (r2) ld r3, (r4) • Guess that r4 != r2 and execute load before store • If later find r4==r2, squash load and all following instructions, but mark load instruction as store-wait • Subsequent executions of the same load instruction will wait for all previous stores to complete • Periodically clear store-wait bits 4/1/2008 CS152-Spring’08 23 Speculative Loads / Stores Just like register updates, stores should not modify the memory until after the instruction is committed - A speculative store buffer is a structure introduced to hold speculative store data. 4/1/2008 CS152-Spring’08 24 Speculative Store Buffer Speculative Store Buffer V V V V V V S S S S S S Load Address Tag Tag Tag Tag Tag Tag Data Data Data Data Data Data L1 Data Cache Tags Store Commit Path Data Load Data • On store execute: – mark entry valid and speculative, and save data and tag of instruction. • On store commit: – clear speculative bit and eventually move data to cache • On store abort: – clear valid bit 4/1/2008 CS152-Spring’08 25 Speculative Store Buffer Speculative Store Buffer V V V V V V • • S S S S S S Tag Tag Tag Tag Tag Tag Load Address Data Data Data Data Data Data L1 Data Cache Tags Data Store Commit Path Load Data If data in both store buffer and cache, which should we use? Speculative store buffer If same address in store buffer twice, which should we use? Youngest store older than load 4/1/2008 CS152-Spring’08 26 Datapath: Branch Prediction and Speculative Execution Update predictors Branch Prediction kill kill Branch Resolution kill kill PC Fetch Decode & Rename Reorder Buffer Commit Reg. File 4/1/2008 Branch ALU MEM Unit Execute CS152-Spring’08 Store Buffer D$ 27 Acknowledgements • These slides contain material developed and copyright by: – – – – – – Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) • MIT material derived from course 6.823 • UCB material derived from course CS252 4/1/2008 CS152-Spring’08 28
