Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 15
Organisasi I/O: I
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Mahasiswa dapat membandingkan
beberapa metode pengaksesan peralatan
I/O dalam sistem komputer ( C4 ) ( No
TIK : 7 )
2
Chapter 4.
Input/Output
Organization: I
3
Processor
Memory
Bus
I/O device 1
I/O device n
Figure 4.1. A single-bus structure.
4
Address lines
Bus
Data lines
Control lines
Address
decoder
Control
circuits
Data and
status registers
I/O
interf ace
Input dev ice
Figure 4.2. I/O interface for an input device.
5
DATAIN
DATAOUT
STATUS
DIRQ
KIRQ SOUT
CONTROL
DEN
KEN
3
2
7
6
5
4
1
SIN
0
Figure 4.3. Registers in keyboard and display interf
aces.
6
WAITK
WAITD
Move
TestBit
Branch=0
Move
TestBit
Branch=0
Move
Move
Compare
Branch0
Move
Call
#LINE,R0
#0,STATUS
WAITK
DATAIN,R1
#1,STATUS
WAITD
R1,DATAOUT
R1,(R0)+
#$0D,R1
WAITK
#$0A,DATA OUT
PROCESS
Initialize memory pointer.
Test SIN.
Wait for characterto be entered.
Readcharacter.
Test SOUT.
Wait for display to becomeready.
Sendcharacterto display.
Store characterandadvance pointer.
Check if Carriage Return.
If not, get anothercharacter.
Otherwise,sendLine Feed.
Call a subroutineto process
the input line.
Figure 4.4 A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the disp
7
Program 1
Program 2
COMPUTE routine
PRINT routine
1
2
Interrupt
occurs
here
i
i +1
M
Figure 4.5. Transfer of control through the use of interrupts.
8
Vdd
Processor
R
I NTR
INTR
INTR1
INTR2
INTRn
Figure 4.6.An equivalent circuit for an open-drain bus used
to implement a common interrupt-request line.
9
Processor
INTR1
Dev ice 1
I NTRp
Dev ice 2
INTA1
Dev icep
INTA p
Priority arbitration
circuit
Figure 4.7. Implementation of interrupt priority using individual
interrupt-request and acknowledge lines.
Figure 4.7. Implementation of interrupt priority using individual interrupt-request and acknowledge lines.
10
Processor
I NT R
INTA
Dev icen
Dev ice 2
Dev ice 1
(a) Daisy chain
Processor
I NTR1
INTA1
Dev ice
Dev ice
Dev ice
Dev ice
INTR p
INTA p
Priority arbitration
circuit
(b) Arrangement of priority groups
Fi gure 4.8. Interrupt pri ori ty schem es.
11
Main Program
Move
Clear
BitSet
BitSet
..
.
#LINE,PNTR
EOL
#2,CONTROL
#9,PS
Initialize buffer pointer.
Clear end-of-line indicator.
Enable keyboard interrupts.
Set interrupt-enablebit in the PS.
Interrupt-serviceroutine
READ
RTRN
MoveMultiple R0-R1,– (SP)
Move
PNTR,R0
MoveByte
DATAIN,R1
MoveByte
R1,(R0)+
Move
R0,PNTR
CompareByte #$0D,R1
Branch 0
RTRN
Move
#1,EOL
BitClear
#2,CONTROL
MoveMultiple (SP)+,R0-R1
Return-from-interrupt
Save registersR0 and R1on stack.
Load addresspointer.
Get input characterand
store it in memory.
Updatepointer.
Check if CarriageReturn.
Indicateend of line.
Disable keyboard interrupts.
Restoreregisters R0 and R1.
Figure 4.9. Using interrupts to read a line of characters from a keyboard via the registers in Figure 4.3.
12
OSINIT
OSSER VICES
SCHEDULER
Set in terrupt vectors:
Time-slice
clo c k  SCHEDULER
Soft w are in terrupt
 OSSER VICES
Keyb oard in terrupts
 IOData
..
.
Examine stac k to determine
requested op eration.
Call appropriate
routine.
Sa ve program state.
Select a runnable pro cess.
Restore sav ed con text of new pro cess.
Push new values for PS and PC on stac k.
Return from in terrupt.
(a) OS initialization, services, and scheduler
IOINIT
Set pro cess status to Blo c ked.
Initialize
memory buffer address poin ter and coun ter.
Call device driv er to initialize device
and enable in terrupts
in the device in terface.
Return from subroutine.
IOD A T A
Poll devices to determine
source of in terrupt.
Call appropriate
driv er.
If END = 1, then set pro cess status to Runnable.
Return from in terrupt.
(b) I/O routines
KBDINIT
KBDD A T A
Enable in terrupts.
Return from subroutine.
Chec k device status.
If ready , then transfer c haracter.
If character
= CR, then { set END
else set END = 0.
Return from subroutine.
= 1; Disable
in terrupts }
(c) Keyboard driver
Figure 4.10. A few operating system routines.
13
7
6
I
F
5
4
3
2
1
0
M4
M3
M2
M1
M0
Figure 4.11. Low-order byte of the ARM processor status register.
14
User
FIQ
IRQ
R0
R0
R0
R0
R0
R0
R1
R1
R1
R1
R1
R1
R2
R2
R2
R2
R2
R3
R3
R3
R3
R3
R4
R4
R4
R4
R4
R5
R5
R5
R5
R5
R6
Superv isor
Abort
R6
R6
R6
R6
R7
R7
R7
R7
R7
R8
R8_f iq
R8
R8
R8
Undef ined
R2
R3
R4
R5
R6
R7
R8
R9
R9_f iq
R9
R9
R9
R9
R10
R10_f iq
R10
R10
R10
R10
R11
R11_f iq
R11
R11
R11
R11
R12
R12_f iq
R12
R12
R12
R12
R13
R13_f iq
R13_irq
R13-sv c
R13_abt
R13_und
R14
R14_f iq
R14_irq
R14_sv c
R14_abt
R14_und
R15
R15
R15
R15
R15
R15
Processor status regi ster
CPSR
CPSR
SPSR_f iq
CPSR
SPSR_irq
CPSR
SPSR_sv c
CPSR
SPSR_abt
CPSR
SPSR_und
Fi gure 4.12. Accessi bl e regi sters i n di fferent m odes of the ARM processor.
15
Main
program
MO V
STR
ADR
LDRB
ORR
STRB
MO V
MSR
..
.
IR Q
READ
In terrupt-service
STMFD
ADR
LDRB
LDR
STRB
STR
CMPB
LDMNEFD
SUBNES
LDRB
AND
STRB
MO V
STR
LDMFD
SUBS
R0,#0
R0,EOL
R1,D A T AIN
R0,[R1,#3]
R0,R0,#4
R0,[R1,#3]
R0,#&50
CPSR,R0
Clear EOL flag.
Load address of Register D A T AIN.
register.
Get contents of CONTROL
Set bit KEN in register CONTR OL
to enable k eyb oard in terrupts.
Enable IR Q in terrupts
in pro cessor
and switc h to user mo de.
routine
R13!, { R0  R2,R14
R1,DATAIN
R0,[R1]
R2,PNTR
R0,[R2],#1
R2,PNTR
R0,#&0D
R13!, { R0  R2,R14
PC,R14
irq,#4
R0,[R1,#3]
R0,R0,#&FB
R0,[R1,#3]
R0,#1
R0,EOL
R13!, { R0-R2,R14 }
PC,R14
irq,#4
irq }
irq }
Sa v e R0, R1, and R14 irq on the stack.
Load address of register
D A T AIN.
Get input character.
Load pointer
v alue.
Store character
and increment
pointer.
Up date poin ter v alue in the memory .
Chec k if Carriage Return.
If not, restore registers
and return.
Otherwise
get CONTROL
register.
Clear bit KEN
to disable k eyb oard in terrupts.
Set EOL flag.
Restore registers
and return.
Figure 4.13. An ARM interrupt-service routine to read an input line from a keyboard based on Figure 4.9.
16
15
13
T
S
10
8
Trace
Superv isor
Interrupt
Priority
4
3
2
1
0
X
N
Z
V
C
Condition
Codes
Figure 4.14. Processor status gister
re
in the 68000 processor
.
17
Main program
MOVE.L
CLR
ORI.B
MOVE
..
.
#LINE,PNTR
EOL
#4,CONTROL
#$100,SR
Initialize buffer pointer.
Clear end-of-lineindicator.
Set bit KEN.
Setprocessorpriority to 1.
Interrupt-serviceroutine
READ
RTRN
MOVEM.L
MOVEA.L
MOVE.B
MOVE.B
MOVE.L
CMPI.B
BNE
MOVE
ANDI.B
MOVEM.L
RTE
A0/D0,– (A7)
PNTR,A0
DATAIN,D0
D0,(A0)+
A0,PNTR
#$0D,D0
RTRN
#1,EOL
#$FB,CONTROL
(A7)+,A0/D0
Save registersA0, D0 on stack.
Load addresspointer.
Get input character.
Store it in memory buffer.
Updatepointer.
Check if CarriageReturn.
Indicateend of line.
Clearbit KEN.
Restore registersD0, A0.
Figure 4.15. A 68000 interrupt-service routine to read an input line from a keyboard based on Figure 4.9.
18
15
14
13
12
IOPL
11
10
9
8
IF
TF
Figure 4.16. Part of the Pentium's processor status register.
19
Main program
MOV
MOV
OR
STI
..
.
EOL,0
BL,4
CONTROL,BL
Set KEN to enable keyboard interrupts.
Set interruptflag in processor register.
In terrupt-serviceroutine
READ
RTRN
PUSH
PUSH
MOV
MOV
MOV
INC
CMP
JNE
MOV
XOR
MOV
POP
POP
IRET
EAX
EBX
EAX,PNTR
BL,DATAIN
[EAX],BL
DWORDPTR[EAX]
BL,0DH
RTRN
BL,4
CONTROL,BL
EOL,1
EBX
EAX
Save registerEAX on stack.
Save registerEBX on stack.
Load addresspointer.
Get input character.
Storecharacter.
Increment PNTR.
Check if characteris CR.
Clearbit KEN.
Set EOL flag.
Restoreregister EBX.
Restoreregister EAX.
Figure 4.17. An interrupt-servicing routine to read one line from a keyboard using interrupts on IA-32 processors.
20
31
30
1
0
Status and control
IRQ
Done
IE
R/ W
Starting address
Word count
Figure 4.18. Registers in a DMA interf
ace.
21
Sy stem us
b
Disk/DMA
controller
Disk
Disk
DMA
controller
Printer
K ey board
Network
Interface
Figure 4.19. Use of DMA controllers in a computer system.
Figure 4.19. Use of DMA controllers in a computer system.
22
B BSY
BR
Processor
BG1
DMA
controller
1
BG2
DMA
controller
2
Figure 4.20. A simple arrangement for
us barbitration using a daisy chain.
23
Time
BR
BG1
BG2
B BSY
Bus
master
Processor
DMA controller 2
Processor
Figure 4.21. Sequence of signals during transferusofmastership
b
for the de
vices in Figure 4.20.
Figure 4.21. Sequence of signals during transfer of bus mastership for the devices in Figure 4.20.
24
A RB 1
A RB 0
Start-Arbitration
O.C.
0
1
0
1
0
1
1
1
Interf ace circuit
f or dev ice A
Figure 4.22. A distributed arbitration scheme.
25
Matakuliah
Tahun
Versi
: T0324 / Arsitektur dan Organisasi Komputer
: 2005
:1
Pertemuan 16
Organisasi I/O: II
26
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Membandingkan beberapa metode
pengaksesan peralatan I/O dalam sistem
komputer ( C4 ) ( No TIK : 7 )
27
Chapter 4.
Input/Output
Organization: II
28
Time
Bus clock
Address and
command
Data
t0
t1
t2
Bus cy cle
Figure 4.23. Timing of an input transfer on a synchronous bus.
29
Figure 4.24. A detailed timing diagram for the input transfer of Figure 4.23.
30
Figure 4.25. An input transfer using multiple clock
ycles.
c
31
Master-ready
Slav e-ready
Data
t0
t1
t2
t3
t4
t5
Bus cy cle
Figure 4.26. Handshake control of data transfer during an input operation.
32
Slav e-ready
t0
t1
t2
t3
t4
t5
Bus cy cle
Figure 4.27. Handshake control of data transfer during an output operation.
33
Data
Address
Processor
R/W
DATAIN
Slave-ready
Data
SIN
Master-ready
Input
interface
Valid
Encoder
and
debouncing
circuit
Key board
switches
Figure 4.28. Keyboard to processor connection.
34
DATAIN
D7
Q7
D7
Q0
D0
Key board
data
D0
SIN
Slaveready
Status
f lag
Valid
1
Readstatus
Readdata
R/ W
Master
ready
A31
Address
decoder
A1
A0
Fi gure 4.29. Input i nterf
ace ci rcui t.
35
36
Data
Address
Processor
CPU
R/W
DATAOUT
Data
SOUT
Valid
Output
interface
Idle
Printer
Master-eady
Slave-ready
Figure 4.31. Printer to processor connection.
37
38
D7
Bus
PA7
D A T AIN
D1
D0
PA0
SIN
Input
status
CA
PB7
D A TA OUT
PB0
SOUT
Handshak e
control
Sla veReady
CB1
CB2
1
Master Ready
R/ W
A31
Address
decoder
My-address
A2
A1
A0
RS1
RS0
Figure 4.33. Combined input/output interface circuit.
39
DATAIN
D0
P0
DATAOUT
Data
Direction
Register
My -address
RS2
RS1
RS0
R/W
Ready
Accept
Register
select
Status
and
control
C1
C2
INTR
Fi gure 4.34. A general 8-bi t paral l el i nterf
ace.
40
D AT A OUT
D7
D7
Q7
Printer
data
D0
D0
D1
D0
Q1
Q0
SOUT
Read
status
Handshak e
control
Idle
Valid
Load
data
R/ W
Sla v eready
Go
A31
My-address
Address
decoder
T iming
Logic
A1
A0
Clock
My-address
Idle
Respond
Go=1
Figure 4.35. A parallel point interface for the bus of Figure 4.25,
with a state-diagram for the timing logic.
41
Time
1
2
3
Clock
Address
R/W
Data
Go
Slave-ready
Figure 4.36. Timing for the output interf
ace in Figure 4.35.
42
D0
DATAOUT
My -address
RS1
RS0
R/W
Chip and
register
select
Output shif t re
gister
Serial
output
Ready
Accept
I NTR
Status
and
control
Recei
v ing clock
Transmission clock
Fi gure 4.37. A seri al i nterf
ace.
43
Main
memory
Processor
Processor b us
Bridge
PCI b us
Additional
memory
SCSI
controller
Ethernet
interf ace
USB
controller
ISA
interf ace
SCSI b us
IDE
disk
V ideo
Disk
controller
Disk 1
Disk 2
CD-R OM
controller
CDR OM
K eyboard
Game
Figure 4.38. An example of a computer system using different interface standards.
44
PCI bridge
Main
memory
PCI bus
Disk
Printer
Ethernet
interface
Figure 4.39. Use of a PCI
us bin a computer system.
45
46
47
Targets examine ID
DB2
DB5
DB6
BSY
SEL
Free
Arbitration
Selection
Figure 4.42. Arbitration and selection on the SCSI bus.
Device 6 wins arbitration and selects device2.
48
Host computer
Root
hub
Hub
Hub
I/O
de vice
Hub
I/O
de vice
I/O
de vice
I/O
de vice
I/O
de vice
I/O
de vice
Figure 4.43. Universal Serial Bus tree structure.
49
Host computer
Root
Hub
HS
HS
Hub A
HS
Hub B
F/LS
HS
F/LS
De vice
C
- High speed
- Full/Lo w speed
De vice
D
Figure 4.44. Split bus operation
50
PID
0
PID
1
PID
2
PID
3
PID
0
PID
1
PID
2
PID
3
(a) Packet identifier field
Bits
8
7
PID
ADDR
4
ENDP
5
CRC16
(b) Token packet, IN or OUT
Bits
8
0 to 8192
16
PID
D A TA
CRC16
(c) Data packet
Figure 4.45. USB packet format.
51
ACK
Token
Data1
ACK
Fi gure 4.46. An output transfer
.
52
Bits
8
11
PID
Frame number
5
CRC5
(a) SOF Packet
1-ms frame
S
T3
D
T7
D
S - Start-of-frame pack
et
T n - T ok en pack et, address =
D - Data pack et
A - A CK pack et
S
T3
D
n
(b) Frame example
Figure 4.47. USB frames.
53
BG1
BG2
BR1
BGn
BR2
BRn
Figure P4.1. A decentralizedusb assignment scheme.
54
Table 4.1. Interrupt vector addresses for ARM processor
Address Exception
(hex)
Mode entered
0
Reset
Supervisor
4
Undefinedinstruction
Undefined
8
Softwareinterrupt
Supervisor
C
Abort during prefetch
Abort
10
Abort during data
Abort
14
Reserved
18
IRQ
IRQ
1C
FIQ
FIQ
55
Table 4.2. Address correction during return from exception.
Exception
Saved address* Desired
return address
Return instruction
Undefinedinstruction
PC+4
PC+4
MOVS PC,R14und
Software interrupt
PC+4
PC+4
MOVS PC,R14svc
Prefetch Abort
PC+4
PC
SUBS PC,R14abt,#4
Data Abort
PC+8
PC
SUBS PC,R14abt,#8
IRQ
PC+4
PC
SUBS PC,R14irq,#4
FIQ
PC+4
PC
SUBS PC,R14fiq,#4
* PC is the addressof the instruction that causedthe exception. For IRQ and FIQ,
it is the addressof the first instruction not executedbecauseof the interrupt.
56
Table 4.3. Data transfer signals on the PCI bus.
Name
Function
CLK
A 33-MHz or 66-MHz clock.
FRAME#
Sent by the initiator to indicate the duration of a
transaction.
AD
32 address/datalines, which may be optionally
increasedto 64.
C/BE#
4 command/byte-enablelines (8 for a 64-bit bus).
IRDY#, TRD Y#
Initiator-ready and Target-readysignals.
DEVSEL#
A responsefrom the device indicating that it has
recognizedits addressand is ready for a data
transfer transaction.
IDSEL#
Initialization Device Select.
57
Table 4.4 The SCSI bus signals.
Category
Data
Name
– DB(0)
– DB(7)
Phase
– DB(P)
– BSY
– SEL
Information
t yp e
– C/D
– MSG
Handshak e
– REQ
– A CK
Direction
transfer
Other
of
– I/O
– A TN
– RST
to
Function
Data lines: Carry one b yte of information
during the information
transfer phase and
iden tify device during arbitration,
selection and
reselection
phases
P arit y bit for the data bus
Busy: Asserted when the bus is not free
Selection:
Asserted during selection and
reselection
Con trol/Data:
Asserted
during transfer of
con trol information
(command,
status or
message)
Message:
indicates that the information
being
transferred
is a message
Request:
Asserted b y a target to request a data
transfer cycle
Ac kno wledge:
Asserted b y the initiator
when it
has completed
a data transfer op eration
Input/Output:
Asserted to indicate an input
op eration (relativ e to the initiator)
A tten tion: Asserted
by an initiator
when it
wishes to send a message to a target
Reset: Causes all device con trols to disconnect
from the bus and assume their start-up state
58